1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
11 #include "rk3xxx.dtsi"
14 compatible = "rockchip,rk3066a";
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
36 clock-latency = <40000>;
37 clocks = <&cru ARMCLK>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
48 compatible = "mmio-sram";
49 reg = <0x10080000 0x10000>;
52 ranges = <0 0x10080000 0x10000>;
55 compatible = "rockchip,rk3066-smp-sram";
61 compatible = "rockchip,rk3066-i2s";
62 reg = <0x10118000 0x2000>;
63 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2s0_bus>;
68 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
69 dma-names = "tx", "rx";
70 clock-names = "i2s_hclk", "i2s_clk";
71 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
72 rockchip,playback-channels = <8>;
73 rockchip,capture-channels = <2>;
74 #sound-dai-cells = <0>;
79 compatible = "rockchip,rk3066-i2s";
80 reg = <0x1011a000 0x2000>;
81 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2s1_bus>;
86 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
87 dma-names = "tx", "rx";
88 clock-names = "i2s_hclk", "i2s_clk";
89 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
90 rockchip,playback-channels = <2>;
91 rockchip,capture-channels = <2>;
92 #sound-dai-cells = <0>;
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x1011c000 0x2000>;
99 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s2_bus>;
104 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
108 rockchip,playback-channels = <2>;
109 rockchip,capture-channels = <2>;
110 #sound-dai-cells = <0>;
114 cru: clock-controller@20000000 {
115 compatible = "rockchip,rk3066a-cru";
116 reg = <0x20000000 0x1000>;
117 rockchip,grf = <&grf>;
121 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
122 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
123 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
124 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
125 assigned-clock-rates = <400000000>, <594000000>,
126 <300000000>, <150000000>,
127 <75000000>, <300000000>,
128 <150000000>, <75000000>;
132 compatible = "snps,dw-apb-timer-osc";
133 reg = <0x2000e000 0x100>;
134 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
136 clock-names = "timer", "pclk";
139 efuse: efuse@20010000 {
140 compatible = "rockchip,rk3066a-efuse";
141 reg = <0x20010000 0x4000>;
142 #address-cells = <1>;
144 clocks = <&cru PCLK_EFUSE>;
145 clock-names = "pclk_efuse";
147 cpu_leakage: cpu_leakage@17 {
153 compatible = "snps,dw-apb-timer-osc";
154 reg = <0x20038000 0x100>;
155 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
157 clock-names = "timer", "pclk";
161 compatible = "snps,dw-apb-timer-osc";
162 reg = <0x2003a000 0x100>;
163 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
165 clock-names = "timer", "pclk";
168 tsadc: tsadc@20060000 {
169 compatible = "rockchip,rk3066-tsadc";
170 reg = <0x20060000 0x100>;
171 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
172 clock-names = "saradc", "apb_pclk";
173 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
174 #io-channel-cells = <1>;
175 resets = <&cru SRST_TSADC>;
176 reset-names = "saradc-apb";
181 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
182 rockchip,grf = <&grf>;
183 #address-cells = <1>;
187 usbphy0: usb-phy@17c {
190 clocks = <&cru SCLK_OTGPHY0>;
191 clock-names = "phyclk";
195 usbphy1: usb-phy@188 {
198 clocks = <&cru SCLK_OTGPHY1>;
199 clock-names = "phyclk";
205 compatible = "rockchip,rk3066a-pinctrl";
206 rockchip,grf = <&grf>;
207 #address-cells = <1>;
211 gpio0: gpio0@20034000 {
212 compatible = "rockchip,gpio-bank";
213 reg = <0x20034000 0x100>;
214 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru PCLK_GPIO0>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
224 gpio1: gpio1@2003c000 {
225 compatible = "rockchip,gpio-bank";
226 reg = <0x2003c000 0x100>;
227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cru PCLK_GPIO1>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
237 gpio2: gpio2@2003e000 {
238 compatible = "rockchip,gpio-bank";
239 reg = <0x2003e000 0x100>;
240 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cru PCLK_GPIO2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
250 gpio3: gpio3@20080000 {
251 compatible = "rockchip,gpio-bank";
252 reg = <0x20080000 0x100>;
253 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cru PCLK_GPIO3>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
263 gpio4: gpio4@20084000 {
264 compatible = "rockchip,gpio-bank";
265 reg = <0x20084000 0x100>;
266 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&cru PCLK_GPIO4>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
276 gpio6: gpio6@2000a000 {
277 compatible = "rockchip,gpio-bank";
278 reg = <0x2000a000 0x100>;
279 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&cru PCLK_GPIO6>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
289 pcfg_pull_default: pcfg_pull_default {
290 bias-pull-pin-default;
293 pcfg_pull_none: pcfg_pull_none {
298 emac_xfer: emac-xfer {
299 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
300 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
301 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
302 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
303 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
304 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
305 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
306 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
309 emac_mdio: emac-mdio {
310 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
311 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
317 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
321 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
325 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
329 * The data pins are shared between nandc and emmc and
330 * not accessible through pinctrl. Also they should've
331 * been already set correctly by firmware, as
332 * flash/emmc is the boot-device.
337 i2c0_xfer: i2c0-xfer {
338 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
339 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
344 i2c1_xfer: i2c1-xfer {
345 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
346 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
351 i2c2_xfer: i2c2-xfer {
352 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
353 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
358 i2c3_xfer: i2c3-xfer {
359 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
360 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
365 i2c4_xfer: i2c4-xfer {
366 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
367 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
373 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
379 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
385 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
391 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
397 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
400 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
403 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
406 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
409 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
415 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
418 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
421 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
424 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
427 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
432 uart0_xfer: uart0-xfer {
433 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
434 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
437 uart0_cts: uart0-cts {
438 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
441 uart0_rts: uart0-rts {
442 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
447 uart1_xfer: uart1-xfer {
448 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
449 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
452 uart1_cts: uart1-cts {
453 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
456 uart1_rts: uart1-rts {
457 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
462 uart2_xfer: uart2-xfer {
463 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
464 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
466 /* no rts / cts for uart2 */
470 uart3_xfer: uart3-xfer {
471 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
472 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
475 uart3_cts: uart3-cts {
476 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
479 uart3_rts: uart3-rts {
480 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
486 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
490 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
494 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
498 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
501 sd0_bus1: sd0-bus-width1 {
502 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
505 sd0_bus4: sd0-bus-width4 {
506 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
507 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
508 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
509 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
515 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
519 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
523 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
527 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
530 sd1_bus1: sd1-bus-width1 {
531 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
534 sd1_bus4: sd1-bus-width4 {
535 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
536 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
537 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
538 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
544 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
545 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
546 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
547 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
548 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
549 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
550 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
551 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
552 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
558 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
559 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
560 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
561 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
562 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
563 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
569 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
570 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
571 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
572 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
573 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
574 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
581 compatible = "rockchip,rk3066-mali", "arm,mali-400";
582 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
592 interrupt-names = "gp",
602 power-domains = <&power RK3066_PD_GPU>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c0_xfer>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c1_xfer>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c2_xfer>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c3_xfer>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c4_xfer>;
631 clock-frequency = <50000000>;
634 max-frequency = <50000000>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
652 power: power-controller {
653 compatible = "rockchip,rk3066-power-controller";
654 #power-domain-cells = <1>;
655 #address-cells = <1>;
658 pd_vio@RK3066_PD_VIO {
659 reg = <RK3066_PD_VIO>;
660 clocks = <&cru ACLK_LCDC0>,
676 pm_qos = <&qos_lcdc0>,
684 pd_video@RK3066_PD_VIDEO {
685 reg = <RK3066_PD_VIDEO>;
686 clocks = <&cru ACLK_VDPU>,
693 pd_gpu@RK3066_PD_GPU {
694 reg = <RK3066_PD_GPU>;
695 clocks = <&cru ACLK_GPU>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pwm0_out>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&pwm1_out>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&pwm2_out>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pwm3_out>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
727 pinctrl-names = "default";
728 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
732 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
733 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
734 dma-names = "tx", "rx";
735 pinctrl-names = "default";
736 pinctrl-0 = <&uart0_xfer>;
740 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
741 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
742 dma-names = "tx", "rx";
743 pinctrl-names = "default";
744 pinctrl-0 = <&uart1_xfer>;
748 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
749 dmas = <&dmac2 6>, <&dmac2 7>;
750 dma-names = "tx", "rx";
751 pinctrl-names = "default";
752 pinctrl-0 = <&uart2_xfer>;
756 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
757 dmas = <&dmac2 8>, <&dmac2 9>;
758 dma-names = "tx", "rx";
759 pinctrl-names = "default";
760 pinctrl-0 = <&uart3_xfer>;
764 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
768 compatible = "rockchip,rk3066-emac";