arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include <dt-bindings/soc/rockchip,boot-mode.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         compatible = "rockchip,rk3036";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 mshc0 = &emmc;
  61                 mshc1 = &sdmmc;
  62                 mshc2 = &sdio;
  63                 serial0 = &uart0;
  64                 serial1 = &uart1;
  65                 serial2 = &uart2;
  66                 spi = &spi;
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72                 enable-method = "rockchip,rk3036-smp";
  73
  74                 cpu0: cpu@f00 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0xf00>;
  78                         resets = <&cru SRST_CORE0>;
  79                         operating-points = <
  80                                 /* KHz    uV */
  81                                  816000 1000000
  82                         >;
  83                         clock-latency = <40000>;
  84                         clocks = <&cru ARMCLK>;
  85                 };
  86
  87                 cpu1: cpu@f01 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a7";
  90                         reg = <0xf01>;
  91                         resets = <&cru SRST_CORE1>;
  92                 };
  93         };
  94
  95         amba {
  96                 compatible = "simple-bus";
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100
 101                 pdma: pdma@20078000 {
 102                         compatible = "arm,pl330", "arm,primecell";
 103                         reg = <0x20078000 0x4000>;
 104                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 106                         #dma-cells = <1>;
 107                         arm,pl330-broken-no-flushp;
 108                         clocks = <&cru ACLK_DMAC2>;
 109                         clock-names = "apb_pclk";
 110                 };
 111         };
 112
 113         arm-pmu {
 114                 compatible = "arm,cortex-a7-pmu";
 115                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 116                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 117                 interrupt-affinity = <&cpu0>, <&cpu1>;
 118         };
 119
 120         display-subsystem {
 121                 compatible = "rockchip,display-subsystem";
 122                 ports = <&vop_out>;
 123         };
 124
 125         timer {
 126                 compatible = "arm,armv7-timer";
 127                 arm,cpu-registers-not-fw-configured;
 128                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 131                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 132                 clock-frequency = <24000000>;
 133         };
 134
 135         xin24m: oscillator {
 136                 compatible = "fixed-clock";
 137                 clock-frequency = <24000000>;
 138                 clock-output-names = "xin24m";
 139                 #clock-cells = <0>;
 140         };
 141
 142         bus_intmem@10080000 {
 143                 compatible = "mmio-sram";
 144                 reg = <0x10080000 0x2000>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0x10080000 0x2000>;
 148
 149                 smp-sram@0 {
 150                         compatible = "rockchip,rk3066-smp-sram";
 151                         reg = <0x00 0x10>;
 152                 };
 153         };
 154
 155         gpu: gpu@10090000 {
 156                 compatible = "rockchip,rk3036-mali", "arm,mali-400";
 157                 reg = <0x10090000 0x10000>;
 158                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 162                 interrupt-names = "gp",
 163                                   "gpmmu",
 164                                   "pp0",
 165                                   "ppmmu0";
 166                 assigned-clocks = <&cru SCLK_GPU>;
 167                 assigned-clock-rates = <100000000>;
 168                 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 169                 clock-names = "core", "bus";
 170                 resets = <&cru SRST_GPU>;
 171                 status = "disabled";
 172         };
 173
 174         vop: vop@10118000 {
 175                 compatible = "rockchip,rk3036-vop";
 176                 reg = <0x10118000 0x19c>;
 177                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 179                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 180                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 181                 reset-names = "axi", "ahb", "dclk";
 182                 iommus = <&vop_mmu>;
 183                 status = "disabled";
 184
 185                 vop_out: port {
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         vop_out_hdmi: endpoint@0 {
 189                                 reg = <0>;
 190                                 remote-endpoint = <&hdmi_in_vop>;
 191                         };
 192                 };
 193         };
 194
 195         vop_mmu: iommu@10118300 {
 196                 compatible = "rockchip,iommu";
 197                 reg = <0x10118300 0x100>;
 198                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 199                 interrupt-names = "vop_mmu";
 200                 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 201                 clock-names = "aclk", "iface";
 202                 #iommu-cells = <0>;
 203                 status = "disabled";
 204         };
 205
 206         gic: interrupt-controller@10139000 {
 207                 compatible = "arm,gic-400";
 208                 interrupt-controller;
 209                 #interrupt-cells = <3>;
 210                 #address-cells = <0>;
 211
 212                 reg = <0x10139000 0x1000>,
 213                       <0x1013a000 0x2000>,
 214                       <0x1013c000 0x2000>,
 215                       <0x1013e000 0x2000>;
 216                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 217         };
 218
 219         usb_otg: usb@10180000 {
 220                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 221                                 "snps,dwc2";
 222                 reg = <0x10180000 0x40000>;
 223                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru HCLK_OTG0>;
 225                 clock-names = "otg";
 226                 dr_mode = "otg";
 227                 g-np-tx-fifo-size = <16>;
 228                 g-rx-fifo-size = <275>;
 229                 g-tx-fifo-size = <256 128 128 64 64 32>;
 230                 status = "disabled";
 231         };
 232
 233         usb_host: usb@101c0000 {
 234                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 235                                 "snps,dwc2";
 236                 reg = <0x101c0000 0x40000>;
 237                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&cru HCLK_OTG1>;
 239                 clock-names = "otg";
 240                 dr_mode = "host";
 241                 status = "disabled";
 242         };
 243
 244         emac: ethernet@10200000 {
 245                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 246                 reg = <0x10200000 0x4000>;
 247                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 rockchip,grf = <&grf>;
 251                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 252                 clock-names = "hclk", "macref", "macclk";
 253                 /*
 254                  * Fix the emac parent clock is DPLL instead of APLL.
 255                  * since that will cause some unstable things if the cpufreq
 256                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 257                  */
 258                 assigned-clocks = <&cru SCLK_MACPLL>;
 259                 assigned-clock-parents = <&cru PLL_DPLL>;
 260                 max-speed = <100>;
 261                 phy-mode = "rmii";
 262                 status = "disabled";
 263         };
 264
 265         sdmmc: dwmmc@10214000 {
 266                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 267                 reg = <0x10214000 0x4000>;
 268                 clock-frequency = <37500000>;
 269                 max-frequency = <37500000>;
 270                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 271                 clock-names = "biu", "ciu";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 274                 resets = <&cru SRST_MMC0>;
 275                 reset-names = "reset";
 276                 status = "disabled";
 277         };
 278
 279         sdio: dwmmc@10218000 {
 280                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 281                 reg = <0x10218000 0x4000>;
 282                 max-frequency = <37500000>;
 283                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 284                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 285                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 286                 fifo-depth = <0x100>;
 287                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 288                 resets = <&cru SRST_SDIO>;
 289                 reset-names = "reset";
 290                 status = "disabled";
 291         };
 292
 293         emmc: dwmmc@1021c000 {
 294                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 295                 reg = <0x1021c000 0x4000>;
 296                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 297                 bus-width = <8>;
 298                 cap-mmc-highspeed;
 299                 clock-frequency = <37500000>;
 300                 max-frequency = <37500000>;
 301                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 302                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 303                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 304                 default-sample-phase = <158>;
 305                 disable-wp;
 306                 dmas = <&pdma 12>;
 307                 dma-names = "rx-tx";
 308                 fifo-depth = <0x100>;
 309                 mmc-ddr-1_8v;
 310                 non-removable;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 313                 resets = <&cru SRST_EMMC>;
 314                 reset-names = "reset";
 315                 status = "disabled";
 316         };
 317
 318         i2s: i2s@10220000 {
 319                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 320                 reg = <0x10220000 0x4000>;
 321                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 clock-names = "i2s_clk", "i2s_hclk";
 325                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 326                 dmas = <&pdma 0>, <&pdma 1>;
 327                 dma-names = "tx", "rx";
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&i2s_bus>;
 330                 status = "disabled";
 331         };
 332
 333         cru: clock-controller@20000000 {
 334                 compatible = "rockchip,rk3036-cru";
 335                 reg = <0x20000000 0x1000>;
 336                 rockchip,grf = <&grf>;
 337                 #clock-cells = <1>;
 338                 #reset-cells = <1>;
 339                 assigned-clocks = <&cru PLL_GPLL>;
 340                 assigned-clock-rates = <594000000>;
 341         };
 342
 343         grf: syscon@20008000 {
 344                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 345                 reg = <0x20008000 0x1000>;
 346
 347                 reboot-mode {
 348                         compatible = "syscon-reboot-mode";
 349                         offset = <0x1d8>;
 350                         mode-normal = <BOOT_NORMAL>;
 351                         mode-recovery = <BOOT_RECOVERY>;
 352                         mode-bootloader = <BOOT_FASTBOOT>;
 353                         mode-loader = <BOOT_BL_DOWNLOAD>;
 354                 };
 355         };
 356
 357         acodec: acodec-ana@20030000 {
 358                 compatible = "rk3036-codec";
 359                 reg = <0x20030000 0x4000>;
 360                 rockchip,grf = <&grf>;
 361                 clock-names = "acodec_pclk";
 362                 clocks = <&cru PCLK_ACODEC>;
 363                 status = "disabled";
 364         };
 365
 366         hdmi: hdmi@20034000 {
 367                 compatible = "rockchip,rk3036-inno-hdmi";
 368                 reg = <0x20034000 0x4000>;
 369                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&cru  PCLK_HDMI>;
 371                 clock-names = "pclk";
 372                 rockchip,grf = <&grf>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&hdmi_ctl>;
 375                 status = "disabled";
 376
 377                 hdmi_in: port {
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         hdmi_in_vop: endpoint@0 {
 381                                 reg = <0>;
 382                                 remote-endpoint = <&vop_out_hdmi>;
 383                         };
 384                 };
 385         };
 386
 387         timer: timer@20044000 {
 388                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 389                 reg = <0x20044000 0x20>;
 390                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 392                 clock-names = "timer", "pclk";
 393         };
 394
 395         pwm0: pwm@20050000 {
 396                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 397                 reg = <0x20050000 0x10>;
 398                 #pwm-cells = <3>;
 399                 clocks = <&cru PCLK_PWM>;
 400                 clock-names = "pwm";
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&pwm0_pin>;
 403                 status = "disabled";
 404         };
 405
 406         pwm1: pwm@20050010 {
 407                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 408                 reg = <0x20050010 0x10>;
 409                 #pwm-cells = <3>;
 410                 clocks = <&cru PCLK_PWM>;
 411                 clock-names = "pwm";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&pwm1_pin>;
 414                 status = "disabled";
 415         };
 416
 417         pwm2: pwm@20050020 {
 418                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 419                 reg = <0x20050020 0x10>;
 420                 #pwm-cells = <3>;
 421                 clocks = <&cru PCLK_PWM>;
 422                 clock-names = "pwm";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&pwm2_pin>;
 425                 status = "disabled";
 426         };
 427
 428         pwm3: pwm@20050030 {
 429                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 430                 reg = <0x20050030 0x10>;
 431                 #pwm-cells = <2>;
 432                 clocks = <&cru PCLK_PWM>;
 433                 clock-names = "pwm";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pwm3_pin>;
 436                 status = "disabled";
 437         };
 438
 439         i2c1: i2c@20056000 {
 440                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 441                 reg = <0x20056000 0x1000>;
 442                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clock-names = "i2c";
 446                 clocks = <&cru PCLK_I2C1>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&i2c1_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         i2c2: i2c@2005a000 {
 453                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 454                 reg = <0x2005a000 0x1000>;
 455                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 clock-names = "i2c";
 459                 clocks = <&cru PCLK_I2C2>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&i2c2_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         uart0: serial@20060000 {
 466                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 467                 reg = <0x20060000 0x100>;
 468                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 clock-frequency = <24000000>;
 472                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 473                 clock-names = "baudclk", "apb_pclk";
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 476                 status = "disabled";
 477         };
 478
 479         uart1: serial@20064000 {
 480                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 481                 reg = <0x20064000 0x100>;
 482                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 clock-frequency = <24000000>;
 486                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 487                 clock-names = "baudclk", "apb_pclk";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart1_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart2: serial@20068000 {
 494                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 495                 reg = <0x20068000 0x100>;
 496                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 clock-frequency = <24000000>;
 500                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&uart2_xfer>;
 504                 status = "disabled";
 505         };
 506
 507         i2c0: i2c@20072000 {
 508                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 509                 reg = <0x20072000 0x1000>;
 510                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 clock-names = "i2c";
 514                 clocks = <&cru PCLK_I2C0>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&i2c0_xfer>;
 517                 status = "disabled";
 518         };
 519
 520         spi: spi@20074000 {
 521                 compatible = "rockchip,rockchip-spi";
 522                 reg = <0x20074000 0x1000>;
 523                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 525                 clock-names = "apb-pclk","spi_pclk";
 526                 dmas = <&pdma 8>, <&pdma 9>;
 527                 dma-names = "tx", "rx";
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 status = "disabled";
 533         };
 534
 535         pinctrl: pinctrl {
 536                 compatible = "rockchip,rk3036-pinctrl";
 537                 rockchip,grf = <&grf>;
 538                 #address-cells = <1>;
 539                 #size-cells = <1>;
 540                 ranges;
 541
 542                 gpio0: gpio0@2007c000 {
 543                         compatible = "rockchip,gpio-bank";
 544                         reg = <0x2007c000 0x100>;
 545                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&cru PCLK_GPIO0>;
 547
 548                         gpio-controller;
 549                         #gpio-cells = <2>;
 550
 551                         interrupt-controller;
 552                         #interrupt-cells = <2>;
 553                 };
 554
 555                 gpio1: gpio1@20080000 {
 556                         compatible = "rockchip,gpio-bank";
 557                         reg = <0x20080000 0x100>;
 558                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&cru PCLK_GPIO1>;
 560
 561                         gpio-controller;
 562                         #gpio-cells = <2>;
 563
 564                         interrupt-controller;
 565                         #interrupt-cells = <2>;
 566                 };
 567
 568                 gpio2: gpio2@20084000 {
 569                         compatible = "rockchip,gpio-bank";
 570                         reg = <0x20084000 0x100>;
 571                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&cru PCLK_GPIO2>;
 573
 574                         gpio-controller;
 575                         #gpio-cells = <2>;
 576
 577                         interrupt-controller;
 578                         #interrupt-cells = <2>;
 579                 };
 580
 581                 pcfg_pull_default: pcfg_pull_default {
 582                         bias-pull-pin-default;
 583                 };
 584
 585                 pcfg_pull_none: pcfg-pull-none {
 586                         bias-disable;
 587                 };
 588
 589                 pwm0 {
 590                         pwm0_pin: pwm0-pin {
 591                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 592                         };
 593                 };
 594
 595                 pwm1 {
 596                         pwm1_pin: pwm1-pin {
 597                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 598                         };
 599                 };
 600
 601                 pwm2 {
 602                         pwm2_pin: pwm2-pin {
 603                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 604                         };
 605                 };
 606
 607                 pwm3 {
 608                         pwm3_pin: pwm3-pin {
 609                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 610                         };
 611                 };
 612
 613                 sdmmc {
 614                         sdmmc_clk: sdmmc-clk {
 615                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 616                         };
 617
 618                         sdmmc_cmd: sdmmc-cmd {
 619                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 620                         };
 621
 622                         sdmmc_cd: sdmmc-cd {
 623                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 624                         };
 625
 626                         sdmmc_bus1: sdmmc-bus1 {
 627                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 628                         };
 629
 630                         sdmmc_bus4: sdmmc-bus4 {
 631                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 632                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 633                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 634                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 635                         };
 636                 };
 637
 638                 sdio {
 639                         sdio_bus1: sdio-bus1 {
 640                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 641                         };
 642
 643                         sdio_bus4: sdio-bus4 {
 644                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 645                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 646                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 647                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 648                         };
 649
 650                         sdio_cmd: sdio-cmd {
 651                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 652                         };
 653
 654                         sdio_clk: sdio-clk {
 655                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 656                         };
 657                 };
 658
 659                 emmc {
 660                         /*
 661                          * We run eMMC at max speed; bump up drive strength.
 662                          * We also have external pulls, so disable the internal ones.
 663                          */
 664                         emmc_clk: emmc-clk {
 665                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 666                         };
 667
 668                         emmc_cmd: emmc-cmd {
 669                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 670                         };
 671
 672                         emmc_bus8: emmc-bus8 {
 673                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 674                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 675                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 676                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 677                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 678                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 679                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 680                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 681                         };
 682                 };
 683
 684                 emac {
 685                         emac_xfer: emac-xfer {
 686                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 687                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 688                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 689                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 690                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 691                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 692                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 693                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 694                         };
 695
 696                         emac_mdio: emac-mdio {
 697                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 698                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 699                         };
 700                 };
 701
 702                 i2c0 {
 703                         i2c0_xfer: i2c0-xfer {
 704                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 705                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 706                         };
 707                 };
 708
 709                 i2c1 {
 710                         i2c1_xfer: i2c1-xfer {
 711                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 712                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 713                         };
 714                 };
 715
 716                 i2c2 {
 717                         i2c2_xfer: i2c2-xfer {
 718                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 719                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 720                         };
 721                 };
 722
 723                 i2s {
 724                         i2s_bus: i2s-bus {
 725                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 726                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 727                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 728                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 729                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 730                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 731                         };
 732                 };
 733
 734                 hdmi {
 735                         hdmi_ctl: hdmi-ctl {
 736                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 737                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 738                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 739                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 740                         };
 741                 };
 742
 743                 uart0 {
 744                         uart0_xfer: uart0-xfer {
 745                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 746                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 747                         };
 748
 749                         uart0_cts: uart0-cts {
 750                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 751                         };
 752
 753                         uart0_rts: uart0-rts {
 754                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 755                         };
 756                 };
 757
 758                 uart1 {
 759                         uart1_xfer: uart1-xfer {
 760                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 761                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 762                         };
 763                         /* no rts / cts for uart1 */
 764                 };
 765
 766                 uart2 {
 767                         uart2_xfer: uart2-xfer {
 768                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 769                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 770                         };
 771                         /* no rts / cts for uart2 */
 772                 };
 773
 774                 spi {
 775                         spi_txd:spi-txd {
 776                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 777                         };
 778
 779                         spi_rxd:spi-rxd {
 780                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 781                         };
 782
 783                         spi_clk:spi-clk {
 784                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 785                         };
 786
 787                         spi_cs0:spi-cs0 {
 788                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 789
 790                         };
 791
 792                         spi_cs1:spi-cs1 {
 793                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 794
 795                         };
 796                 };
 797         };
 798 };