arch/arm/boot/dts/rk1108.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/clock/rv1108-cru.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 / {
  47         #address-cells = <1>;
  48         #size-cells = <1>;
  49
  50         compatible = "rockchip,rk1108";
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@f00 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0xf00>;
  68                 };
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a7-pmu";
  73                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv7-timer";
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  80                 clock-frequency = <24000000>;
  81         };
  82
  83         xin24m: oscillator {
  84                 compatible = "fixed-clock";
  85                 clock-frequency = <24000000>;
  86                 clock-output-names = "xin24m";
  87                 #clock-cells = <0>;
  88         };
  89
  90         amba {
  91                 compatible = "simple-bus";
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 pdma: pdma@102a0000 {
  97                         compatible = "arm,pl330", "arm,primecell";
  98                         reg = <0x102a0000 0x4000>;
  99                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 100                         #dma-cells = <1>;
 101                         arm,pl330-broken-no-flushp;
 102                         clocks = <&cru ACLK_DMAC>;
 103                         clock-names = "apb_pclk";
 104                 };
 105         };
 106
 107         bus_intmem@10080000 {
 108                 compatible = "mmio-sram";
 109                 reg = <0x10080000 0x2000>;
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges = <0 0x10080000 0x2000>;
 113         };
 114
 115         uart2: serial@10210000 {
 116                 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
 117                 reg = <0x10210000 0x100>;
 118                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 119                 reg-shift = <2>;
 120                 reg-io-width = <4>;
 121                 clock-frequency = <24000000>;
 122                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 123                 clock-names = "baudclk", "apb_pclk";
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&uart2m0_xfer>;
 126                 status = "disabled";
 127         };
 128
 129         uart1: serial@10220000 {
 130                 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
 131                 reg = <0x10220000 0x100>;
 132                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 133                 reg-shift = <2>;
 134                 reg-io-width = <4>;
 135                 clock-frequency = <24000000>;
 136                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 137                 clock-names = "baudclk", "apb_pclk";
 138                 pinctrl-names = "default";
 139                 pinctrl-0 = <&uart1_xfer>;
 140                 status = "disabled";
 141         };
 142
 143         uart0: serial@10230000 {
 144                 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
 145                 reg = <0x10230000 0x100>;
 146                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 147                 reg-shift = <2>;
 148                 reg-io-width = <4>;
 149                 clock-frequency = <24000000>;
 150                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 151                 clock-names = "baudclk", "apb_pclk";
 152                 pinctrl-names = "default";
 153                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 154                 status = "disabled";
 155         };
 156
 157         grf: syscon@10300000 {
 158                 compatible = "rockchip,rk1108-grf", "syscon";
 159                 reg = <0x10300000 0x1000>;
 160         };
 161
 162         pmugrf: syscon@20060000 {
 163                 compatible = "rockchip,rk1108-pmugrf", "syscon";
 164                 reg = <0x20060000 0x1000>;
 165         };
 166
 167         cru: clock-controller@20200000 {
 168                 compatible = "rockchip,rk1108-cru";
 169                 reg = <0x20200000 0x1000>;
 170                 rockchip,grf = <&grf>;
 171                 #clock-cells = <1>;
 172                 #reset-cells = <1>;
 173         };
 174
 175         emmc: dwmmc@30110000 {
 176                 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 177                 clock-freq-min-max = <400000 150000000>;
 178                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 179                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 180                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 181                 fifo-depth = <0x100>;
 182                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 183                 reg = <0x30110000 0x4000>;
 184                 status = "disabled";
 185         };
 186
 187         sdio: dwmmc@30120000 {
 188                 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 189                 clock-freq-min-max = <400000 150000000>;
 190                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 191                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 192                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 193                 fifo-depth = <0x100>;
 194                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 195                 reg = <0x30120000 0x4000>;
 196                 status = "disabled";
 197         };
 198
 199         sdmmc: dwmmc@30130000 {
 200                 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 201                 clock-freq-min-max = <400000 100000000>;
 202                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 203                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 204                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 205                 fifo-depth = <0x100>;
 206                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 207                 reg = <0x30130000 0x4000>;
 208                 status = "disabled";
 209         };
 210
 211         gic: interrupt-controller@32010000 {
 212                 compatible = "arm,gic-400";
 213                 interrupt-controller;
 214                 #interrupt-cells = <3>;
 215                 #address-cells = <0>;
 216
 217                 reg = <0x32011000 0x1000>,
 218                       <0x32012000 0x2000>,
 219                       <0x32014000 0x2000>,
 220                       <0x32016000 0x2000>;
 221                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 222         };
 223
 224         pinctrl: pinctrl {
 225                 compatible = "rockchip,rv1108-pinctrl";
 226                 rockchip,grf = <&grf>;
 227                 rockchip,pmu = <&pmugrf>;
 228                 #address-cells = <1>;
 229                 #size-cells = <1>;
 230                 ranges;
 231
 232                 gpio0: gpio0@20030000 {
 233                         compatible = "rockchip,gpio-bank";
 234                         reg = <0x20030000 0x100>;
 235                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&xin24m>;
 237
 238                         gpio-controller;
 239                         #gpio-cells = <2>;
 240
 241                         interrupt-controller;
 242                         #interrupt-cells = <2>;
 243                 };
 244
 245                 gpio1: gpio1@10310000 {
 246                         compatible = "rockchip,gpio-bank";
 247                         reg = <0x10310000 0x100>;
 248                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&xin24m>;
 250
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 gpio2: gpio2@10320000 {
 259                         compatible = "rockchip,gpio-bank";
 260                         reg = <0x10320000 0x100>;
 261                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&xin24m>;
 263
 264                         gpio-controller;
 265                         #gpio-cells = <2>;
 266
 267                         interrupt-controller;
 268                         #interrupt-cells = <2>;
 269                 };
 270
 271                 gpio3: gpio3@10330000 {
 272                         compatible = "rockchip,gpio-bank";
 273                         reg = <0x10330000 0x100>;
 274                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&xin24m>;
 276
 277                         gpio-controller;
 278                         #gpio-cells = <2>;
 279
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 pcfg_pull_up: pcfg-pull-up {
 285                         bias-pull-up;
 286                 };
 287
 288                 pcfg_pull_down: pcfg-pull-down {
 289                         bias-pull-down;
 290                 };
 291
 292                 pcfg_pull_none: pcfg-pull-none {
 293                         bias-disable;
 294                 };
 295
 296                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 297                         drive-strength = <8>;
 298                 };
 299
 300                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 301                         drive-strength = <12>;
 302                 };
 303
 304                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 305                         bias-pull-up;
 306                         drive-strength = <8>;
 307                 };
 308
 309                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 310                         drive-strength = <4>;
 311                 };
 312
 313                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 314                         bias-pull-up;
 315                         drive-strength = <4>;
 316                 };
 317
 318                 pcfg_output_high: pcfg-output-high {
 319                         output-high;
 320                 };
 321
 322                 pcfg_output_low: pcfg-output-low {
 323                         output-low;
 324                 };
 325
 326                 pcfg_input_high: pcfg-input-high {
 327                         bias-pull-up;
 328                         input-enable;
 329                 };
 330
 331                 i2c1 {
 332                         i2c1_xfer: i2c1-xfer {
 333                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 334                                                 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
 335                         };
 336                 };
 337
 338                 i2c2m1 {
 339                         i2c2m1_xfer: i2c2m1-xfer {
 340                                 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
 341                                                 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
 342                         };
 343
 344                         i2c2m1_gpio: i2c2m1-gpio {
 345                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
 346                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 347                         };
 348                 };
 349
 350                 i2c2m05v {
 351                         i2c2m05v_xfer: i2c2m05v-xfer {
 352                                 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
 353                                                 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
 354                         };
 355
 356                         i2c2m05v_gpio: i2c2m05v-gpio {
 357                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
 358                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 359                         };
 360                 };
 361
 362                 i2c3 {
 363                         i2c3_xfer: i2c3-xfer {
 364                                 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 365                                                 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
 366                         };
 367                 };
 368
 369                 sdmmc {
 370                         sdmmc_clk: sdmmc-clk {
 371                                 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 372                         };
 373
 374                         sdmmc_cmd: sdmmc-cmd {
 375                                 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 376                         };
 377
 378                         sdmmc_cd: sdmmc-cd {
 379                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 380                         };
 381
 382                         sdmmc_bus1: sdmmc-bus1 {
 383                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 384                         };
 385
 386                         sdmmc_bus4: sdmmc-bus4 {
 387                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 388                                                 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 389                                                 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 390                                                 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 391                         };
 392                 };
 393
 394                 uart0 {
 395                         uart0_xfer: uart0-xfer {
 396                                 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
 397                                                 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
 398                         };
 399
 400                         uart0_cts: uart0-cts {
 401                                 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
 402                         };
 403
 404                         uart0_rts: uart0-rts {
 405                                 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
 406                         };
 407
 408                         uart0_rts_gpio: uart0-rts-gpio {
 409                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 410                         };
 411                 };
 412
 413                 uart1 {
 414                         uart1_xfer: uart1-xfer {
 415                                 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 416                                                 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 417                         };
 418
 419                         uart1_cts: uart1-cts {
 420                                 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 421                         };
 422
 423                         uart1_rts: uart1-rts {
 424                                 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 425                         };
 426                 };
 427
 428                 uart2m0 {
 429                         uart2m0_xfer: uart2m0-xfer {
 430                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
 431                                                 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 432                         };
 433                 };
 434
 435                 uart2m1 {
 436                         uart2m1_xfer: uart2m1-xfer {
 437                                 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
 438                                                 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
 439                         };
 440                 };
 441
 442                 uart2_5v {
 443                         uart2_5v_cts: uart2_5v-cts {
 444                                 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
 445                         };
 446
 447                         uart2_5v_rts: uart2_5v-rts {
 448                                 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
 449                         };
 450                 };
 451         };
 452 };