arch/arm/boot/dts/r9a06g032.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Europe Limited
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
  11
  12 / {
  13         compatible = "renesas,r9a06g032";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24                         reg = <0>;
  25                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
  26                 };
  27
  28                 cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <1>;
  32                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
  33                         enable-method = "renesas,r9a06g032-smp";
  34                         cpu-release-addr = <0 0x4000c204>;
  35                 };
  36         };
  37
  38         ext_jtag_clk: extjtagclk {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <0>;
  42         };
  43
  44         ext_mclk: extmclk {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47                 clock-frequency = <40000000>;
  48         };
  49
  50         ext_rgmii_ref: extrgmiiref {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-clock";
  53                 clock-frequency = <0>;
  54         };
  55
  56         ext_rtc_clk: extrtcclk {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <0>;
  60         };
  61
  62         soc {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 interrupt-parent = <&gic>;
  67                 ranges;
  68
  69                 sysctrl: system-controller@4000c000 {
  70                         compatible = "renesas,r9a06g032-sysctrl";
  71                         reg = <0x4000c000 0x1000>;
  72                         status = "okay";
  73                         #clock-cells = <1>;
  74
  75                         clocks = <&ext_mclk>, <&ext_rtc_clk>,
  76                                         <&ext_jtag_clk>, <&ext_rgmii_ref>;
  77                         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
  78                 };
  79
  80                 uart0: serial@40060000 {
  81                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
  82                         reg = <0x40060000 0x400>;
  83                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  84                         reg-shift = <2>;
  85                         reg-io-width = <4>;
  86                         clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
  87                         clock-names = "baudclk", "apb_pclk";
  88                         status = "disabled";
  89                 };
  90
  91                 uart1: serial@40061000 {
  92                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
  93                         reg = <0x40061000 0x400>;
  94                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  95                         reg-shift = <2>;
  96                         reg-io-width = <4>;
  97                         clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
  98                         clock-names = "baudclk", "apb_pclk";
  99                         status = "disabled";
 100                 };
 101
 102                 uart2: serial@40062000 {
 103                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 104                         reg = <0x40062000 0x400>;
 105                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 106                         reg-shift = <2>;
 107                         reg-io-width = <4>;
 108                         clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
 109                         clock-names = "baudclk", "apb_pclk";
 110                         status = "disabled";
 111                 };
 112
 113                 uart3: serial@50000000 {
 114                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 115                         reg = <0x50000000 0x400>;
 116                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 117                         reg-shift = <2>;
 118                         reg-io-width = <4>;
 119                         clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
 120                         clock-names = "baudclk", "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 uart4: serial@50001000 {
 125                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 126                         reg = <0x50001000 0x400>;
 127                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 128                         reg-shift = <2>;
 129                         reg-io-width = <4>;
 130                         clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
 131                         clock-names = "baudclk", "apb_pclk";
 132                         status = "disabled";
 133                 };
 134
 135                 uart5: serial@50002000 {
 136                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 137                         reg = <0x50002000 0x400>;
 138                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 139                         reg-shift = <2>;
 140                         reg-io-width = <4>;
 141                         clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
 142                         clock-names = "baudclk", "apb_pclk";
 143                         status = "disabled";
 144                 };
 145
 146                 uart6: serial@50003000 {
 147                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 148                         reg = <0x50003000 0x400>;
 149                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 150                         reg-shift = <2>;
 151                         reg-io-width = <4>;
 152                         clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
 153                         clock-names = "baudclk", "apb_pclk";
 154                         status = "disabled";
 155                 };
 156
 157                 uart7: serial@50004000 {
 158                         compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 159                         reg = <0x50004000 0x400>;
 160                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 161                         reg-shift = <2>;
 162                         reg-io-width = <4>;
 163                         clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
 164                         clock-names = "baudclk", "apb_pclk";
 165                         status = "disabled";
 166                 };
 167
 168                 gic: gic@44101000 {
 169                         compatible = "arm,cortex-a7-gic", "arm,gic-400";
 170                         interrupt-controller;
 171                         #interrupt-cells = <3>;
 172                         reg = <0x44101000 0x1000>, /* Distributer */
 173                               <0x44102000 0x2000>, /* CPU interface */
 174                               <0x44104000 0x2000>, /* Virt interface control */
 175                               <0x44106000 0x2000>; /* Virt CPU interface */
 176                         interrupts =
 177                                 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 178                 };
 179         };
 180
 181         timer {
 182                 compatible = "arm,cortex-a7-timer",
 183                              "arm,armv7-timer";
 184                 interrupt-parent = <&gic>;
 185                 arm,cpu-registers-not-fw-configured;
 186                 always-on;
 187                 interrupts =
 188                         <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 189                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 190                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 191                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 192         };
 193 };