arch/arm/boot/dts/r9a06g032.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Europe Limited
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "renesas,r9a06g032";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a7";
  23                         reg = <0>;
  24                         clocks = <&sysctrl 84>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <1>;
  31                         clocks = <&sysctrl 84>;
  32                         enable-method = "renesas,r9a06g032-smp";
  33                         cpu-release-addr = <0 0x4000c204>;
  34                 };
  35         };
  36
  37         ext_jtag_clk: extjtagclk {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40                 clock-frequency = <0>;
  41         };
  42
  43         ext_mclk: extmclk {
  44                 #clock-cells = <0>;
  45                 compatible = "fixed-clock";
  46                 clock-frequency = <40000000>;
  47         };
  48
  49         ext_rgmii_ref: extrgmiiref {
  50                 #clock-cells = <0>;
  51                 compatible = "fixed-clock";
  52                 clock-frequency = <0>;
  53         };
  54
  55         ext_rtc_clk: extrtcclk {
  56                 #clock-cells = <0>;
  57                 compatible = "fixed-clock";
  58                 clock-frequency = <0>;
  59         };
  60
  61         soc {
  62                 compatible = "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 interrupt-parent = <&gic>;
  66                 ranges;
  67
  68                 sysctrl: system-controller@4000c000 {
  69                         compatible = "renesas,r9a06g032-sysctrl";
  70                         reg = <0x4000c000 0x1000>;
  71                         status = "okay";
  72                         #clock-cells = <1>;
  73
  74                         clocks = <&ext_mclk>, <&ext_rtc_clk>,
  75                                         <&ext_jtag_clk>, <&ext_rgmii_ref>;
  76                         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
  77                 };
  78
  79                 uart0: serial@40060000 {
  80                         compatible = "snps,dw-apb-uart";
  81                         reg = <0x40060000 0x400>;
  82                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  83                         reg-shift = <2>;
  84                         reg-io-width = <4>;
  85                         clocks = <&sysctrl 146>;
  86                         clock-names = "baudclk";
  87                         status = "disabled";
  88                 };
  89
  90                 gic: gic@44101000 {
  91                         compatible = "arm,cortex-a7-gic", "arm,gic-400";
  92                         interrupt-controller;
  93                         #interrupt-cells = <3>;
  94                         reg = <0x44101000 0x1000>, /* Distributer */
  95                               <0x44102000 0x2000>, /* CPU interface */
  96                               <0x44104000 0x2000>, /* Virt interface control */
  97                               <0x44106000 0x2000>; /* Virt CPU interface */
  98                         interrupts =
  99                                 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 100                 };
 101         };
 102
 103         timer {
 104                 compatible = "arm,cortex-a7-timer",
 105                              "arm,armv7-timer";
 106                 interrupt-parent = <&gic>;
 107                 arm,cpu-registers-not-fw-configured;
 108                 always-on;
 109                 interrupts =
 110                         <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 111                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 112                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 113                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 114         };
 115 };