arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58         };
  59
  60         L2_CA7: cache-controller@1 {
  61                 compatible = "cache";
  62                 power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                 cache-unified;
  64                 cache-level = <2>;
  65         };
  66
  67         gic: interrupt-controller@f1001000 {
  68                 compatible = "arm,gic-400";
  69                 #interrupt-cells = <3>;
  70                 #address-cells = <0>;
  71                 interrupt-controller;
  72                 reg = <0 0xf1001000 0 0x1000>,
  73                         <0 0xf1002000 0 0x1000>,
  74                         <0 0xf1004000 0 0x2000>,
  75                         <0 0xf1006000 0 0x2000>;
  76                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  77         };
  78
  79         gpio0: gpio@e6050000 {
  80                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  81                 reg = <0 0xe6050000 0 0x50>;
  82                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  83                 #gpio-cells = <2>;
  84                 gpio-controller;
  85                 gpio-ranges = <&pfc 0 0 32>;
  86                 #interrupt-cells = <2>;
  87                 interrupt-controller;
  88                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  89                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  90         };
  91
  92         gpio1: gpio@e6051000 {
  93                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  94                 reg = <0 0xe6051000 0 0x50>;
  95                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 32 26>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 102                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 103         };
 104
 105         gpio2: gpio@e6052000 {
 106                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 107                 reg = <0 0xe6052000 0 0x50>;
 108                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 gpio-ranges = <&pfc 0 64 32>;
 112                 #interrupt-cells = <2>;
 113                 interrupt-controller;
 114                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 115                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 116         };
 117
 118         gpio3: gpio@e6053000 {
 119                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 120                 reg = <0 0xe6053000 0 0x50>;
 121                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 96 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 128                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 129         };
 130
 131         gpio4: gpio@e6054000 {
 132                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 133                 reg = <0 0xe6054000 0 0x50>;
 134                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 128 32>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 141                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 28>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 154                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 155         };
 156
 157         gpio6: gpio@e6055400 {
 158                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 159                 reg = <0 0xe6055400 0 0x50>;
 160                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 161                 #gpio-cells = <2>;
 162                 gpio-controller;
 163                 gpio-ranges = <&pfc 0 192 26>;
 164                 #interrupt-cells = <2>;
 165                 interrupt-controller;
 166                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 167                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 168         };
 169
 170         cmt0: timer@ffca0000 {
 171                 compatible = "renesas,cmt-48-gen2";
 172                 reg = <0 0xffca0000 0 0x1004>;
 173                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 176                 clock-names = "fck";
 177                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 178
 179                 renesas,channels-mask = <0x60>;
 180
 181                 status = "disabled";
 182         };
 183
 184         cmt1: timer@e6130000 {
 185                 compatible = "renesas,cmt-48-gen2";
 186                 reg = <0 0xe6130000 0 0x1004>;
 187                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 196                 clock-names = "fck";
 197                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 198
 199                 renesas,channels-mask = <0xff>;
 200
 201                 status = "disabled";
 202         };
 203
 204         timer {
 205                 compatible = "arm,armv7-timer";
 206                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 207                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 210         };
 211
 212         irqc0: interrupt-controller@e61c0000 {
 213                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 214                 #interrupt-cells = <2>;
 215                 interrupt-controller;
 216                 reg = <0 0xe61c0000 0 0x200>;
 217                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 228                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 229         };
 230
 231         pfc: pin-controller@e6060000 {
 232                 compatible = "renesas,pfc-r8a7794";
 233                 reg = <0 0xe6060000 0 0x11c>;
 234         };
 235
 236         dmac0: dma-controller@e6700000 {
 237                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 238                 reg = <0 0xe6700000 0 0x20000>;
 239                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 240                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 255                 interrupt-names = "error",
 256                                 "ch0", "ch1", "ch2", "ch3",
 257                                 "ch4", "ch5", "ch6", "ch7",
 258                                 "ch8", "ch9", "ch10", "ch11",
 259                                 "ch12", "ch13", "ch14";
 260                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 261                 clock-names = "fck";
 262                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 263                 #dma-cells = <1>;
 264                 dma-channels = <15>;
 265         };
 266
 267         dmac1: dma-controller@e6720000 {
 268                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 269                 reg = <0 0xe6720000 0 0x20000>;
 270                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 271                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 286                 interrupt-names = "error",
 287                                 "ch0", "ch1", "ch2", "ch3",
 288                                 "ch4", "ch5", "ch6", "ch7",
 289                                 "ch8", "ch9", "ch10", "ch11",
 290                                 "ch12", "ch13", "ch14";
 291                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 292                 clock-names = "fck";
 293                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 294                 #dma-cells = <1>;
 295                 dma-channels = <15>;
 296         };
 297
 298         scifa0: serial@e6c40000 {
 299                 compatible = "renesas,scifa-r8a7794",
 300                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 301                 reg = <0 0xe6c40000 0 64>;
 302                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 304                 clock-names = "fck";
 305                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 306                 dma-names = "tx", "rx";
 307                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 308                 status = "disabled";
 309         };
 310
 311         scifa1: serial@e6c50000 {
 312                 compatible = "renesas,scifa-r8a7794",
 313                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 314                 reg = <0 0xe6c50000 0 64>;
 315                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 317                 clock-names = "fck";
 318                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 319                 dma-names = "tx", "rx";
 320                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 321                 status = "disabled";
 322         };
 323
 324         scifa2: serial@e6c60000 {
 325                 compatible = "renesas,scifa-r8a7794",
 326                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 327                 reg = <0 0xe6c60000 0 64>;
 328                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 330                 clock-names = "fck";
 331                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 332                 dma-names = "tx", "rx";
 333                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 334                 status = "disabled";
 335         };
 336
 337         scifa3: serial@e6c70000 {
 338                 compatible = "renesas,scifa-r8a7794",
 339                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 340                 reg = <0 0xe6c70000 0 64>;
 341                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 343                 clock-names = "fck";
 344                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 345                 dma-names = "tx", "rx";
 346                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 347                 status = "disabled";
 348         };
 349
 350         scifa4: serial@e6c78000 {
 351                 compatible = "renesas,scifa-r8a7794",
 352                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 353                 reg = <0 0xe6c78000 0 64>;
 354                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 356                 clock-names = "fck";
 357                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 358                 dma-names = "tx", "rx";
 359                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 360                 status = "disabled";
 361         };
 362
 363         scifa5: serial@e6c80000 {
 364                 compatible = "renesas,scifa-r8a7794",
 365                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 366                 reg = <0 0xe6c80000 0 64>;
 367                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 369                 clock-names = "fck";
 370                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 371                 dma-names = "tx", "rx";
 372                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 373                 status = "disabled";
 374         };
 375
 376         scifb0: serial@e6c20000 {
 377                 compatible = "renesas,scifb-r8a7794",
 378                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 379                 reg = <0 0xe6c20000 0 64>;
 380                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 382                 clock-names = "fck";
 383                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 384                 dma-names = "tx", "rx";
 385                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 386                 status = "disabled";
 387         };
 388
 389         scifb1: serial@e6c30000 {
 390                 compatible = "renesas,scifb-r8a7794",
 391                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 392                 reg = <0 0xe6c30000 0 64>;
 393                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 395                 clock-names = "fck";
 396                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 397                 dma-names = "tx", "rx";
 398                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 399                 status = "disabled";
 400         };
 401
 402         scifb2: serial@e6ce0000 {
 403                 compatible = "renesas,scifb-r8a7794",
 404                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 405                 reg = <0 0xe6ce0000 0 64>;
 406                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 408                 clock-names = "fck";
 409                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 410                 dma-names = "tx", "rx";
 411                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 412                 status = "disabled";
 413         };
 414
 415         scif0: serial@e6e60000 {
 416                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 417                              "renesas,scif";
 418                 reg = <0 0xe6e60000 0 64>;
 419                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 421                          <&scif_clk>;
 422                 clock-names = "fck", "brg_int", "scif_clk";
 423                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 424                 dma-names = "tx", "rx";
 425                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 426                 status = "disabled";
 427         };
 428
 429         scif1: serial@e6e68000 {
 430                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 431                              "renesas,scif";
 432                 reg = <0 0xe6e68000 0 64>;
 433                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 435                          <&scif_clk>;
 436                 clock-names = "fck", "brg_int", "scif_clk";
 437                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 438                 dma-names = "tx", "rx";
 439                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 440                 status = "disabled";
 441         };
 442
 443         scif2: serial@e6e58000 {
 444                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 445                              "renesas,scif";
 446                 reg = <0 0xe6e58000 0 64>;
 447                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 449                          <&scif_clk>;
 450                 clock-names = "fck", "brg_int", "scif_clk";
 451                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 452                 dma-names = "tx", "rx";
 453                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 454                 status = "disabled";
 455         };
 456
 457         scif3: serial@e6ea8000 {
 458                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 459                              "renesas,scif";
 460                 reg = <0 0xe6ea8000 0 64>;
 461                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 463                          <&scif_clk>;
 464                 clock-names = "fck", "brg_int", "scif_clk";
 465                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 466                 dma-names = "tx", "rx";
 467                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 468                 status = "disabled";
 469         };
 470
 471         scif4: serial@e6ee0000 {
 472                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 473                              "renesas,scif";
 474                 reg = <0 0xe6ee0000 0 64>;
 475                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 477                          <&scif_clk>;
 478                 clock-names = "fck", "brg_int", "scif_clk";
 479                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 480                 dma-names = "tx", "rx";
 481                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 482                 status = "disabled";
 483         };
 484
 485         scif5: serial@e6ee8000 {
 486                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 487                              "renesas,scif";
 488                 reg = <0 0xe6ee8000 0 64>;
 489                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 491                          <&scif_clk>;
 492                 clock-names = "fck", "brg_int", "scif_clk";
 493                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 494                 dma-names = "tx", "rx";
 495                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 496                 status = "disabled";
 497         };
 498
 499         hscif0: serial@e62c0000 {
 500                 compatible = "renesas,hscif-r8a7794",
 501                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 502                 reg = <0 0xe62c0000 0 96>;
 503                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 505                          <&scif_clk>;
 506                 clock-names = "fck", "brg_int", "scif_clk";
 507                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 508                 dma-names = "tx", "rx";
 509                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 510                 status = "disabled";
 511         };
 512
 513         hscif1: serial@e62c8000 {
 514                 compatible = "renesas,hscif-r8a7794",
 515                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 516                 reg = <0 0xe62c8000 0 96>;
 517                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 519                          <&scif_clk>;
 520                 clock-names = "fck", "brg_int", "scif_clk";
 521                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 522                 dma-names = "tx", "rx";
 523                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 524                 status = "disabled";
 525         };
 526
 527         hscif2: serial@e62d0000 {
 528                 compatible = "renesas,hscif-r8a7794",
 529                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 530                 reg = <0 0xe62d0000 0 96>;
 531                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 533                          <&scif_clk>;
 534                 clock-names = "fck", "brg_int", "scif_clk";
 535                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 536                 dma-names = "tx", "rx";
 537                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 538                 status = "disabled";
 539         };
 540
 541         ether: ethernet@ee700000 {
 542                 compatible = "renesas,ether-r8a7794";
 543                 reg = <0 0xee700000 0 0x400>;
 544                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 546                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 547                 phy-mode = "rmii";
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         avb: ethernet@e6800000 {
 554                 compatible = "renesas,etheravb-r8a7794",
 555                              "renesas,etheravb-rcar-gen2";
 556                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 557                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 559                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 status = "disabled";
 563         };
 564
 565         /* The memory map in the User's Manual maps the cores to bus numbers */
 566         i2c0: i2c@e6508000 {
 567                 compatible = "renesas,i2c-r8a7794";
 568                 reg = <0 0xe6508000 0 0x40>;
 569                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 570                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 571                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 i2c-scl-internal-delay-ns = <6>;
 575                 status = "disabled";
 576         };
 577
 578         i2c1: i2c@e6518000 {
 579                 compatible = "renesas,i2c-r8a7794";
 580                 reg = <0 0xe6518000 0 0x40>;
 581                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 582                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 583                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 i2c-scl-internal-delay-ns = <6>;
 587                 status = "disabled";
 588         };
 589
 590         i2c2: i2c@e6530000 {
 591                 compatible = "renesas,i2c-r8a7794";
 592                 reg = <0 0xe6530000 0 0x40>;
 593                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 594                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 595                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 i2c-scl-internal-delay-ns = <6>;
 599                 status = "disabled";
 600         };
 601
 602         i2c3: i2c@e6540000 {
 603                 compatible = "renesas,i2c-r8a7794";
 604                 reg = <0 0xe6540000 0 0x40>;
 605                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 607                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 i2c-scl-internal-delay-ns = <6>;
 611                 status = "disabled";
 612         };
 613
 614         i2c4: i2c@e6520000 {
 615                 compatible = "renesas,i2c-r8a7794";
 616                 reg = <0 0xe6520000 0 0x40>;
 617                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 618                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 619                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 i2c-scl-internal-delay-ns = <6>;
 623                 status = "disabled";
 624         };
 625
 626         i2c5: i2c@e6528000 {
 627                 compatible = "renesas,i2c-r8a7794";
 628                 reg = <0 0xe6528000 0 0x40>;
 629                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 631                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 i2c-scl-internal-delay-ns = <6>;
 635                 status = "disabled";
 636         };
 637
 638         i2c6: i2c@e6500000 {
 639                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 640                 reg = <0 0xe6500000 0 0x425>;
 641                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 643                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 644                 dma-names = "tx", "rx";
 645                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 status = "disabled";
 649         };
 650
 651         i2c7: i2c@e6510000 {
 652                 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
 653                 reg = <0 0xe6510000 0 0x425>;
 654                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 656                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 657                 dma-names = "tx", "rx";
 658                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 status = "disabled";
 662         };
 663
 664         mmcif0: mmc@ee200000 {
 665                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 666                 reg = <0 0xee200000 0 0x80>;
 667                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 669                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 670                 dma-names = "tx", "rx";
 671                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 672                 reg-io-width = <4>;
 673                 status = "disabled";
 674         };
 675
 676         sdhi0: sd@ee100000 {
 677                 compatible = "renesas,sdhi-r8a7794";
 678                 reg = <0 0xee100000 0 0x200>;
 679                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 680                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 681                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 682                 status = "disabled";
 683         };
 684
 685         sdhi1: sd@ee140000 {
 686                 compatible = "renesas,sdhi-r8a7794";
 687                 reg = <0 0xee140000 0 0x100>;
 688                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 690                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 691                 status = "disabled";
 692         };
 693
 694         sdhi2: sd@ee160000 {
 695                 compatible = "renesas,sdhi-r8a7794";
 696                 reg = <0 0xee160000 0 0x100>;
 697                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 699                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 700                 status = "disabled";
 701         };
 702
 703         qspi: spi@e6b10000 {
 704                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 705                 reg = <0 0xe6b10000 0 0x2c>;
 706                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 708                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 709                 dma-names = "tx", "rx";
 710                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 711                 num-cs = <1>;
 712                 #address-cells = <1>;
 713                 #size-cells = <0>;
 714                 status = "disabled";
 715         };
 716
 717         vin0: video@e6ef0000 {
 718                 compatible = "renesas,vin-r8a7794";
 719                 reg = <0 0xe6ef0000 0 0x1000>;
 720                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 722                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 723                 status = "disabled";
 724         };
 725
 726         vin1: video@e6ef1000 {
 727                 compatible = "renesas,vin-r8a7794";
 728                 reg = <0 0xe6ef1000 0 0x1000>;
 729                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 731                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 732                 status = "disabled";
 733         };
 734
 735         pci0: pci@ee090000 {
 736                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 737                 device_type = "pci";
 738                 reg = <0 0xee090000 0 0xc00>,
 739                       <0 0xee080000 0 0x1100>;
 740                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 742                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 743                 status = "disabled";
 744
 745                 bus-range = <0 0>;
 746                 #address-cells = <3>;
 747                 #size-cells = <2>;
 748                 #interrupt-cells = <1>;
 749                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 750                 interrupt-map-mask = <0xff00 0 0 0x7>;
 751                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 752                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 753                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 754
 755                 usb@0,1 {
 756                         reg = <0x800 0 0 0 0>;
 757                         device_type = "pci";
 758                         phys = <&usb0 0>;
 759                         phy-names = "usb";
 760                 };
 761
 762                 usb@0,2 {
 763                         reg = <0x1000 0 0 0 0>;
 764                         device_type = "pci";
 765                         phys = <&usb0 0>;
 766                         phy-names = "usb";
 767                 };
 768         };
 769
 770         pci1: pci@ee0d0000 {
 771                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 772                 device_type = "pci";
 773                 reg = <0 0xee0d0000 0 0xc00>,
 774                       <0 0xee0c0000 0 0x1100>;
 775                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 776                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 777                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 778                 status = "disabled";
 779
 780                 bus-range = <1 1>;
 781                 #address-cells = <3>;
 782                 #size-cells = <2>;
 783                 #interrupt-cells = <1>;
 784                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 785                 interrupt-map-mask = <0xff00 0 0 0x7>;
 786                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 787                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 788                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 789
 790                 usb@0,1 {
 791                         reg = <0x800 0 0 0 0>;
 792                         device_type = "pci";
 793                         phys = <&usb2 0>;
 794                         phy-names = "usb";
 795                 };
 796
 797                 usb@0,2 {
 798                         reg = <0x1000 0 0 0 0>;
 799                         device_type = "pci";
 800                         phys = <&usb2 0>;
 801                         phy-names = "usb";
 802                 };
 803         };
 804
 805         hsusb: usb@e6590000 {
 806                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 807                 reg = <0 0xe6590000 0 0x100>;
 808                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 809                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 810                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 811                 renesas,buswait = <4>;
 812                 phys = <&usb0 1>;
 813                 phy-names = "usb";
 814                 status = "disabled";
 815         };
 816
 817         usbphy: usb-phy@e6590100 {
 818                 compatible = "renesas,usb-phy-r8a7794";
 819                 reg = <0 0xe6590100 0 0x100>;
 820                 #address-cells = <1>;
 821                 #size-cells = <0>;
 822                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 823                 clock-names = "usbhs";
 824                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 825                 status = "disabled";
 826
 827                 usb0: usb-channel@0 {
 828                         reg = <0>;
 829                         #phy-cells = <1>;
 830                 };
 831                 usb2: usb-channel@2 {
 832                         reg = <2>;
 833                         #phy-cells = <1>;
 834                 };
 835         };
 836
 837         du: display@feb00000 {
 838                 compatible = "renesas,du-r8a7794";
 839                 reg = <0 0xfeb00000 0 0x40000>;
 840                 reg-names = "du";
 841                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 842                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 843                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 844                          <&mstp7_clks R8A7794_CLK_DU0>;
 845                 clock-names = "du.0", "du.1";
 846                 status = "disabled";
 847
 848                 ports {
 849                         #address-cells = <1>;
 850                         #size-cells = <0>;
 851
 852                         port@0 {
 853                                 reg = <0>;
 854                                 du_out_rgb0: endpoint {
 855                                 };
 856                         };
 857                         port@1 {
 858                                 reg = <1>;
 859                                 du_out_rgb1: endpoint {
 860                                 };
 861                         };
 862                 };
 863         };
 864
 865         can0: can@e6e80000 {
 866                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 867                 reg = <0 0xe6e80000 0 0x1000>;
 868                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 870                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 871                 clock-names = "clkp1", "clkp2", "can_clk";
 872                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 873                 status = "disabled";
 874         };
 875
 876         can1: can@e6e88000 {
 877                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 878                 reg = <0 0xe6e88000 0 0x1000>;
 879                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 881                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 882                 clock-names = "clkp1", "clkp2", "can_clk";
 883                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 884                 status = "disabled";
 885         };
 886
 887         clocks {
 888                 #address-cells = <2>;
 889                 #size-cells = <2>;
 890                 ranges;
 891
 892                 /* External root clock */
 893                 extal_clk: extal {
 894                         compatible = "fixed-clock";
 895                         #clock-cells = <0>;
 896                         /* This value must be overriden by the board. */
 897                         clock-frequency = <0>;
 898                 };
 899
 900                 /* External USB clock - can be overridden by the board */
 901                 usb_extal_clk: usb_extal {
 902                         compatible = "fixed-clock";
 903                         #clock-cells = <0>;
 904                         clock-frequency = <48000000>;
 905                 };
 906
 907                 /* External CAN clock */
 908                 can_clk: can {
 909                         compatible = "fixed-clock";
 910                         #clock-cells = <0>;
 911                         /* This value must be overridden by the board. */
 912                         clock-frequency = <0>;
 913                 };
 914
 915                 /* External SCIF clock */
 916                 scif_clk: scif {
 917                         compatible = "fixed-clock";
 918                         #clock-cells = <0>;
 919                         /* This value must be overridden by the board. */
 920                         clock-frequency = <0>;
 921                 };
 922
 923                 /* Special CPG clocks */
 924                 cpg_clocks: cpg_clocks@e6150000 {
 925                         compatible = "renesas,r8a7794-cpg-clocks",
 926                                      "renesas,rcar-gen2-cpg-clocks";
 927                         reg = <0 0xe6150000 0 0x1000>;
 928                         clocks = <&extal_clk &usb_extal_clk>;
 929                         #clock-cells = <1>;
 930                         clock-output-names = "main", "pll0", "pll1", "pll3",
 931                                              "lb", "qspi", "sdh", "sd0", "z",
 932                                              "rcan";
 933                         #power-domain-cells = <0>;
 934                 };
 935                 /* Variable factor clocks */
 936                 sd2_clk: sd2@e6150078 {
 937                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 938                         reg = <0 0xe6150078 0 4>;
 939                         clocks = <&pll1_div2_clk>;
 940                         #clock-cells = <0>;
 941                 };
 942                 sd3_clk: sd3@e615026c {
 943                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 944                         reg = <0 0xe615026c 0 4>;
 945                         clocks = <&pll1_div2_clk>;
 946                         #clock-cells = <0>;
 947                 };
 948                 mmc0_clk: mmc0@e6150240 {
 949                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 950                         reg = <0 0xe6150240 0 4>;
 951                         clocks = <&pll1_div2_clk>;
 952                         #clock-cells = <0>;
 953                 };
 954
 955                 /* Fixed factor clocks */
 956                 pll1_div2_clk: pll1_div2 {
 957                         compatible = "fixed-factor-clock";
 958                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 959                         #clock-cells = <0>;
 960                         clock-div = <2>;
 961                         clock-mult = <1>;
 962                 };
 963                 zg_clk: zg {
 964                         compatible = "fixed-factor-clock";
 965                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 966                         #clock-cells = <0>;
 967                         clock-div = <6>;
 968                         clock-mult = <1>;
 969                 };
 970                 zx_clk: zx {
 971                         compatible = "fixed-factor-clock";
 972                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 973                         #clock-cells = <0>;
 974                         clock-div = <3>;
 975                         clock-mult = <1>;
 976                 };
 977                 zs_clk: zs {
 978                         compatible = "fixed-factor-clock";
 979                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 980                         #clock-cells = <0>;
 981                         clock-div = <6>;
 982                         clock-mult = <1>;
 983                 };
 984                 hp_clk: hp {
 985                         compatible = "fixed-factor-clock";
 986                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 987                         #clock-cells = <0>;
 988                         clock-div = <12>;
 989                         clock-mult = <1>;
 990                 };
 991                 i_clk: i {
 992                         compatible = "fixed-factor-clock";
 993                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 994                         #clock-cells = <0>;
 995                         clock-div = <2>;
 996                         clock-mult = <1>;
 997                 };
 998                 b_clk: b {
 999                         compatible = "fixed-factor-clock";
1000                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1001                         #clock-cells = <0>;
1002                         clock-div = <12>;
1003                         clock-mult = <1>;
1004                 };
1005                 p_clk: p {
1006                         compatible = "fixed-factor-clock";
1007                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1008                         #clock-cells = <0>;
1009                         clock-div = <24>;
1010                         clock-mult = <1>;
1011                 };
1012                 cl_clk: cl {
1013                         compatible = "fixed-factor-clock";
1014                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1015                         #clock-cells = <0>;
1016                         clock-div = <48>;
1017                         clock-mult = <1>;
1018                 };
1019                 m2_clk: m2 {
1020                         compatible = "fixed-factor-clock";
1021                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1022                         #clock-cells = <0>;
1023                         clock-div = <8>;
1024                         clock-mult = <1>;
1025                 };
1026                 rclk_clk: rclk {
1027                         compatible = "fixed-factor-clock";
1028                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1029                         #clock-cells = <0>;
1030                         clock-div = <(48 * 1024)>;
1031                         clock-mult = <1>;
1032                 };
1033                 oscclk_clk: oscclk {
1034                         compatible = "fixed-factor-clock";
1035                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1036                         #clock-cells = <0>;
1037                         clock-div = <(12 * 1024)>;
1038                         clock-mult = <1>;
1039                 };
1040                 zb3_clk: zb3 {
1041                         compatible = "fixed-factor-clock";
1042                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1043                         #clock-cells = <0>;
1044                         clock-div = <4>;
1045                         clock-mult = <1>;
1046                 };
1047                 zb3d2_clk: zb3d2 {
1048                         compatible = "fixed-factor-clock";
1049                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1050                         #clock-cells = <0>;
1051                         clock-div = <8>;
1052                         clock-mult = <1>;
1053                 };
1054                 ddr_clk: ddr {
1055                         compatible = "fixed-factor-clock";
1056                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1057                         #clock-cells = <0>;
1058                         clock-div = <8>;
1059                         clock-mult = <1>;
1060                 };
1061                 mp_clk: mp {
1062                         compatible = "fixed-factor-clock";
1063                         clocks = <&pll1_div2_clk>;
1064                         #clock-cells = <0>;
1065                         clock-div = <15>;
1066                         clock-mult = <1>;
1067                 };
1068                 cp_clk: cp {
1069                         compatible = "fixed-factor-clock";
1070                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1071                         #clock-cells = <0>;
1072                         clock-div = <48>;
1073                         clock-mult = <1>;
1074                 };
1075
1076                 acp_clk: acp {
1077                         compatible = "fixed-factor-clock";
1078                         clocks = <&extal_clk>;
1079                         #clock-cells = <0>;
1080                         clock-div = <2>;
1081                         clock-mult = <1>;
1082                 };
1083
1084                 /* Gate clocks */
1085                 mstp0_clks: mstp0_clks@e6150130 {
1086                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1087                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1088                         clocks = <&mp_clk>;
1089                         #clock-cells = <1>;
1090                         clock-indices = <R8A7794_CLK_MSIOF0>;
1091                         clock-output-names = "msiof0";
1092                 };
1093                 mstp1_clks: mstp1_clks@e6150134 {
1094                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1095                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1096                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1097                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1098                                  <&zs_clk>, <&zs_clk>;
1099                         #clock-cells = <1>;
1100                         clock-indices = <
1101                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1102                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1103                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1104                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1105                         >;
1106                         clock-output-names =
1107                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1108                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1109                 };
1110                 mstp2_clks: mstp2_clks@e6150138 {
1111                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1112                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1113                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1114                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1115                                  <&zs_clk>, <&zs_clk>;
1116                         #clock-cells = <1>;
1117                         clock-indices = <
1118                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1119                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1120                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1121                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1122                         >;
1123                         clock-output-names =
1124                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1125                                 "scifb1", "msiof1", "scifb2",
1126                                 "sys-dmac1", "sys-dmac0";
1127                 };
1128                 mstp3_clks: mstp3_clks@e615013c {
1129                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1130                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1131                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1132                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1133                                  <&hp_clk>, <&hp_clk>;
1134                         #clock-cells = <1>;
1135                         clock-indices = <
1136                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1137                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1138                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1139                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1140                         >;
1141                         clock-output-names =
1142                                 "sdhi2", "sdhi1", "sdhi0",
1143                                 "mmcif0", "i2c6", "i2c7",
1144                                 "cmt1", "usbdmac0", "usbdmac1";
1145                 };
1146                 mstp4_clks: mstp4_clks@e6150140 {
1147                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1148                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1149                         clocks = <&cp_clk>;
1150                         #clock-cells = <1>;
1151                         clock-indices = <R8A7794_CLK_IRQC>;
1152                         clock-output-names = "irqc";
1153                 };
1154                 mstp7_clks: mstp7_clks@e615014c {
1155                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1156                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1157                         clocks = <&mp_clk>, <&mp_clk>,
1158                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1159                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1160                                  <&zx_clk>;
1161                         #clock-cells = <1>;
1162                         clock-indices = <
1163                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1164                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1165                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1166                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1167                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1168                         >;
1169                         clock-output-names =
1170                                 "ehci", "hsusb",
1171                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1172                                 "scif3", "scif2", "scif1", "scif0", "du0";
1173                 };
1174                 mstp8_clks: mstp8_clks@e6150990 {
1175                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1176                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1177                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1178                         #clock-cells = <1>;
1179                         clock-indices = <
1180                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1181                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1182                         >;
1183                         clock-output-names =
1184                                 "vin1", "vin0", "etheravb", "ether";
1185                 };
1186                 mstp9_clks: mstp9_clks@e6150994 {
1187                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1188                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1189                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1190                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1191                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1192                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1193                                  <&hp_clk>, <&hp_clk>;
1194                         #clock-cells = <1>;
1195                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1196                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1197                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1198                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1199                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1200                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1201                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1202                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1203                         clock-output-names =
1204                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1205                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1206                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1207                 };
1208                 mstp11_clks: mstp11_clks@e615099c {
1209                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1210                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1211                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1212                         #clock-cells = <1>;
1213                         clock-indices = <
1214                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1215                         >;
1216                         clock-output-names = "scifa3", "scifa4", "scifa5";
1217                 };
1218         };
1219
1220         sysc: system-controller@e6180000 {
1221                 compatible = "renesas,r8a7794-sysc";
1222                 reg = <0 0xe6180000 0 0x0200>;
1223                 #power-domain-cells = <1>;
1224         };
1225
1226         ipmmu_sy0: mmu@e6280000 {
1227                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1228                 reg = <0 0xe6280000 0 0x1000>;
1229                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1230                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1231                 #iommu-cells = <1>;
1232                 status = "disabled";
1233         };
1234
1235         ipmmu_sy1: mmu@e6290000 {
1236                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1237                 reg = <0 0xe6290000 0 0x1000>;
1238                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1239                 #iommu-cells = <1>;
1240                 status = "disabled";
1241         };
1242
1243         ipmmu_ds: mmu@e6740000 {
1244                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1245                 reg = <0 0xe6740000 0 0x1000>;
1246                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1247                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1248                 #iommu-cells = <1>;
1249                 status = "disabled";
1250         };
1251
1252         ipmmu_mp: mmu@ec680000 {
1253                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1254                 reg = <0 0xec680000 0 0x1000>;
1255                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1256                 #iommu-cells = <1>;
1257                 status = "disabled";
1258         };
1259
1260         ipmmu_mx: mmu@fe951000 {
1261                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1262                 reg = <0 0xfe951000 0 0x1000>;
1263                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1264                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1265                 #iommu-cells = <1>;
1266                 status = "disabled";
1267         };
1268
1269         ipmmu_gp: mmu@e62a0000 {
1270                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1271                 reg = <0 0xe62a0000 0 0x1000>;
1272                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1273                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1274                 #iommu-cells = <1>;
1275                 status = "disabled";
1276         };
1277 };