arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a7-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         cmt0: timer@ffca0000 {
  54                 compatible = "renesas,cmt-48-gen2";
  55                 reg = <0 0xffca0000 0 0x1004>;
  56                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  57                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
  59                 clock-names = "fck";
  60
  61                 renesas,channels-mask = <0x60>;
  62
  63                 status = "disabled";
  64         };
  65
  66         cmt1: timer@e6130000 {
  67                 compatible = "renesas,cmt-48-gen2";
  68                 reg = <0 0xe6130000 0 0x1004>;
  69                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  70                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  71                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  72                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  73                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  74                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  75                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  76                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
  78                 clock-names = "fck";
  79
  80                 renesas,channels-mask = <0xff>;
  81
  82                 status = "disabled";
  83         };
  84
  85         irqc0: interrupt-controller@e61c0000 {
  86                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 reg = <0 0xe61c0000 0 0x200>;
  90                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  91                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
  92                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
  93                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
  94                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
  95                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
  96                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
  97                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
  98                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 100         };
 101
 102         scifa0: serial@e6c40000 {
 103                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 104                 reg = <0 0xe6c40000 0 64>;
 105                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 106                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 107                 clock-names = "sci_ick";
 108                 status = "disabled";
 109         };
 110
 111         scifa1: serial@e6c50000 {
 112                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 113                 reg = <0 0xe6c50000 0 64>;
 114                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 115                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 116                 clock-names = "sci_ick";
 117                 status = "disabled";
 118         };
 119
 120         scifa2: serial@e6c60000 {
 121                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 122                 reg = <0 0xe6c60000 0 64>;
 123                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 124                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 125                 clock-names = "sci_ick";
 126                 status = "disabled";
 127         };
 128
 129         scifa3: serial@e6c70000 {
 130                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 131                 reg = <0 0xe6c70000 0 64>;
 132                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 133                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 134                 clock-names = "sci_ick";
 135                 status = "disabled";
 136         };
 137
 138         scifa4: serial@e6c78000 {
 139                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 140                 reg = <0 0xe6c78000 0 64>;
 141                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 142                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 143                 clock-names = "sci_ick";
 144                 status = "disabled";
 145         };
 146
 147         scifa5: serial@e6c80000 {
 148                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 149                 reg = <0 0xe6c80000 0 64>;
 150                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 151                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 152                 clock-names = "sci_ick";
 153                 status = "disabled";
 154         };
 155
 156         scifb0: serial@e6c20000 {
 157                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 158                 reg = <0 0xe6c20000 0 64>;
 159                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 160                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 161                 clock-names = "sci_ick";
 162                 status = "disabled";
 163         };
 164
 165         scifb1: serial@e6c30000 {
 166                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 167                 reg = <0 0xe6c30000 0 64>;
 168                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 170                 clock-names = "sci_ick";
 171                 status = "disabled";
 172         };
 173
 174         scifb2: serial@e6ce0000 {
 175                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 176                 reg = <0 0xe6ce0000 0 64>;
 177                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 179                 clock-names = "sci_ick";
 180                 status = "disabled";
 181         };
 182
 183         scif0: serial@e6e60000 {
 184                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 185                 reg = <0 0xe6e60000 0 64>;
 186                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 188                 clock-names = "sci_ick";
 189                 status = "disabled";
 190         };
 191
 192         scif1: serial@e6e68000 {
 193                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 194                 reg = <0 0xe6e68000 0 64>;
 195                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 197                 clock-names = "sci_ick";
 198                 status = "disabled";
 199         };
 200
 201         scif2: serial@e6e58000 {
 202                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 203                 reg = <0 0xe6e58000 0 64>;
 204                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 206                 clock-names = "sci_ick";
 207                 status = "disabled";
 208         };
 209
 210         scif3: serial@e6ea8000 {
 211                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 212                 reg = <0 0xe6ea8000 0 64>;
 213                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 215                 clock-names = "sci_ick";
 216                 status = "disabled";
 217         };
 218
 219         scif4: serial@e6ee0000 {
 220                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 221                 reg = <0 0xe6ee0000 0 64>;
 222                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 224                 clock-names = "sci_ick";
 225                 status = "disabled";
 226         };
 227
 228         scif5: serial@e6ee8000 {
 229                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 230                 reg = <0 0xe6ee8000 0 64>;
 231                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 233                 clock-names = "sci_ick";
 234                 status = "disabled";
 235         };
 236
 237         hscif0: serial@e62c0000 {
 238                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 239                 reg = <0 0xe62c0000 0 96>;
 240                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 242                 clock-names = "sci_ick";
 243                 status = "disabled";
 244         };
 245
 246         hscif1: serial@e62c8000 {
 247                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 248                 reg = <0 0xe62c8000 0 96>;
 249                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 250                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 251                 clock-names = "sci_ick";
 252                 status = "disabled";
 253         };
 254
 255         hscif2: serial@e62d0000 {
 256                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 257                 reg = <0 0xe62d0000 0 96>;
 258                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 260                 clock-names = "sci_ick";
 261                 status = "disabled";
 262         };
 263
 264         clocks {
 265                 #address-cells = <2>;
 266                 #size-cells = <2>;
 267                 ranges;
 268
 269                 /* External root clock */
 270                 extal_clk: extal_clk {
 271                         compatible = "fixed-clock";
 272                         #clock-cells = <0>;
 273                         /* This value must be overriden by the board. */
 274                         clock-frequency = <0>;
 275                         clock-output-names = "extal";
 276                 };
 277
 278                 /* Special CPG clocks */
 279                 cpg_clocks: cpg_clocks@e6150000 {
 280                         compatible = "renesas,r8a7794-cpg-clocks",
 281                                      "renesas,rcar-gen2-cpg-clocks";
 282                         reg = <0 0xe6150000 0 0x1000>;
 283                         clocks = <&extal_clk>;
 284                         #clock-cells = <1>;
 285                         clock-output-names = "main", "pll0", "pll1", "pll3",
 286                                              "lb", "qspi", "sdh", "sd0", "z";
 287                 };
 288
 289                 /* Fixed factor clocks */
 290                 pll1_div2_clk: pll1_div2_clk {
 291                         compatible = "fixed-factor-clock";
 292                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 293                         #clock-cells = <0>;
 294                         clock-div = <2>;
 295                         clock-mult = <1>;
 296                         clock-output-names = "pll1_div2";
 297                 };
 298                 zg_clk: zg_clk {
 299                         compatible = "fixed-factor-clock";
 300                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 301                         #clock-cells = <0>;
 302                         clock-div = <6>;
 303                         clock-mult = <1>;
 304                         clock-output-names = "zg";
 305                 };
 306                 zx_clk: zx_clk {
 307                         compatible = "fixed-factor-clock";
 308                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 309                         #clock-cells = <0>;
 310                         clock-div = <3>;
 311                         clock-mult = <1>;
 312                         clock-output-names = "zx";
 313                 };
 314                 zs_clk: zs_clk {
 315                         compatible = "fixed-factor-clock";
 316                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 317                         #clock-cells = <0>;
 318                         clock-div = <6>;
 319                         clock-mult = <1>;
 320                         clock-output-names = "zs";
 321                 };
 322                 hp_clk: hp_clk {
 323                         compatible = "fixed-factor-clock";
 324                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 325                         #clock-cells = <0>;
 326                         clock-div = <12>;
 327                         clock-mult = <1>;
 328                         clock-output-names = "hp";
 329                 };
 330                 i_clk: i_clk {
 331                         compatible = "fixed-factor-clock";
 332                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 333                         #clock-cells = <0>;
 334                         clock-div = <2>;
 335                         clock-mult = <1>;
 336                         clock-output-names = "i";
 337                 };
 338                 b_clk: b_clk {
 339                         compatible = "fixed-factor-clock";
 340                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 341                         #clock-cells = <0>;
 342                         clock-div = <12>;
 343                         clock-mult = <1>;
 344                         clock-output-names = "b";
 345                 };
 346                 p_clk: p_clk {
 347                         compatible = "fixed-factor-clock";
 348                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 349                         #clock-cells = <0>;
 350                         clock-div = <24>;
 351                         clock-mult = <1>;
 352                         clock-output-names = "p";
 353                 };
 354                 cl_clk: cl_clk {
 355                         compatible = "fixed-factor-clock";
 356                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 357                         #clock-cells = <0>;
 358                         clock-div = <48>;
 359                         clock-mult = <1>;
 360                         clock-output-names = "cl";
 361                 };
 362                 m2_clk: m2_clk {
 363                         compatible = "fixed-factor-clock";
 364                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 365                         #clock-cells = <0>;
 366                         clock-div = <8>;
 367                         clock-mult = <1>;
 368                         clock-output-names = "m2";
 369                 };
 370                 imp_clk: imp_clk {
 371                         compatible = "fixed-factor-clock";
 372                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 373                         #clock-cells = <0>;
 374                         clock-div = <4>;
 375                         clock-mult = <1>;
 376                         clock-output-names = "imp";
 377                 };
 378                 rclk_clk: rclk_clk {
 379                         compatible = "fixed-factor-clock";
 380                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 381                         #clock-cells = <0>;
 382                         clock-div = <(48 * 1024)>;
 383                         clock-mult = <1>;
 384                         clock-output-names = "rclk";
 385                 };
 386                 oscclk_clk: oscclk_clk {
 387                         compatible = "fixed-factor-clock";
 388                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 389                         #clock-cells = <0>;
 390                         clock-div = <(12 * 1024)>;
 391                         clock-mult = <1>;
 392                         clock-output-names = "oscclk";
 393                 };
 394                 zb3_clk: zb3_clk {
 395                         compatible = "fixed-factor-clock";
 396                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 397                         #clock-cells = <0>;
 398                         clock-div = <4>;
 399                         clock-mult = <1>;
 400                         clock-output-names = "zb3";
 401                 };
 402                 zb3d2_clk: zb3d2_clk {
 403                         compatible = "fixed-factor-clock";
 404                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 405                         #clock-cells = <0>;
 406                         clock-div = <8>;
 407                         clock-mult = <1>;
 408                         clock-output-names = "zb3d2";
 409                 };
 410                 ddr_clk: ddr_clk {
 411                         compatible = "fixed-factor-clock";
 412                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 413                         #clock-cells = <0>;
 414                         clock-div = <8>;
 415                         clock-mult = <1>;
 416                         clock-output-names = "ddr";
 417                 };
 418                 mp_clk: mp_clk {
 419                         compatible = "fixed-factor-clock";
 420                         clocks = <&pll1_div2_clk>;
 421                         #clock-cells = <0>;
 422                         clock-div = <15>;
 423                         clock-mult = <1>;
 424                         clock-output-names = "mp";
 425                 };
 426                 cp_clk: cp_clk {
 427                         compatible = "fixed-factor-clock";
 428                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 429                         #clock-cells = <0>;
 430                         clock-div = <48>;
 431                         clock-mult = <1>;
 432                         clock-output-names = "cp";
 433                 };
 434
 435                 acp_clk: acp_clk {
 436                         compatible = "fixed-factor-clock";
 437                         clocks = <&extal_clk>;
 438                         #clock-cells = <0>;
 439                         clock-div = <2>;
 440                         clock-mult = <1>;
 441                         clock-output-names = "acp";
 442                 };
 443
 444                 /* Gate clocks */
 445                 mstp0_clks: mstp0_clks@e6150130 {
 446                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 447                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 448                         clocks = <&mp_clk>;
 449                         #clock-cells = <1>;
 450                         renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
 451                         clock-output-names = "msiof0";
 452                 };
 453                 mstp1_clks: mstp1_clks@e6150134 {
 454                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 455                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 456                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 457                                  <&cp_clk>,
 458                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
 459                         #clock-cells = <1>;
 460                         renesas,clock-indices = <
 461                                 R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
 462                                 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
 463                         >;
 464                         clock-output-names =
 465                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
 466                 };
 467                 mstp2_clks: mstp2_clks@e6150138 {
 468                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 469                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 470                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 471                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 472                         #clock-cells = <1>;
 473                         renesas,clock-indices = <
 474                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
 475                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
 476                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
 477                         >;
 478                         clock-output-names =
 479                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 480                                 "scifb1", "msiof1", "scifb2";
 481                 };
 482                 mstp3_clks: mstp3_clks@e615013c {
 483                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 484                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 485                         clocks = <&rclk_clk>;
 486                         #clock-cells = <1>;
 487                         renesas,clock-indices = <
 488                                 R8A7794_CLK_CMT1
 489                         >;
 490                         clock-output-names =
 491                                 "cmt1";
 492                 };
 493                 mstp7_clks: mstp7_clks@e615014c {
 494                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 495                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 496                         clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 497                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 498                         #clock-cells = <1>;
 499                         renesas,clock-indices = <
 500                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
 501                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
 502                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
 503                                 R8A7794_CLK_SCIF0
 504                         >;
 505                         clock-output-names =
 506                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 507                                 "scif3", "scif2", "scif1", "scif0";
 508                 };
 509                 mstp8_clks: mstp8_clks@e6150990 {
 510                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 511                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 512                         clocks = <&p_clk>;
 513                         #clock-cells = <1>;
 514                         renesas,clock-indices = <
 515                                 R8A7794_CLK_ETHER
 516                         >;
 517                         clock-output-names =
 518                                 "ether";
 519                 };
 520                 mstp11_clks: mstp11_clks@e615099c {
 521                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 522                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 523                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 524                         #clock-cells = <1>;
 525                         renesas,clock-indices = <
 526                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
 527                         >;
 528                         clock-output-names = "scifa3", "scifa4", "scifa5";
 529                 };
 530         };
 531 };