arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         clocks = <&z2_clk>;
  47                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  48                         next-level-cache = <&L2_CA7>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54                         reg = <1>;
  55                         clock-frequency = <1000000000>;
  56                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  57                         next-level-cache = <&L2_CA7>;
  58                 };
  59
  60                 L2_CA7: cache-controller-0 {
  61                         compatible = "cache";
  62                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                         cache-unified;
  64                         cache-level = <2>;
  65                 };
  66         };
  67
  68         gic: interrupt-controller@f1001000 {
  69                 compatible = "arm,gic-400";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0 0xf1001000 0 0x1000>,
  74                         <0 0xf1002000 0 0x2000>,
  75                         <0 0xf1004000 0 0x2000>,
  76                         <0 0xf1006000 0 0x2000>;
  77                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  78                 clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
  79                 clock-names = "clk";
  80                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  81         };
  82
  83         gpio0: gpio@e6050000 {
  84                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  85                 reg = <0 0xe6050000 0 0x50>;
  86                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  87                 #gpio-cells = <2>;
  88                 gpio-controller;
  89                 gpio-ranges = <&pfc 0 0 32>;
  90                 #interrupt-cells = <2>;
  91                 interrupt-controller;
  92                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  93                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  94         };
  95
  96         gpio1: gpio@e6051000 {
  97                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  98                 reg = <0 0xe6051000 0 0x50>;
  99                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 32 26>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 106                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 107         };
 108
 109         gpio2: gpio@e6052000 {
 110                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 111                 reg = <0 0xe6052000 0 0x50>;
 112                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 113                 #gpio-cells = <2>;
 114                 gpio-controller;
 115                 gpio-ranges = <&pfc 0 64 32>;
 116                 #interrupt-cells = <2>;
 117                 interrupt-controller;
 118                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 119                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 120         };
 121
 122         gpio3: gpio@e6053000 {
 123                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 124                 reg = <0 0xe6053000 0 0x50>;
 125                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 96 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 132                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 133         };
 134
 135         gpio4: gpio@e6054000 {
 136                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 137                 reg = <0 0xe6054000 0 0x50>;
 138                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 139                 #gpio-cells = <2>;
 140                 gpio-controller;
 141                 gpio-ranges = <&pfc 0 128 32>;
 142                 #interrupt-cells = <2>;
 143                 interrupt-controller;
 144                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 145                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 146         };
 147
 148         gpio5: gpio@e6055000 {
 149                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 150                 reg = <0 0xe6055000 0 0x50>;
 151                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 152                 #gpio-cells = <2>;
 153                 gpio-controller;
 154                 gpio-ranges = <&pfc 0 160 28>;
 155                 #interrupt-cells = <2>;
 156                 interrupt-controller;
 157                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 158                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 159         };
 160
 161         gpio6: gpio@e6055400 {
 162                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 163                 reg = <0 0xe6055400 0 0x50>;
 164                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 165                 #gpio-cells = <2>;
 166                 gpio-controller;
 167                 gpio-ranges = <&pfc 0 192 26>;
 168                 #interrupt-cells = <2>;
 169                 interrupt-controller;
 170                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 171                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 172         };
 173
 174         cmt0: timer@ffca0000 {
 175                 compatible = "renesas,cmt-48-gen2";
 176                 reg = <0 0xffca0000 0 0x1004>;
 177                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 180                 clock-names = "fck";
 181                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 182
 183                 renesas,channels-mask = <0x60>;
 184
 185                 status = "disabled";
 186         };
 187
 188         cmt1: timer@e6130000 {
 189                 compatible = "renesas,cmt-48-gen2";
 190                 reg = <0 0xe6130000 0 0x1004>;
 191                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 200                 clock-names = "fck";
 201                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 202
 203                 renesas,channels-mask = <0xff>;
 204
 205                 status = "disabled";
 206         };
 207
 208         timer {
 209                 compatible = "arm,armv7-timer";
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 214         };
 215
 216         irqc0: interrupt-controller@e61c0000 {
 217                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 218                 #interrupt-cells = <2>;
 219                 interrupt-controller;
 220                 reg = <0 0xe61c0000 0 0x200>;
 221                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 232                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 233         };
 234
 235         pfc: pin-controller@e6060000 {
 236                 compatible = "renesas,pfc-r8a7794";
 237                 reg = <0 0xe6060000 0 0x11c>;
 238         };
 239
 240         dmac0: dma-controller@e6700000 {
 241                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 242                 reg = <0 0xe6700000 0 0x20000>;
 243                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 256                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 257                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 258                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 259                 interrupt-names = "error",
 260                                 "ch0", "ch1", "ch2", "ch3",
 261                                 "ch4", "ch5", "ch6", "ch7",
 262                                 "ch8", "ch9", "ch10", "ch11",
 263                                 "ch12", "ch13", "ch14";
 264                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 265                 clock-names = "fck";
 266                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 267                 #dma-cells = <1>;
 268                 dma-channels = <15>;
 269         };
 270
 271         dmac1: dma-controller@e6720000 {
 272                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 273                 reg = <0 0xe6720000 0 0x20000>;
 274                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 287                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 288                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 289                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 290                 interrupt-names = "error",
 291                                 "ch0", "ch1", "ch2", "ch3",
 292                                 "ch4", "ch5", "ch6", "ch7",
 293                                 "ch8", "ch9", "ch10", "ch11",
 294                                 "ch12", "ch13", "ch14";
 295                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 296                 clock-names = "fck";
 297                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 298                 #dma-cells = <1>;
 299                 dma-channels = <15>;
 300         };
 301
 302         audma0: dma-controller@ec700000 {
 303                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 304                 reg = <0 0xec700000 0 0x10000>;
 305                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 306                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 307                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 308                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 309                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 310                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 311                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 312                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 313                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 314                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 315                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 316                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 317                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 318                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 319                 interrupt-names = "error",
 320                                   "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
 321                                   "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
 322                                   "ch12";
 323                 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
 324                 clock-names = "fck";
 325                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 326                 #dma-cells = <1>;
 327                 dma-channels = <13>;
 328         };
 329
 330         scifa0: serial@e6c40000 {
 331                 compatible = "renesas,scifa-r8a7794",
 332                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 333                 reg = <0 0xe6c40000 0 64>;
 334                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 336                 clock-names = "fck";
 337                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 338                        <&dmac1 0x21>, <&dmac1 0x22>;
 339                 dma-names = "tx", "rx", "tx", "rx";
 340                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 341                 status = "disabled";
 342         };
 343
 344         scifa1: serial@e6c50000 {
 345                 compatible = "renesas,scifa-r8a7794",
 346                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 347                 reg = <0 0xe6c50000 0 64>;
 348                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 350                 clock-names = "fck";
 351                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 352                        <&dmac1 0x25>, <&dmac1 0x26>;
 353                 dma-names = "tx", "rx", "tx", "rx";
 354                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 355                 status = "disabled";
 356         };
 357
 358         scifa2: serial@e6c60000 {
 359                 compatible = "renesas,scifa-r8a7794",
 360                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 361                 reg = <0 0xe6c60000 0 64>;
 362                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 364                 clock-names = "fck";
 365                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 366                        <&dmac1 0x27>, <&dmac1 0x28>;
 367                 dma-names = "tx", "rx", "tx", "rx";
 368                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 369                 status = "disabled";
 370         };
 371
 372         scifa3: serial@e6c70000 {
 373                 compatible = "renesas,scifa-r8a7794",
 374                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 375                 reg = <0 0xe6c70000 0 64>;
 376                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 378                 clock-names = "fck";
 379                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 380                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 381                 dma-names = "tx", "rx", "tx", "rx";
 382                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 383                 status = "disabled";
 384         };
 385
 386         scifa4: serial@e6c78000 {
 387                 compatible = "renesas,scifa-r8a7794",
 388                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 389                 reg = <0 0xe6c78000 0 64>;
 390                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 392                 clock-names = "fck";
 393                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 394                        <&dmac1 0x1f>, <&dmac1 0x20>;
 395                 dma-names = "tx", "rx", "tx", "rx";
 396                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 397                 status = "disabled";
 398         };
 399
 400         scifa5: serial@e6c80000 {
 401                 compatible = "renesas,scifa-r8a7794",
 402                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 403                 reg = <0 0xe6c80000 0 64>;
 404                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 406                 clock-names = "fck";
 407                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 408                        <&dmac1 0x23>, <&dmac1 0x24>;
 409                 dma-names = "tx", "rx", "tx", "rx";
 410                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 411                 status = "disabled";
 412         };
 413
 414         scifb0: serial@e6c20000 {
 415                 compatible = "renesas,scifb-r8a7794",
 416                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 417                 reg = <0 0xe6c20000 0 0x100>;
 418                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 420                 clock-names = "fck";
 421                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 422                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 423                 dma-names = "tx", "rx", "tx", "rx";
 424                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 425                 status = "disabled";
 426         };
 427
 428         scifb1: serial@e6c30000 {
 429                 compatible = "renesas,scifb-r8a7794",
 430                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 431                 reg = <0 0xe6c30000 0 0x100>;
 432                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 434                 clock-names = "fck";
 435                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 436                        <&dmac1 0x19>, <&dmac1 0x1a>;
 437                 dma-names = "tx", "rx", "tx", "rx";
 438                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 439                 status = "disabled";
 440         };
 441
 442         scifb2: serial@e6ce0000 {
 443                 compatible = "renesas,scifb-r8a7794",
 444                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 445                 reg = <0 0xe6ce0000 0 0x100>;
 446                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 448                 clock-names = "fck";
 449                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 450                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 451                 dma-names = "tx", "rx", "tx", "rx";
 452                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 453                 status = "disabled";
 454         };
 455
 456         scif0: serial@e6e60000 {
 457                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 458                              "renesas,scif";
 459                 reg = <0 0xe6e60000 0 64>;
 460                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 462                          <&scif_clk>;
 463                 clock-names = "fck", "brg_int", "scif_clk";
 464                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 465                        <&dmac1 0x29>, <&dmac1 0x2a>;
 466                 dma-names = "tx", "rx", "tx", "rx";
 467                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 468                 status = "disabled";
 469         };
 470
 471         scif1: serial@e6e68000 {
 472                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 473                              "renesas,scif";
 474                 reg = <0 0xe6e68000 0 64>;
 475                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 477                          <&scif_clk>;
 478                 clock-names = "fck", "brg_int", "scif_clk";
 479                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 480                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 481                 dma-names = "tx", "rx", "tx", "rx";
 482                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 483                 status = "disabled";
 484         };
 485
 486         scif2: serial@e6e58000 {
 487                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 488                              "renesas,scif";
 489                 reg = <0 0xe6e58000 0 64>;
 490                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 492                          <&scif_clk>;
 493                 clock-names = "fck", "brg_int", "scif_clk";
 494                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 495                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 496                 dma-names = "tx", "rx", "tx", "rx";
 497                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 498                 status = "disabled";
 499         };
 500
 501         scif3: serial@e6ea8000 {
 502                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 503                              "renesas,scif";
 504                 reg = <0 0xe6ea8000 0 64>;
 505                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 506                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 507                          <&scif_clk>;
 508                 clock-names = "fck", "brg_int", "scif_clk";
 509                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 510                        <&dmac1 0x2f>, <&dmac1 0x30>;
 511                 dma-names = "tx", "rx", "tx", "rx";
 512                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 513                 status = "disabled";
 514         };
 515
 516         scif4: serial@e6ee0000 {
 517                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 518                              "renesas,scif";
 519                 reg = <0 0xe6ee0000 0 64>;
 520                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 521                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 522                          <&scif_clk>;
 523                 clock-names = "fck", "brg_int", "scif_clk";
 524                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 525                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 526                 dma-names = "tx", "rx", "tx", "rx";
 527                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 528                 status = "disabled";
 529         };
 530
 531         scif5: serial@e6ee8000 {
 532                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 533                              "renesas,scif";
 534                 reg = <0 0xe6ee8000 0 64>;
 535                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 537                          <&scif_clk>;
 538                 clock-names = "fck", "brg_int", "scif_clk";
 539                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 540                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 541                 dma-names = "tx", "rx", "tx", "rx";
 542                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 543                 status = "disabled";
 544         };
 545
 546         hscif0: serial@e62c0000 {
 547                 compatible = "renesas,hscif-r8a7794",
 548                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 549                 reg = <0 0xe62c0000 0 96>;
 550                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 552                          <&scif_clk>;
 553                 clock-names = "fck", "brg_int", "scif_clk";
 554                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 555                        <&dmac1 0x39>, <&dmac1 0x3a>;
 556                 dma-names = "tx", "rx", "tx", "rx";
 557                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 558                 status = "disabled";
 559         };
 560
 561         hscif1: serial@e62c8000 {
 562                 compatible = "renesas,hscif-r8a7794",
 563                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 564                 reg = <0 0xe62c8000 0 96>;
 565                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 566                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 567                          <&scif_clk>;
 568                 clock-names = "fck", "brg_int", "scif_clk";
 569                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 570                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 571                 dma-names = "tx", "rx", "tx", "rx";
 572                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 573                 status = "disabled";
 574         };
 575
 576         hscif2: serial@e62d0000 {
 577                 compatible = "renesas,hscif-r8a7794",
 578                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 579                 reg = <0 0xe62d0000 0 96>;
 580                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 581                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 582                          <&scif_clk>;
 583                 clock-names = "fck", "brg_int", "scif_clk";
 584                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 585                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 586                 dma-names = "tx", "rx", "tx", "rx";
 587                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 588                 status = "disabled";
 589         };
 590
 591         ether: ethernet@ee700000 {
 592                 compatible = "renesas,ether-r8a7794";
 593                 reg = <0 0xee700000 0 0x400>;
 594                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 595                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 596                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 597                 phy-mode = "rmii";
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         avb: ethernet@e6800000 {
 604                 compatible = "renesas,etheravb-r8a7794",
 605                              "renesas,etheravb-rcar-gen2";
 606                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 607                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 609                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 status = "disabled";
 613         };
 614
 615         /* The memory map in the User's Manual maps the cores to bus numbers */
 616         i2c0: i2c@e6508000 {
 617                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 618                 reg = <0 0xe6508000 0 0x40>;
 619                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 621                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 i2c-scl-internal-delay-ns = <6>;
 625                 status = "disabled";
 626         };
 627
 628         i2c1: i2c@e6518000 {
 629                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 630                 reg = <0 0xe6518000 0 0x40>;
 631                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 633                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 i2c-scl-internal-delay-ns = <6>;
 637                 status = "disabled";
 638         };
 639
 640         i2c2: i2c@e6530000 {
 641                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 642                 reg = <0 0xe6530000 0 0x40>;
 643                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 645                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 i2c-scl-internal-delay-ns = <6>;
 649                 status = "disabled";
 650         };
 651
 652         i2c3: i2c@e6540000 {
 653                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 654                 reg = <0 0xe6540000 0 0x40>;
 655                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 656                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 657                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 i2c-scl-internal-delay-ns = <6>;
 661                 status = "disabled";
 662         };
 663
 664         i2c4: i2c@e6520000 {
 665                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 666                 reg = <0 0xe6520000 0 0x40>;
 667                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 669                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 i2c-scl-internal-delay-ns = <6>;
 673                 status = "disabled";
 674         };
 675
 676         i2c5: i2c@e6528000 {
 677                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 678                 reg = <0 0xe6528000 0 0x40>;
 679                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 680                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 681                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 i2c-scl-internal-delay-ns = <6>;
 685                 status = "disabled";
 686         };
 687
 688         i2c6: i2c@e6500000 {
 689                 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
 690                              "renesas,rmobile-iic";
 691                 reg = <0 0xe6500000 0 0x425>;
 692                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 693                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 694                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 695                        <&dmac1 0x61>, <&dmac1 0x62>;
 696                 dma-names = "tx", "rx", "tx", "rx";
 697                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 status = "disabled";
 701         };
 702
 703         i2c7: i2c@e6510000 {
 704                 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
 705                              "renesas,rmobile-iic";
 706                 reg = <0 0xe6510000 0 0x425>;
 707                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 708                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 709                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 710                        <&dmac1 0x65>, <&dmac1 0x66>;
 711                 dma-names = "tx", "rx", "tx", "rx";
 712                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 status = "disabled";
 716         };
 717
 718         mmcif0: mmc@ee200000 {
 719                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 720                 reg = <0 0xee200000 0 0x80>;
 721                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 723                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 724                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 725                 dma-names = "tx", "rx", "tx", "rx";
 726                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 727                 reg-io-width = <4>;
 728                 status = "disabled";
 729         };
 730
 731         sdhi0: sd@ee100000 {
 732                 compatible = "renesas,sdhi-r8a7794";
 733                 reg = <0 0xee100000 0 0x328>;
 734                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 735                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 736                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 737                        <&dmac1 0xcd>, <&dmac1 0xce>;
 738                 dma-names = "tx", "rx", "tx", "rx";
 739                 max-frequency = <195000000>;
 740                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 741                 status = "disabled";
 742         };
 743
 744         sdhi1: sd@ee140000 {
 745                 compatible = "renesas,sdhi-r8a7794";
 746                 reg = <0 0xee140000 0 0x100>;
 747                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 748                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 749                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 750                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 751                 dma-names = "tx", "rx", "tx", "rx";
 752                 max-frequency = <97500000>;
 753                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 754                 status = "disabled";
 755         };
 756
 757         sdhi2: sd@ee160000 {
 758                 compatible = "renesas,sdhi-r8a7794";
 759                 reg = <0 0xee160000 0 0x100>;
 760                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 761                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 762                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 763                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 764                 dma-names = "tx", "rx", "tx", "rx";
 765                 max-frequency = <97500000>;
 766                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 767                 status = "disabled";
 768         };
 769
 770         qspi: spi@e6b10000 {
 771                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 772                 reg = <0 0xe6b10000 0 0x2c>;
 773                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 775                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 776                        <&dmac1 0x17>, <&dmac1 0x18>;
 777                 dma-names = "tx", "rx", "tx", "rx";
 778                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 779                 num-cs = <1>;
 780                 #address-cells = <1>;
 781                 #size-cells = <0>;
 782                 status = "disabled";
 783         };
 784
 785         vin0: video@e6ef0000 {
 786                 compatible = "renesas,vin-r8a7794";
 787                 reg = <0 0xe6ef0000 0 0x1000>;
 788                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 789                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 790                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 791                 status = "disabled";
 792         };
 793
 794         vin1: video@e6ef1000 {
 795                 compatible = "renesas,vin-r8a7794";
 796                 reg = <0 0xe6ef1000 0 0x1000>;
 797                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 798                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 799                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 800                 status = "disabled";
 801         };
 802
 803         pci0: pci@ee090000 {
 804                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 805                 device_type = "pci";
 806                 reg = <0 0xee090000 0 0xc00>,
 807                       <0 0xee080000 0 0x1100>;
 808                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 809                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 810                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 811                 status = "disabled";
 812
 813                 bus-range = <0 0>;
 814                 #address-cells = <3>;
 815                 #size-cells = <2>;
 816                 #interrupt-cells = <1>;
 817                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 818                 interrupt-map-mask = <0xff00 0 0 0x7>;
 819                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 820                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 821                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 822
 823                 usb@0,1 {
 824                         reg = <0x800 0 0 0 0>;
 825                         device_type = "pci";
 826                         phys = <&usb0 0>;
 827                         phy-names = "usb";
 828                 };
 829
 830                 usb@0,2 {
 831                         reg = <0x1000 0 0 0 0>;
 832                         device_type = "pci";
 833                         phys = <&usb0 0>;
 834                         phy-names = "usb";
 835                 };
 836         };
 837
 838         pci1: pci@ee0d0000 {
 839                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 840                 device_type = "pci";
 841                 reg = <0 0xee0d0000 0 0xc00>,
 842                       <0 0xee0c0000 0 0x1100>;
 843                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 844                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 845                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 846                 status = "disabled";
 847
 848                 bus-range = <1 1>;
 849                 #address-cells = <3>;
 850                 #size-cells = <2>;
 851                 #interrupt-cells = <1>;
 852                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 853                 interrupt-map-mask = <0xff00 0 0 0x7>;
 854                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 855                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 856                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 857
 858                 usb@0,1 {
 859                         reg = <0x800 0 0 0 0>;
 860                         device_type = "pci";
 861                         phys = <&usb2 0>;
 862                         phy-names = "usb";
 863                 };
 864
 865                 usb@0,2 {
 866                         reg = <0x1000 0 0 0 0>;
 867                         device_type = "pci";
 868                         phys = <&usb2 0>;
 869                         phy-names = "usb";
 870                 };
 871         };
 872
 873         hsusb: usb@e6590000 {
 874                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 875                 reg = <0 0xe6590000 0 0x100>;
 876                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 877                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 878                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 879                 renesas,buswait = <4>;
 880                 phys = <&usb0 1>;
 881                 phy-names = "usb";
 882                 status = "disabled";
 883         };
 884
 885         usbphy: usb-phy@e6590100 {
 886                 compatible = "renesas,usb-phy-r8a7794",
 887                              "renesas,rcar-gen2-usb-phy";
 888                 reg = <0 0xe6590100 0 0x100>;
 889                 #address-cells = <1>;
 890                 #size-cells = <0>;
 891                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 892                 clock-names = "usbhs";
 893                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 894                 status = "disabled";
 895
 896                 usb0: usb-channel@0 {
 897                         reg = <0>;
 898                         #phy-cells = <1>;
 899                 };
 900                 usb2: usb-channel@2 {
 901                         reg = <2>;
 902                         #phy-cells = <1>;
 903                 };
 904         };
 905
 906         vsp1@fe928000 {
 907                 compatible = "renesas,vsp1";
 908                 reg = <0 0xfe928000 0 0x8000>;
 909                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 910                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
 911                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 912         };
 913
 914         vsp1@fe930000 {
 915                 compatible = "renesas,vsp1";
 916                 reg = <0 0xfe930000 0 0x8000>;
 917                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 918                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
 919                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 920         };
 921
 922         du: display@feb00000 {
 923                 compatible = "renesas,du-r8a7794";
 924                 reg = <0 0xfeb00000 0 0x40000>;
 925                 reg-names = "du";
 926                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 927                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 928                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 929                          <&mstp7_clks R8A7794_CLK_DU1>;
 930                 clock-names = "du.0", "du.1";
 931                 status = "disabled";
 932
 933                 ports {
 934                         #address-cells = <1>;
 935                         #size-cells = <0>;
 936
 937                         port@0 {
 938                                 reg = <0>;
 939                                 du_out_rgb0: endpoint {
 940                                 };
 941                         };
 942                         port@1 {
 943                                 reg = <1>;
 944                                 du_out_rgb1: endpoint {
 945                                 };
 946                         };
 947                 };
 948         };
 949
 950         can0: can@e6e80000 {
 951                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 952                 reg = <0 0xe6e80000 0 0x1000>;
 953                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 954                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 955                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 956                 clock-names = "clkp1", "clkp2", "can_clk";
 957                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 958                 status = "disabled";
 959         };
 960
 961         can1: can@e6e88000 {
 962                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 963                 reg = <0 0xe6e88000 0 0x1000>;
 964                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 965                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 966                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 967                 clock-names = "clkp1", "clkp2", "can_clk";
 968                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 969                 status = "disabled";
 970         };
 971
 972         clocks {
 973                 #address-cells = <2>;
 974                 #size-cells = <2>;
 975                 ranges;
 976
 977                 /* External root clock */
 978                 extal_clk: extal {
 979                         compatible = "fixed-clock";
 980                         #clock-cells = <0>;
 981                         /* This value must be overriden by the board. */
 982                         clock-frequency = <0>;
 983                 };
 984
 985                 /* External USB clock - can be overridden by the board */
 986                 usb_extal_clk: usb_extal {
 987                         compatible = "fixed-clock";
 988                         #clock-cells = <0>;
 989                         clock-frequency = <48000000>;
 990                 };
 991
 992                 /* External CAN clock */
 993                 can_clk: can {
 994                         compatible = "fixed-clock";
 995                         #clock-cells = <0>;
 996                         /* This value must be overridden by the board. */
 997                         clock-frequency = <0>;
 998                 };
 999
1000                 /* External SCIF clock */
1001                 scif_clk: scif {
1002                         compatible = "fixed-clock";
1003                         #clock-cells = <0>;
1004                         /* This value must be overridden by the board. */
1005                         clock-frequency = <0>;
1006                 };
1007
1008                 /*
1009                  * The external audio clocks are configured  as 0 Hz fixed
1010                  * frequency clocks by default.  Boards that provide audio
1011                  * clocks should override them.
1012                  */
1013                 audio_clka: audio_clka {
1014                         compatible = "fixed-clock";
1015                         #clock-cells = <0>;
1016                         clock-frequency = <0>;
1017                 };
1018                 audio_clkb: audio_clkb {
1019                         compatible = "fixed-clock";
1020                         #clock-cells = <0>;
1021                         clock-frequency = <0>;
1022                 };
1023                 audio_clkc: audio_clkc {
1024                         compatible = "fixed-clock";
1025                         #clock-cells = <0>;
1026                         clock-frequency = <0>;
1027                 };
1028
1029                 /* Special CPG clocks */
1030                 cpg_clocks: cpg_clocks@e6150000 {
1031                         compatible = "renesas,r8a7794-cpg-clocks",
1032                                      "renesas,rcar-gen2-cpg-clocks";
1033                         reg = <0 0xe6150000 0 0x1000>;
1034                         clocks = <&extal_clk &usb_extal_clk>;
1035                         #clock-cells = <1>;
1036                         clock-output-names = "main", "pll0", "pll1", "pll3",
1037                                              "lb", "qspi", "sdh", "sd0", "rcan";
1038                         #power-domain-cells = <0>;
1039                 };
1040                 /* Variable factor clocks */
1041                 sd2_clk: sd2@e6150078 {
1042                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1043                         reg = <0 0xe6150078 0 4>;
1044                         clocks = <&pll1_div2_clk>;
1045                         #clock-cells = <0>;
1046                 };
1047                 sd3_clk: sd3@e615026c {
1048                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1049                         reg = <0 0xe615026c 0 4>;
1050                         clocks = <&pll1_div2_clk>;
1051                         #clock-cells = <0>;
1052                 };
1053                 mmc0_clk: mmc0@e6150240 {
1054                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1055                         reg = <0 0xe6150240 0 4>;
1056                         clocks = <&pll1_div2_clk>;
1057                         #clock-cells = <0>;
1058                 };
1059
1060                 /* Fixed factor clocks */
1061                 pll1_div2_clk: pll1_div2 {
1062                         compatible = "fixed-factor-clock";
1063                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1064                         #clock-cells = <0>;
1065                         clock-div = <2>;
1066                         clock-mult = <1>;
1067                 };
1068                 z2_clk: z2 {
1069                         compatible = "fixed-factor-clock";
1070                         clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
1071                         #clock-cells = <0>;
1072                         clock-div = <1>;
1073                         clock-mult = <1>;
1074                 };
1075                 zg_clk: zg {
1076                         compatible = "fixed-factor-clock";
1077                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1078                         #clock-cells = <0>;
1079                         clock-div = <6>;
1080                         clock-mult = <1>;
1081                 };
1082                 zx_clk: zx {
1083                         compatible = "fixed-factor-clock";
1084                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1085                         #clock-cells = <0>;
1086                         clock-div = <3>;
1087                         clock-mult = <1>;
1088                 };
1089                 zs_clk: zs {
1090                         compatible = "fixed-factor-clock";
1091                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1092                         #clock-cells = <0>;
1093                         clock-div = <6>;
1094                         clock-mult = <1>;
1095                 };
1096                 hp_clk: hp {
1097                         compatible = "fixed-factor-clock";
1098                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1099                         #clock-cells = <0>;
1100                         clock-div = <12>;
1101                         clock-mult = <1>;
1102                 };
1103                 i_clk: i {
1104                         compatible = "fixed-factor-clock";
1105                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1106                         #clock-cells = <0>;
1107                         clock-div = <2>;
1108                         clock-mult = <1>;
1109                 };
1110                 b_clk: b {
1111                         compatible = "fixed-factor-clock";
1112                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1113                         #clock-cells = <0>;
1114                         clock-div = <12>;
1115                         clock-mult = <1>;
1116                 };
1117                 p_clk: p {
1118                         compatible = "fixed-factor-clock";
1119                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1120                         #clock-cells = <0>;
1121                         clock-div = <24>;
1122                         clock-mult = <1>;
1123                 };
1124                 cl_clk: cl {
1125                         compatible = "fixed-factor-clock";
1126                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1127                         #clock-cells = <0>;
1128                         clock-div = <48>;
1129                         clock-mult = <1>;
1130                 };
1131                 m2_clk: m2 {
1132                         compatible = "fixed-factor-clock";
1133                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1134                         #clock-cells = <0>;
1135                         clock-div = <8>;
1136                         clock-mult = <1>;
1137                 };
1138                 rclk_clk: rclk {
1139                         compatible = "fixed-factor-clock";
1140                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1141                         #clock-cells = <0>;
1142                         clock-div = <(48 * 1024)>;
1143                         clock-mult = <1>;
1144                 };
1145                 oscclk_clk: oscclk {
1146                         compatible = "fixed-factor-clock";
1147                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1148                         #clock-cells = <0>;
1149                         clock-div = <(12 * 1024)>;
1150                         clock-mult = <1>;
1151                 };
1152                 zb3_clk: zb3 {
1153                         compatible = "fixed-factor-clock";
1154                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1155                         #clock-cells = <0>;
1156                         clock-div = <4>;
1157                         clock-mult = <1>;
1158                 };
1159                 zb3d2_clk: zb3d2 {
1160                         compatible = "fixed-factor-clock";
1161                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1162                         #clock-cells = <0>;
1163                         clock-div = <8>;
1164                         clock-mult = <1>;
1165                 };
1166                 ddr_clk: ddr {
1167                         compatible = "fixed-factor-clock";
1168                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1169                         #clock-cells = <0>;
1170                         clock-div = <8>;
1171                         clock-mult = <1>;
1172                 };
1173                 mp_clk: mp {
1174                         compatible = "fixed-factor-clock";
1175                         clocks = <&pll1_div2_clk>;
1176                         #clock-cells = <0>;
1177                         clock-div = <15>;
1178                         clock-mult = <1>;
1179                 };
1180                 cp_clk: cp {
1181                         compatible = "fixed-factor-clock";
1182                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1183                         #clock-cells = <0>;
1184                         clock-div = <48>;
1185                         clock-mult = <1>;
1186                 };
1187
1188                 acp_clk: acp {
1189                         compatible = "fixed-factor-clock";
1190                         clocks = <&extal_clk>;
1191                         #clock-cells = <0>;
1192                         clock-div = <2>;
1193                         clock-mult = <1>;
1194                 };
1195
1196                 /* Gate clocks */
1197                 mstp0_clks: mstp0_clks@e6150130 {
1198                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1199                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1200                         clocks = <&mp_clk>;
1201                         #clock-cells = <1>;
1202                         clock-indices = <R8A7794_CLK_MSIOF0>;
1203                         clock-output-names = "msiof0";
1204                 };
1205                 mstp1_clks: mstp1_clks@e6150134 {
1206                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1207                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1208                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1209                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1210                                  <&zs_clk>, <&zs_clk>;
1211                         #clock-cells = <1>;
1212                         clock-indices = <
1213                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1214                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1215                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1216                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1217                         >;
1218                         clock-output-names =
1219                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1220                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1221                 };
1222                 mstp2_clks: mstp2_clks@e6150138 {
1223                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1224                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1225                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1226                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1227                                  <&zs_clk>, <&zs_clk>;
1228                         #clock-cells = <1>;
1229                         clock-indices = <
1230                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1231                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1232                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1233                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1234                         >;
1235                         clock-output-names =
1236                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1237                                 "scifb1", "msiof1", "scifb2",
1238                                 "sys-dmac1", "sys-dmac0";
1239                 };
1240                 mstp3_clks: mstp3_clks@e615013c {
1241                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1242                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1243                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1244                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1245                                  <&hp_clk>, <&hp_clk>;
1246                         #clock-cells = <1>;
1247                         clock-indices = <
1248                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1249                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1250                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1251                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1252                         >;
1253                         clock-output-names =
1254                                 "sdhi2", "sdhi1", "sdhi0",
1255                                 "mmcif0", "i2c6", "i2c7",
1256                                 "cmt1", "usbdmac0", "usbdmac1";
1257                 };
1258                 mstp4_clks: mstp4_clks@e6150140 {
1259                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1260                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1261                         clocks = <&cp_clk>, <&zs_clk>;
1262                         #clock-cells = <1>;
1263                         clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>;
1264                         clock-output-names = "irqc", "intc-sys";
1265                 };
1266                 mstp5_clks: mstp5_clks@e6150144 {
1267                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1268                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1269                         clocks = <&hp_clk>, <&p_clk>;
1270                         #clock-cells = <1>;
1271                         clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1272                                          R8A7794_CLK_PWM>;
1273                         clock-output-names = "audmac0", "pwm";
1274                 };
1275                 mstp7_clks: mstp7_clks@e615014c {
1276                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1277                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1278                         clocks = <&mp_clk>, <&hp_clk>,
1279                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1280                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1281                                  <&zx_clk>, <&zx_clk>;
1282                         #clock-cells = <1>;
1283                         clock-indices = <
1284                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1285                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1286                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1287                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1288                                 R8A7794_CLK_SCIF0
1289                                 R8A7794_CLK_DU1 R8A7794_CLK_DU0
1290                         >;
1291                         clock-output-names =
1292                                 "ehci", "hsusb",
1293                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1294                                 "scif3", "scif2", "scif1", "scif0",
1295                                 "du1", "du0";
1296                 };
1297                 mstp8_clks: mstp8_clks@e6150990 {
1298                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1299                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1300                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1301                         #clock-cells = <1>;
1302                         clock-indices = <
1303                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1304                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1305                         >;
1306                         clock-output-names =
1307                                 "vin1", "vin0", "etheravb", "ether";
1308                 };
1309                 mstp9_clks: mstp9_clks@e6150994 {
1310                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1311                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1312                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1313                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1314                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1315                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1316                                  <&hp_clk>, <&hp_clk>;
1317                         #clock-cells = <1>;
1318                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1319                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1320                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1321                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1322                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1323                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1324                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1325                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1326                         clock-output-names =
1327                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1328                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1329                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1330                 };
1331                 mstp10_clks: mstp10_clks@e6150998 {
1332                         compatible = "renesas,r8a7794-mstp-clocks",
1333                                      "renesas,cpg-mstp-clocks";
1334                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1335                         clocks = <&p_clk>,
1336                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1337                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1338                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1339                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1340                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1341                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1342                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1343                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1344                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1345                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1346                                  <&p_clk>,
1347                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1348                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1349                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1350                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1351                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1352                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1353                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1354                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1355                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1356                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1357                         #clock-cells = <1>;
1358                         clock-indices = <R8A7794_CLK_SSI_ALL
1359                                          R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1360                                          R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1361                                          R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1362                                          R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1363                                          R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1364                                          R8A7794_CLK_SCU_ALL
1365                                          R8A7794_CLK_SCU_DVC1
1366                                          R8A7794_CLK_SCU_DVC0
1367                                          R8A7794_CLK_SCU_CTU1_MIX1
1368                                          R8A7794_CLK_SCU_CTU0_MIX0
1369                                          R8A7794_CLK_SCU_SRC6
1370                                          R8A7794_CLK_SCU_SRC5
1371                                          R8A7794_CLK_SCU_SRC4
1372                                          R8A7794_CLK_SCU_SRC3
1373                                          R8A7794_CLK_SCU_SRC2
1374                                          R8A7794_CLK_SCU_SRC1>;
1375                         clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1376                                              "ssi6", "ssi5", "ssi4", "ssi3",
1377                                              "ssi2", "ssi1", "ssi0",
1378                                              "scu-all", "scu-dvc1", "scu-dvc0",
1379                                              "scu-ctu1-mix1", "scu-ctu0-mix0",
1380                                              "scu-src6", "scu-src5", "scu-src4",
1381                                              "scu-src3", "scu-src2", "scu-src1";
1382                 };
1383                 mstp11_clks: mstp11_clks@e615099c {
1384                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1385                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1386                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1387                         #clock-cells = <1>;
1388                         clock-indices = <
1389                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1390                         >;
1391                         clock-output-names = "scifa3", "scifa4", "scifa5";
1392                 };
1393         };
1394
1395         rst: reset-controller@e6160000 {
1396                 compatible = "renesas,r8a7794-rst";
1397                 reg = <0 0xe6160000 0 0x0100>;
1398         };
1399
1400         prr: chipid@ff000044 {
1401                 compatible = "renesas,prr";
1402                 reg = <0 0xff000044 0 4>;
1403         };
1404
1405         sysc: system-controller@e6180000 {
1406                 compatible = "renesas,r8a7794-sysc";
1407                 reg = <0 0xe6180000 0 0x0200>;
1408                 #power-domain-cells = <1>;
1409         };
1410
1411         ipmmu_sy0: mmu@e6280000 {
1412                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1413                 reg = <0 0xe6280000 0 0x1000>;
1414                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1415                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1416                 #iommu-cells = <1>;
1417                 status = "disabled";
1418         };
1419
1420         ipmmu_sy1: mmu@e6290000 {
1421                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1422                 reg = <0 0xe6290000 0 0x1000>;
1423                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1424                 #iommu-cells = <1>;
1425                 status = "disabled";
1426         };
1427
1428         ipmmu_ds: mmu@e6740000 {
1429                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1430                 reg = <0 0xe6740000 0 0x1000>;
1431                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1432                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1433                 #iommu-cells = <1>;
1434                 status = "disabled";
1435         };
1436
1437         ipmmu_mp: mmu@ec680000 {
1438                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1439                 reg = <0 0xec680000 0 0x1000>;
1440                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1441                 #iommu-cells = <1>;
1442                 status = "disabled";
1443         };
1444
1445         ipmmu_mx: mmu@fe951000 {
1446                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1447                 reg = <0 0xfe951000 0 0x1000>;
1448                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1449                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1450                 #iommu-cells = <1>;
1451                 status = "disabled";
1452         };
1453
1454         ipmmu_gp: mmu@e62a0000 {
1455                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1456                 reg = <0 0xe62a0000 0 0x1000>;
1457                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1458                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1459                 #iommu-cells = <1>;
1460                 status = "disabled";
1461         };
1462
1463         rcar_sound: sound@ec500000 {
1464                 /*
1465                  * #sound-dai-cells is required
1466                  *
1467                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1468                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1469                  */
1470                 compatible = "renesas,rcar_sound-r8a7794",
1471                              "renesas,rcar_sound-gen2";
1472                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1473                         <0 0xec5a0000 0 0x100>,  /* ADG */
1474                         <0 0xec540000 0 0x1000>, /* SSIU */
1475                         <0 0xec541000 0 0x280>,  /* SSI */
1476                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1477                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1478
1479                 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1480                          <&mstp10_clks R8A7794_CLK_SSI9>,
1481                          <&mstp10_clks R8A7794_CLK_SSI8>,
1482                          <&mstp10_clks R8A7794_CLK_SSI7>,
1483                          <&mstp10_clks R8A7794_CLK_SSI6>,
1484                          <&mstp10_clks R8A7794_CLK_SSI5>,
1485                          <&mstp10_clks R8A7794_CLK_SSI4>,
1486                          <&mstp10_clks R8A7794_CLK_SSI3>,
1487                          <&mstp10_clks R8A7794_CLK_SSI2>,
1488                          <&mstp10_clks R8A7794_CLK_SSI1>,
1489                          <&mstp10_clks R8A7794_CLK_SSI0>,
1490                          <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1491                          <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1492                          <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1493                          <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1494                          <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1495                          <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1496                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1497                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1498                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1499                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1500                          <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1501                          <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1502                          <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1503                          <&m2_clk>;
1504                 clock-names = "ssi-all",
1505                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1506                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1507                               "src.6", "src.5", "src.4", "src.3", "src.2",
1508                               "src.1",
1509                               "ctu.0", "ctu.1",
1510                               "mix.0", "mix.1",
1511                               "dvc.0", "dvc.1",
1512                               "clk_a", "clk_b", "clk_c", "clk_i";
1513                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1514
1515                 status = "disabled";
1516
1517                 rcar_sound,dvc {
1518                         dvc0: dvc-0 {
1519                                 dmas = <&audma0 0xbc>;
1520                                 dma-names = "tx";
1521                         };
1522                         dvc1: dvc-1 {
1523                                 dmas = <&audma0 0xbe>;
1524                                 dma-names = "tx";
1525                         };
1526                 };
1527
1528                 rcar_sound,mix {
1529                         mix0: mix-0 { };
1530                         mix1: mix-1 { };
1531                 };
1532
1533                 rcar_sound,ctu {
1534                         ctu00: ctu-0 { };
1535                         ctu01: ctu-1 { };
1536                         ctu02: ctu-2 { };
1537                         ctu03: ctu-3 { };
1538                         ctu10: ctu-4 { };
1539                         ctu11: ctu-5 { };
1540                         ctu12: ctu-6 { };
1541                         ctu13: ctu-7 { };
1542                 };
1543
1544                 rcar_sound,src {
1545                         src-0 {
1546                                 status = "disabled";
1547                         };
1548                         src1: src-1 {
1549                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1550                                 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1551                                 dma-names = "rx", "tx";
1552                         };
1553                         src2: src-2 {
1554                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1555                                 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1556                                 dma-names = "rx", "tx";
1557                         };
1558                         src3: src-3 {
1559                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1560                                 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1561                                 dma-names = "rx", "tx";
1562                         };
1563                         src4: src-4 {
1564                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1565                                 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1566                                 dma-names = "rx", "tx";
1567                         };
1568                         src5: src-5 {
1569                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1570                                 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1571                                 dma-names = "rx", "tx";
1572                         };
1573                         src6: src-6 {
1574                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1575                                 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1576                                 dma-names = "rx", "tx";
1577                         };
1578                 };
1579
1580                 rcar_sound,ssi {
1581                         ssi0: ssi-0 {
1582                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1583                                 dmas = <&audma0 0x01>, <&audma0 0x02>,
1584                                        <&audma0 0x15>, <&audma0 0x16>;
1585                                 dma-names = "rx", "tx", "rxu", "txu";
1586                         };
1587                         ssi1: ssi-1 {
1588                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1589                                 dmas = <&audma0 0x03>, <&audma0 0x04>,
1590                                        <&audma0 0x49>, <&audma0 0x4a>;
1591                                 dma-names = "rx", "tx", "rxu", "txu";
1592                         };
1593                         ssi2: ssi-2 {
1594                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1595                                 dmas = <&audma0 0x05>, <&audma0 0x06>,
1596                                        <&audma0 0x63>, <&audma0 0x64>;
1597                                 dma-names = "rx", "tx", "rxu", "txu";
1598                         };
1599                         ssi3: ssi-3 {
1600                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1601                                 dmas = <&audma0 0x07>, <&audma0 0x08>,
1602                                        <&audma0 0x6f>, <&audma0 0x70>;
1603                                 dma-names = "rx", "tx", "rxu", "txu";
1604                         };
1605                         ssi4: ssi-4 {
1606                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1607                                 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1608                                        <&audma0 0x71>, <&audma0 0x72>;
1609                                 dma-names = "rx", "tx", "rxu", "txu";
1610                         };
1611                         ssi5: ssi-5 {
1612                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1613                                 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1614                                        <&audma0 0x73>, <&audma0 0x74>;
1615                                 dma-names = "rx", "tx", "rxu", "txu";
1616                         };
1617                         ssi6: ssi-6 {
1618                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1619                                 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1620                                        <&audma0 0x75>, <&audma0 0x76>;
1621                                 dma-names = "rx", "tx", "rxu", "txu";
1622                         };
1623                         ssi7: ssi-7 {
1624                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1625                                 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1626                                        <&audma0 0x79>, <&audma0 0x7a>;
1627                                 dma-names = "rx", "tx", "rxu", "txu";
1628                         };
1629                         ssi8: ssi-8 {
1630                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1631                                 dmas = <&audma0 0x11>, <&audma0 0x12>,
1632                                        <&audma0 0x7b>, <&audma0 0x7c>;
1633                                 dma-names = "rx", "tx", "rxu", "txu";
1634                         };
1635                         ssi9: ssi-9 {
1636                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1637                                 dmas = <&audma0 0x13>, <&audma0 0x14>,
1638                                        <&audma0 0x7d>, <&audma0 0x7e>;
1639                                 dma-names = "rx", "tx", "rxu", "txu";
1640                         };
1641                 };
1642         };
1643 };