arch/arm/boot/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a7792-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7792";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 spi0 = &qspi;
  29                 spi1 = &msiof0;
  30                 spi2 = &msiof1;
  31                 vin0 = &vin0;
  32                 vin1 = &vin1;
  33                 vin2 = &vin2;
  34                 vin3 = &vin3;
  35                 vin4 = &vin4;
  36                 vin5 = &vin5;
  37         };
  38
  39         /* External CAN clock */
  40         can_clk: can {
  41                 compatible = "fixed-clock";
  42                 #clock-cells = <0>;
  43                 /* This value must be overridden by the board. */
  44                 clock-frequency = <0>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "renesas,apmu";
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <0>;
  56                         clock-frequency = <1000000000>;
  57                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  58                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  59                         next-level-cache = <&L2_CA15>;
  60                 };
  61
  62                 cpu1: cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <1>;
  66                         clock-frequency = <1000000000>;
  67                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  68                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  69                         next-level-cache = <&L2_CA15>;
  70                 };
  71
  72                 L2_CA15: cache-controller-0 {
  73                         compatible = "cache";
  74                         cache-unified;
  75                         cache-level = <2>;
  76                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  77                 };
  78         };
  79
  80         /* External root clock */
  81         extal_clk: extal {
  82                 compatible = "fixed-clock";
  83                 #clock-cells = <0>;
  84                 /* This value must be overridden by the board. */
  85                 clock-frequency = <0>;
  86         };
  87
  88         /* External SCIF clock */
  89         scif_clk: scif {
  90                 compatible = "fixed-clock";
  91                 #clock-cells = <0>;
  92                 /* This value must be overridden by the board. */
  93                 clock-frequency = <0>;
  94         };
  95
  96         soc {
  97                 compatible = "simple-bus";
  98                 interrupt-parent = <&gic>;
  99
 100                 #address-cells = <2>;
 101                 #size-cells = <2>;
 102                 ranges;
 103
 104                 apmu@e6152000 {
 105                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
 106                         reg = <0 0xe6152000 0 0x188>;
 107                         cpus = <&cpu0 &cpu1>;
 108                 };
 109
 110                 gic: interrupt-controller@f1001000 {
 111                         compatible = "arm,gic-400";
 112                         #interrupt-cells = <3>;
 113                         interrupt-controller;
 114                         reg = <0 0xf1001000 0 0x1000>,
 115                               <0 0xf1002000 0 0x2000>,
 116                               <0 0xf1004000 0 0x2000>,
 117                               <0 0xf1006000 0 0x2000>;
 118                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 119                                       IRQ_TYPE_LEVEL_HIGH)>;
 120                         clocks = <&cpg CPG_MOD 408>;
 121                         clock-names = "clk";
 122                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 123                         resets = <&cpg 408>;
 124                 };
 125
 126                 irqc: interrupt-controller@e61c0000 {
 127                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 128                         #interrupt-cells = <2>;
 129                         interrupt-controller;
 130                         reg = <0 0xe61c0000 0 0x200>;
 131                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&cpg CPG_MOD 407>;
 136                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 137                         resets = <&cpg 407>;
 138                 };
 139
 140                 rst: reset-controller@e6160000 {
 141                         compatible = "renesas,r8a7792-rst";
 142                         reg = <0 0xe6160000 0 0x0100>;
 143                 };
 144
 145                 prr: chipid@ff000044 {
 146                         compatible = "renesas,prr";
 147                         reg = <0 0xff000044 0 4>;
 148                 };
 149
 150                 sysc: system-controller@e6180000 {
 151                         compatible = "renesas,r8a7792-sysc";
 152                         reg = <0 0xe6180000 0 0x0200>;
 153                         #power-domain-cells = <1>;
 154                 };
 155
 156                 pfc: pin-controller@e6060000 {
 157                         compatible = "renesas,pfc-r8a7792";
 158                         reg = <0 0xe6060000 0 0x144>;
 159                 };
 160
 161                 gpio0: gpio@e6050000 {
 162                         compatible = "renesas,gpio-r8a7792",
 163                                      "renesas,rcar-gen2-gpio";
 164                         reg = <0 0xe6050000 0 0x50>;
 165                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 166                         #gpio-cells = <2>;
 167                         gpio-controller;
 168                         gpio-ranges = <&pfc 0 0 29>;
 169                         #interrupt-cells = <2>;
 170                         interrupt-controller;
 171                         clocks = <&cpg CPG_MOD 912>;
 172                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 173                         resets = <&cpg 912>;
 174                 };
 175
 176                 gpio1: gpio@e6051000 {
 177                         compatible = "renesas,gpio-r8a7792",
 178                                      "renesas,rcar-gen2-gpio";
 179                         reg = <0 0xe6051000 0 0x50>;
 180                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 181                         #gpio-cells = <2>;
 182                         gpio-controller;
 183                         gpio-ranges = <&pfc 0 32 23>;
 184                         #interrupt-cells = <2>;
 185                         interrupt-controller;
 186                         clocks = <&cpg CPG_MOD 911>;
 187                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 188                         resets = <&cpg 911>;
 189                 };
 190
 191                 gpio2: gpio@e6052000 {
 192                         compatible = "renesas,gpio-r8a7792",
 193                                      "renesas,rcar-gen2-gpio";
 194                         reg = <0 0xe6052000 0 0x50>;
 195                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 196                         #gpio-cells = <2>;
 197                         gpio-controller;
 198                         gpio-ranges = <&pfc 0 64 32>;
 199                         #interrupt-cells = <2>;
 200                         interrupt-controller;
 201                         clocks = <&cpg CPG_MOD 910>;
 202                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 203                         resets = <&cpg 910>;
 204                 };
 205
 206                 gpio3: gpio@e6053000 {
 207                         compatible = "renesas,gpio-r8a7792",
 208                                      "renesas,rcar-gen2-gpio";
 209                         reg = <0 0xe6053000 0 0x50>;
 210                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 211                         #gpio-cells = <2>;
 212                         gpio-controller;
 213                         gpio-ranges = <&pfc 0 96 28>;
 214                         #interrupt-cells = <2>;
 215                         interrupt-controller;
 216                         clocks = <&cpg CPG_MOD 909>;
 217                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 218                         resets = <&cpg 909>;
 219                 };
 220
 221                 gpio4: gpio@e6054000 {
 222                         compatible = "renesas,gpio-r8a7792",
 223                                      "renesas,rcar-gen2-gpio";
 224                         reg = <0 0xe6054000 0 0x50>;
 225                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 226                         #gpio-cells = <2>;
 227                         gpio-controller;
 228                         gpio-ranges = <&pfc 0 128 17>;
 229                         #interrupt-cells = <2>;
 230                         interrupt-controller;
 231                         clocks = <&cpg CPG_MOD 908>;
 232                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 233                         resets = <&cpg 908>;
 234                 };
 235
 236                 gpio5: gpio@e6055000 {
 237                         compatible = "renesas,gpio-r8a7792",
 238                                      "renesas,rcar-gen2-gpio";
 239                         reg = <0 0xe6055000 0 0x50>;
 240                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 241                         #gpio-cells = <2>;
 242                         gpio-controller;
 243                         gpio-ranges = <&pfc 0 160 17>;
 244                         #interrupt-cells = <2>;
 245                         interrupt-controller;
 246                         clocks = <&cpg CPG_MOD 907>;
 247                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 248                         resets = <&cpg 907>;
 249                 };
 250
 251                 gpio6: gpio@e6055100 {
 252                         compatible = "renesas,gpio-r8a7792",
 253                                      "renesas,rcar-gen2-gpio";
 254                         reg = <0 0xe6055100 0 0x50>;
 255                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 256                         #gpio-cells = <2>;
 257                         gpio-controller;
 258                         gpio-ranges = <&pfc 0 192 17>;
 259                         #interrupt-cells = <2>;
 260                         interrupt-controller;
 261                         clocks = <&cpg CPG_MOD 905>;
 262                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 263                         resets = <&cpg 905>;
 264                 };
 265
 266                 gpio7: gpio@e6055200 {
 267                         compatible = "renesas,gpio-r8a7792",
 268                                      "renesas,rcar-gen2-gpio";
 269                         reg = <0 0xe6055200 0 0x50>;
 270                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 271                         #gpio-cells = <2>;
 272                         gpio-controller;
 273                         gpio-ranges = <&pfc 0 224 17>;
 274                         #interrupt-cells = <2>;
 275                         interrupt-controller;
 276                         clocks = <&cpg CPG_MOD 904>;
 277                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 278                         resets = <&cpg 904>;
 279                 };
 280
 281                 gpio8: gpio@e6055300 {
 282                         compatible = "renesas,gpio-r8a7792",
 283                                      "renesas,rcar-gen2-gpio";
 284                         reg = <0 0xe6055300 0 0x50>;
 285                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 286                         #gpio-cells = <2>;
 287                         gpio-controller;
 288                         gpio-ranges = <&pfc 0 256 17>;
 289                         #interrupt-cells = <2>;
 290                         interrupt-controller;
 291                         clocks = <&cpg CPG_MOD 921>;
 292                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 293                         resets = <&cpg 921>;
 294                 };
 295
 296                 gpio9: gpio@e6055400 {
 297                         compatible = "renesas,gpio-r8a7792",
 298                                      "renesas,rcar-gen2-gpio";
 299                         reg = <0 0xe6055400 0 0x50>;
 300                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 301                         #gpio-cells = <2>;
 302                         gpio-controller;
 303                         gpio-ranges = <&pfc 0 288 17>;
 304                         #interrupt-cells = <2>;
 305                         interrupt-controller;
 306                         clocks = <&cpg CPG_MOD 919>;
 307                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 308                         resets = <&cpg 919>;
 309                 };
 310
 311                 gpio10: gpio@e6055500 {
 312                         compatible = "renesas,gpio-r8a7792",
 313                                      "renesas,rcar-gen2-gpio";
 314                         reg = <0 0xe6055500 0 0x50>;
 315                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 316                         #gpio-cells = <2>;
 317                         gpio-controller;
 318                         gpio-ranges = <&pfc 0 320 32>;
 319                         #interrupt-cells = <2>;
 320                         interrupt-controller;
 321                         clocks = <&cpg CPG_MOD 914>;
 322                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 323                         resets = <&cpg 914>;
 324                 };
 325
 326                 gpio11: gpio@e6055600 {
 327                         compatible = "renesas,gpio-r8a7792",
 328                                      "renesas,rcar-gen2-gpio";
 329                         reg = <0 0xe6055600 0 0x50>;
 330                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 331                         #gpio-cells = <2>;
 332                         gpio-controller;
 333                         gpio-ranges = <&pfc 0 352 30>;
 334                         #interrupt-cells = <2>;
 335                         interrupt-controller;
 336                         clocks = <&cpg CPG_MOD 913>;
 337                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 338                         resets = <&cpg 913>;
 339                 };
 340
 341                 dmac0: dma-controller@e6700000 {
 342                         compatible = "renesas,dmac-r8a7792",
 343                                      "renesas,rcar-dmac";
 344                         reg = <0 0xe6700000 0 0x20000>;
 345                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 346                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 347                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 348                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 349                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 350                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 351                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 352                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 353                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 354                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 355                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 356                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 357                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 358                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 359                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 360                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 361                         interrupt-names = "error",
 362                                           "ch0", "ch1", "ch2", "ch3",
 363                                           "ch4", "ch5", "ch6", "ch7",
 364                                           "ch8", "ch9", "ch10", "ch11",
 365                                           "ch12", "ch13", "ch14";
 366                         clocks = <&cpg CPG_MOD 219>;
 367                         clock-names = "fck";
 368                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 369                         resets = <&cpg 219>;
 370                         #dma-cells = <1>;
 371                         dma-channels = <15>;
 372                 };
 373
 374                 dmac1: dma-controller@e6720000 {
 375                         compatible = "renesas,dmac-r8a7792",
 376                                      "renesas,rcar-dmac";
 377                         reg = <0 0xe6720000 0 0x20000>;
 378                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 379                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 380                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 381                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 382                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 383                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 384                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 385                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 386                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 387                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 388                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 389                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 390                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 391                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 392                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 393                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 394                         interrupt-names = "error",
 395                                           "ch0", "ch1", "ch2", "ch3",
 396                                           "ch4", "ch5", "ch6", "ch7",
 397                                           "ch8", "ch9", "ch10", "ch11",
 398                                           "ch12", "ch13", "ch14";
 399                         clocks = <&cpg CPG_MOD 218>;
 400                         clock-names = "fck";
 401                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 402                         resets = <&cpg 218>;
 403                         #dma-cells = <1>;
 404                         dma-channels = <15>;
 405                 };
 406
 407                 scif0: serial@e6e60000 {
 408                         compatible = "renesas,scif-r8a7792",
 409                                      "renesas,rcar-gen2-scif", "renesas,scif";
 410                         reg = <0 0xe6e60000 0 64>;
 411                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 412                         clocks = <&cpg CPG_MOD 721>,
 413                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 414                         clock-names = "fck", "brg_int", "scif_clk";
 415                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 416                                <&dmac1 0x29>, <&dmac1 0x2a>;
 417                         dma-names = "tx", "rx", "tx", "rx";
 418                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 419                         resets = <&cpg 721>;
 420                         status = "disabled";
 421                 };
 422
 423                 scif1: serial@e6e68000 {
 424                         compatible = "renesas,scif-r8a7792",
 425                                      "renesas,rcar-gen2-scif", "renesas,scif";
 426                         reg = <0 0xe6e68000 0 64>;
 427                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&cpg CPG_MOD 720>,
 429                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 430                         clock-names = "fck", "brg_int", "scif_clk";
 431                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 432                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 433                         dma-names = "tx", "rx", "tx", "rx";
 434                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 435                         resets = <&cpg 720>;
 436                         status = "disabled";
 437                 };
 438
 439                 scif2: serial@e6e58000 {
 440                         compatible = "renesas,scif-r8a7792",
 441                                      "renesas,rcar-gen2-scif", "renesas,scif";
 442                         reg = <0 0xe6e58000 0 64>;
 443                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 444                         clocks = <&cpg CPG_MOD 719>,
 445                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 446                         clock-names = "fck", "brg_int", "scif_clk";
 447                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 448                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 449                         dma-names = "tx", "rx", "tx", "rx";
 450                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 451                         resets = <&cpg 719>;
 452                         status = "disabled";
 453                 };
 454
 455                 scif3: serial@e6ea8000 {
 456                         compatible = "renesas,scif-r8a7792",
 457                                      "renesas,rcar-gen2-scif", "renesas,scif";
 458                         reg = <0 0xe6ea8000 0 64>;
 459                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&cpg CPG_MOD 718>,
 461                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 462                         clock-names = "fck", "brg_int", "scif_clk";
 463                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 464                                <&dmac1 0x2f>, <&dmac1 0x30>;
 465                         dma-names = "tx", "rx", "tx", "rx";
 466                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 467                         resets = <&cpg 718>;
 468                         status = "disabled";
 469                 };
 470
 471                 hscif0: serial@e62c0000 {
 472                         compatible = "renesas,hscif-r8a7792",
 473                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 474                         reg = <0 0xe62c0000 0 96>;
 475                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&cpg CPG_MOD 717>,
 477                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 478                         clock-names = "fck", "brg_int", "scif_clk";
 479                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 480                                <&dmac1 0x39>, <&dmac1 0x3a>;
 481                         dma-names = "tx", "rx", "tx", "rx";
 482                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 483                         resets = <&cpg 717>;
 484                         status = "disabled";
 485                 };
 486
 487                 hscif1: serial@e62c8000 {
 488                         compatible = "renesas,hscif-r8a7792",
 489                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 490                         reg = <0 0xe62c8000 0 96>;
 491                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&cpg CPG_MOD 716>,
 493                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 494                         clock-names = "fck", "brg_int", "scif_clk";
 495                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 496                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 497                         dma-names = "tx", "rx", "tx", "rx";
 498                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 499                         resets = <&cpg 716>;
 500                         status = "disabled";
 501                 };
 502
 503                 icram0: sram@e63a0000 {
 504                         compatible = "mmio-sram";
 505                         reg = <0 0xe63a0000 0 0x12000>;
 506                 };
 507
 508                 icram1: sram@e63c0000 {
 509                         compatible = "mmio-sram";
 510                         reg = <0 0xe63c0000 0 0x1000>;
 511                         #address-cells = <1>;
 512                         #size-cells = <1>;
 513                         ranges = <0 0 0xe63c0000 0x1000>;
 514
 515                         smp-sram@0 {
 516                                 compatible = "renesas,smp-sram";
 517                                 reg = <0 0x10>;
 518                         };
 519                 };
 520
 521                 sdhi0: sd@ee100000 {
 522                         compatible = "renesas,sdhi-r8a7792",
 523                                      "renesas,rcar-gen2-sdhi";
 524                         reg = <0 0xee100000 0 0x328>;
 525                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 526                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 527                                <&dmac1 0xcd>, <&dmac1 0xce>;
 528                         dma-names = "tx", "rx", "tx", "rx";
 529                         clocks = <&cpg CPG_MOD 314>;
 530                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 531                         resets = <&cpg 314>;
 532                         status = "disabled";
 533                 };
 534
 535                 jpu: jpeg-codec@fe980000 {
 536                         compatible = "renesas,jpu-r8a7792",
 537                                      "renesas,rcar-gen2-jpu";
 538                         reg = <0 0xfe980000 0 0x10300>;
 539                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&cpg CPG_MOD 106>;
 541                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 542                         resets = <&cpg 106>;
 543                 };
 544
 545                 avb: ethernet@e6800000 {
 546                         compatible = "renesas,etheravb-r8a7792",
 547                                      "renesas,etheravb-rcar-gen2";
 548                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 549                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&cpg CPG_MOD 812>;
 551                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 552                         resets = <&cpg 812>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         status = "disabled";
 556                 };
 557
 558                 /* I2C doesn't need pinmux */
 559                 i2c0: i2c@e6508000 {
 560                         compatible = "renesas,i2c-r8a7792",
 561                                      "renesas,rcar-gen2-i2c";
 562                         reg = <0 0xe6508000 0 0x40>;
 563                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cpg CPG_MOD 931>;
 565                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 566                         resets = <&cpg 931>;
 567                         i2c-scl-internal-delay-ns = <6>;
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         status = "disabled";
 571                 };
 572
 573                 i2c1: i2c@e6518000 {
 574                         compatible = "renesas,i2c-r8a7792",
 575                                      "renesas,rcar-gen2-i2c";
 576                         reg = <0 0xe6518000 0 0x40>;
 577                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&cpg CPG_MOD 930>;
 579                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 580                         resets = <&cpg 930>;
 581                         i2c-scl-internal-delay-ns = <6>;
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 i2c2: i2c@e6530000 {
 588                         compatible = "renesas,i2c-r8a7792",
 589                                      "renesas,rcar-gen2-i2c";
 590                         reg = <0 0xe6530000 0 0x40>;
 591                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 592                         clocks = <&cpg CPG_MOD 929>;
 593                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 594                         resets = <&cpg 929>;
 595                         i2c-scl-internal-delay-ns = <6>;
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         status = "disabled";
 599                 };
 600
 601                 i2c3: i2c@e6540000 {
 602                         compatible = "renesas,i2c-r8a7792",
 603                                      "renesas,rcar-gen2-i2c";
 604                         reg = <0 0xe6540000 0 0x40>;
 605                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&cpg CPG_MOD 928>;
 607                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 608                         resets = <&cpg 928>;
 609                         i2c-scl-internal-delay-ns = <6>;
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         status = "disabled";
 613                 };
 614
 615                 i2c4: i2c@e6520000 {
 616                         compatible = "renesas,i2c-r8a7792",
 617                                      "renesas,rcar-gen2-i2c";
 618                         reg = <0 0xe6520000 0 0x40>;
 619                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&cpg CPG_MOD 927>;
 621                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 622                         resets = <&cpg 927>;
 623                         i2c-scl-internal-delay-ns = <6>;
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         status = "disabled";
 627                 };
 628
 629                 i2c5: i2c@e6528000 {
 630                         compatible = "renesas,i2c-r8a7792",
 631                                      "renesas,rcar-gen2-i2c";
 632                         reg = <0 0xe6528000 0 0x40>;
 633                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&cpg CPG_MOD 925>;
 635                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 636                         resets = <&cpg 925>;
 637                         i2c-scl-internal-delay-ns = <110>;
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         status = "disabled";
 641                 };
 642
 643                 qspi: spi@e6b10000 {
 644                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 645                         reg = <0 0xe6b10000 0 0x2c>;
 646                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 647                         clocks = <&cpg CPG_MOD 917>;
 648                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 649                                <&dmac1 0x17>, <&dmac1 0x18>;
 650                         dma-names = "tx", "rx", "tx", "rx";
 651                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 652                         resets = <&cpg 917>;
 653                         num-cs = <1>;
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                         status = "disabled";
 657                 };
 658
 659                 msiof0: spi@e6e20000 {
 660                         compatible = "renesas,msiof-r8a7792",
 661                                      "renesas,rcar-gen2-msiof";
 662                         reg = <0 0xe6e20000 0 0x0064>;
 663                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 664                         clocks = <&cpg CPG_MOD 000>;
 665                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 666                                <&dmac1 0x51>, <&dmac1 0x52>;
 667                         dma-names = "tx", "rx", "tx", "rx";
 668                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 669                         resets = <&cpg 000>;
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                         status = "disabled";
 673                 };
 674
 675                 msiof1: spi@e6e10000 {
 676                         compatible = "renesas,msiof-r8a7792",
 677                                      "renesas,rcar-gen2-msiof";
 678                         reg = <0 0xe6e10000 0 0x0064>;
 679                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&cpg CPG_MOD 208>;
 681                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 682                                <&dmac1 0x55>, <&dmac1 0x56>;
 683                         dma-names = "tx", "rx", "tx", "rx";
 684                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 685                         resets = <&cpg 208>;
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         status = "disabled";
 689                 };
 690
 691                 du: display@feb00000 {
 692                         compatible = "renesas,du-r8a7792";
 693                         reg = <0 0xfeb00000 0 0x40000>;
 694                         reg-names = "du";
 695                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&cpg CPG_MOD 724>,
 698                                  <&cpg CPG_MOD 723>;
 699                         clock-names = "du.0", "du.1";
 700                         status = "disabled";
 701
 702                         ports {
 703                                 #address-cells = <1>;
 704                                 #size-cells = <0>;
 705
 706                                 port@0 {
 707                                         reg = <0>;
 708                                         du_out_rgb0: endpoint {
 709                                         };
 710                                 };
 711                                 port@1 {
 712                                         reg = <1>;
 713                                         du_out_rgb1: endpoint {
 714                                         };
 715                                 };
 716                         };
 717                 };
 718
 719                 can0: can@e6e80000 {
 720                         compatible = "renesas,can-r8a7792",
 721                                      "renesas,rcar-gen2-can";
 722                         reg = <0 0xe6e80000 0 0x1000>;
 723                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&cpg CPG_MOD 916>,
 725                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 726                         clock-names = "clkp1", "clkp2", "can_clk";
 727                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 728                         resets = <&cpg 916>;
 729                         status = "disabled";
 730                 };
 731
 732                 can1: can@e6e88000 {
 733                         compatible = "renesas,can-r8a7792",
 734                                      "renesas,rcar-gen2-can";
 735                         reg = <0 0xe6e88000 0 0x1000>;
 736                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 737                         clocks = <&cpg CPG_MOD 915>,
 738                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 739                         clock-names = "clkp1", "clkp2", "can_clk";
 740                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 741                         resets = <&cpg 915>;
 742                         status = "disabled";
 743                 };
 744
 745                 vin0: video@e6ef0000 {
 746                         compatible = "renesas,vin-r8a7792",
 747                                      "renesas,rcar-gen2-vin";
 748                         reg = <0 0xe6ef0000 0 0x1000>;
 749                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 750                         clocks = <&cpg CPG_MOD 811>;
 751                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 752                         resets = <&cpg 811>;
 753                         status = "disabled";
 754                 };
 755
 756                 vin1: video@e6ef1000 {
 757                         compatible = "renesas,vin-r8a7792",
 758                                      "renesas,rcar-gen2-vin";
 759                         reg = <0 0xe6ef1000 0 0x1000>;
 760                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&cpg CPG_MOD 810>;
 762                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 763                         resets = <&cpg 810>;
 764                         status = "disabled";
 765                 };
 766
 767                 vin2: video@e6ef2000 {
 768                         compatible = "renesas,vin-r8a7792",
 769                                      "renesas,rcar-gen2-vin";
 770                         reg = <0 0xe6ef2000 0 0x1000>;
 771                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 772                         clocks = <&cpg CPG_MOD 809>;
 773                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 774                         resets = <&cpg 809>;
 775                         status = "disabled";
 776                 };
 777
 778                 vin3: video@e6ef3000 {
 779                         compatible = "renesas,vin-r8a7792",
 780                                      "renesas,rcar-gen2-vin";
 781                         reg = <0 0xe6ef3000 0 0x1000>;
 782                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&cpg CPG_MOD 808>;
 784                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 785                         resets = <&cpg 808>;
 786                         status = "disabled";
 787                 };
 788
 789                 vin4: video@e6ef4000 {
 790                         compatible = "renesas,vin-r8a7792",
 791                                      "renesas,rcar-gen2-vin";
 792                         reg = <0 0xe6ef4000 0 0x1000>;
 793                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 794                         clocks = <&cpg CPG_MOD 805>;
 795                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 796                         resets = <&cpg 805>;
 797                         status = "disabled";
 798                 };
 799
 800                 vin5: video@e6ef5000 {
 801                         compatible = "renesas,vin-r8a7792",
 802                                      "renesas,rcar-gen2-vin";
 803                         reg = <0 0xe6ef5000 0 0x1000>;
 804                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&cpg CPG_MOD 804>;
 806                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 807                         resets = <&cpg 804>;
 808                         status = "disabled";
 809                 };
 810
 811                 vsp@fe928000 {
 812                         compatible = "renesas,vsp1";
 813                         reg = <0 0xfe928000 0 0x8000>;
 814                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 815                         clocks = <&cpg CPG_MOD 131>;
 816                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 817                         resets = <&cpg 131>;
 818                 };
 819
 820                 vsp@fe930000 {
 821                         compatible = "renesas,vsp1";
 822                         reg = <0 0xfe930000 0 0x8000>;
 823                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&cpg CPG_MOD 128>;
 825                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 826                         resets = <&cpg 128>;
 827                 };
 828
 829                 vsp@fe938000 {
 830                         compatible = "renesas,vsp1";
 831                         reg = <0 0xfe938000 0 0x8000>;
 832                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 833                         clocks = <&cpg CPG_MOD 127>;
 834                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 835                         resets = <&cpg 127>;
 836                 };
 837
 838                 cpg: clock-controller@e6150000 {
 839                         compatible = "renesas,r8a7792-cpg-mssr";
 840                         reg = <0 0xe6150000 0 0x1000>;
 841                         clocks = <&extal_clk>;
 842                         clock-names = "extal";
 843                         #clock-cells = <2>;
 844                         #power-domain-cells = <0>;
 845                         #reset-cells = <1>;
 846                 };
 847         };
 848
 849         timer {
 850                 compatible = "arm,armv7-timer";
 851                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 852                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 853                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 854                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 855         };
 856 };