arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7791-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7791";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &i2c4;
  30                 i2c5 = &i2c5;
  31                 i2c6 = &i2c6;
  32                 i2c7 = &i2c7;
  33                 i2c8 = &i2c8;
  34                 spi0 = &qspi;
  35                 spi1 = &msiof0;
  36                 spi2 = &msiof1;
  37                 spi3 = &msiof2;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 enable-method = "renesas,apmu";
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0>;
  52                         clock-frequency = <1500000000>;
  53                         voltage-tolerance = <1>; /* 1% */
  54                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  55                         clock-latency = <300000>; /* 300 us */
  56                         power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
  57                         next-level-cache = <&L2_CA15>;
  58
  59                         /* kHz - uV - OPPs unknown yet */
  60                         operating-points = <1500000 1000000>,
  61                                            <1312500 1000000>,
  62                                            <1125000 1000000>,
  63                                            < 937500 1000000>,
  64                                            < 750000 1000000>,
  65                                            < 375000 1000000>;
  66                 };
  67
  68                 cpu1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a15";
  71                         reg = <1>;
  72                         clock-frequency = <1500000000>;
  73                         power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
  74                         next-level-cache = <&L2_CA15>;
  75                 };
  76
  77                 L2_CA15: cache-controller@0 {
  78                         compatible = "cache";
  79                         reg = <0>;
  80                         power-domains = <&sysc R8A7791_PD_CA15_SCU>;
  81                         cache-unified;
  82                         cache-level = <2>;
  83                 };
  84         };
  85
  86         thermal-zones {
  87                 cpu_thermal: cpu-thermal {
  88                         polling-delay-passive   = <0>;
  89                         polling-delay           = <0>;
  90
  91                         thermal-sensors = <&thermal>;
  92
  93                         trips {
  94                                 cpu-crit {
  95                                         temperature     = <115000>;
  96                                         hysteresis      = <0>;
  97                                         type            = "critical";
  98                                 };
  99                         };
 100                         cooling-maps {
 101                         };
 102                 };
 103         };
 104
 105         apmu@e6152000 {
 106                 compatible = "renesas,r8a7791-apmu", "renesas,apmu";
 107                 reg = <0 0xe6152000 0 0x188>;
 108                 cpus = <&cpu0 &cpu1>;
 109         };
 110
 111         gic: interrupt-controller@f1001000 {
 112                 compatible = "arm,gic-400";
 113                 #interrupt-cells = <3>;
 114                 #address-cells = <0>;
 115                 interrupt-controller;
 116                 reg = <0 0xf1001000 0 0x1000>,
 117                         <0 0xf1002000 0 0x2000>,
 118                         <0 0xf1004000 0 0x2000>,
 119                         <0 0xf1006000 0 0x2000>;
 120                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 121         };
 122
 123         gpio0: gpio@e6050000 {
 124                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 125                 reg = <0 0xe6050000 0 0x50>;
 126                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 127                 #gpio-cells = <2>;
 128                 gpio-controller;
 129                 gpio-ranges = <&pfc 0 0 32>;
 130                 #interrupt-cells = <2>;
 131                 interrupt-controller;
 132                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
 133                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 134         };
 135
 136         gpio1: gpio@e6051000 {
 137                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 138                 reg = <0 0xe6051000 0 0x50>;
 139                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 140                 #gpio-cells = <2>;
 141                 gpio-controller;
 142                 gpio-ranges = <&pfc 0 32 26>;
 143                 #interrupt-cells = <2>;
 144                 interrupt-controller;
 145                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 146                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 147         };
 148
 149         gpio2: gpio@e6052000 {
 150                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 151                 reg = <0 0xe6052000 0 0x50>;
 152                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 153                 #gpio-cells = <2>;
 154                 gpio-controller;
 155                 gpio-ranges = <&pfc 0 64 32>;
 156                 #interrupt-cells = <2>;
 157                 interrupt-controller;
 158                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 159                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 160         };
 161
 162         gpio3: gpio@e6053000 {
 163                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 164                 reg = <0 0xe6053000 0 0x50>;
 165                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 166                 #gpio-cells = <2>;
 167                 gpio-controller;
 168                 gpio-ranges = <&pfc 0 96 32>;
 169                 #interrupt-cells = <2>;
 170                 interrupt-controller;
 171                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 172                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 173         };
 174
 175         gpio4: gpio@e6054000 {
 176                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 177                 reg = <0 0xe6054000 0 0x50>;
 178                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 179                 #gpio-cells = <2>;
 180                 gpio-controller;
 181                 gpio-ranges = <&pfc 0 128 32>;
 182                 #interrupt-cells = <2>;
 183                 interrupt-controller;
 184                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 185                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 186         };
 187
 188         gpio5: gpio@e6055000 {
 189                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 190                 reg = <0 0xe6055000 0 0x50>;
 191                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 192                 #gpio-cells = <2>;
 193                 gpio-controller;
 194                 gpio-ranges = <&pfc 0 160 32>;
 195                 #interrupt-cells = <2>;
 196                 interrupt-controller;
 197                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 198                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 199         };
 200
 201         gpio6: gpio@e6055400 {
 202                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 203                 reg = <0 0xe6055400 0 0x50>;
 204                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 205                 #gpio-cells = <2>;
 206                 gpio-controller;
 207                 gpio-ranges = <&pfc 0 192 32>;
 208                 #interrupt-cells = <2>;
 209                 interrupt-controller;
 210                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 211                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 212         };
 213
 214         gpio7: gpio@e6055800 {
 215                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 216                 reg = <0 0xe6055800 0 0x50>;
 217                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 218                 #gpio-cells = <2>;
 219                 gpio-controller;
 220                 gpio-ranges = <&pfc 0 224 26>;
 221                 #interrupt-cells = <2>;
 222                 interrupt-controller;
 223                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 224                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 225         };
 226
 227         thermal: thermal@e61f0000 {
 228                 compatible =    "renesas,thermal-r8a7791",
 229                                 "renesas,rcar-gen2-thermal",
 230                                 "renesas,rcar-thermal";
 231                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 232                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 234                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 235                 #thermal-sensor-cells = <0>;
 236         };
 237
 238         timer {
 239                 compatible = "arm,armv7-timer";
 240                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 241                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 242                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 243                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 244         };
 245
 246         cmt0: timer@ffca0000 {
 247                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 248                 reg = <0 0xffca0000 0 0x1004>;
 249                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 252                 clock-names = "fck";
 253                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 254
 255                 renesas,channels-mask = <0x60>;
 256
 257                 status = "disabled";
 258         };
 259
 260         cmt1: timer@e6130000 {
 261                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 262                 reg = <0 0xe6130000 0 0x1004>;
 263                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 272                 clock-names = "fck";
 273                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 274
 275                 renesas,channels-mask = <0xff>;
 276
 277                 status = "disabled";
 278         };
 279
 280         irqc0: interrupt-controller@e61c0000 {
 281                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 282                 #interrupt-cells = <2>;
 283                 interrupt-controller;
 284                 reg = <0 0xe61c0000 0 0x200>;
 285                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 296                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 297         };
 298
 299         dmac0: dma-controller@e6700000 {
 300                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 301                 reg = <0 0xe6700000 0 0x20000>;
 302                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 303                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 304                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 311                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 312                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 313                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 314                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 315                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 316                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 317                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 318                 interrupt-names = "error",
 319                                 "ch0", "ch1", "ch2", "ch3",
 320                                 "ch4", "ch5", "ch6", "ch7",
 321                                 "ch8", "ch9", "ch10", "ch11",
 322                                 "ch12", "ch13", "ch14";
 323                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 324                 clock-names = "fck";
 325                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 326                 #dma-cells = <1>;
 327                 dma-channels = <15>;
 328         };
 329
 330         dmac1: dma-controller@e6720000 {
 331                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 332                 reg = <0 0xe6720000 0 0x20000>;
 333                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 343                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 344                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 345                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 346                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 347                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 348                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 349                 interrupt-names = "error",
 350                                 "ch0", "ch1", "ch2", "ch3",
 351                                 "ch4", "ch5", "ch6", "ch7",
 352                                 "ch8", "ch9", "ch10", "ch11",
 353                                 "ch12", "ch13", "ch14";
 354                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 355                 clock-names = "fck";
 356                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 357                 #dma-cells = <1>;
 358                 dma-channels = <15>;
 359         };
 360
 361         audma0: dma-controller@ec700000 {
 362                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 363                 reg = <0 0xec700000 0 0x10000>;
 364                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 365                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 366                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 367                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 368                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 369                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 370                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 371                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 372                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 373                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 374                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 375                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 376                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 377                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 378                 interrupt-names = "error",
 379                                 "ch0", "ch1", "ch2", "ch3",
 380                                 "ch4", "ch5", "ch6", "ch7",
 381                                 "ch8", "ch9", "ch10", "ch11",
 382                                 "ch12";
 383                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 384                 clock-names = "fck";
 385                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 386                 #dma-cells = <1>;
 387                 dma-channels = <13>;
 388         };
 389
 390         audma1: dma-controller@ec720000 {
 391                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 392                 reg = <0 0xec720000 0 0x10000>;
 393                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 394                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 395                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 396                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 397                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 398                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 399                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 400                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 401                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 402                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 403                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 404                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 405                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 406                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 407                 interrupt-names = "error",
 408                                 "ch0", "ch1", "ch2", "ch3",
 409                                 "ch4", "ch5", "ch6", "ch7",
 410                                 "ch8", "ch9", "ch10", "ch11",
 411                                 "ch12";
 412                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 413                 clock-names = "fck";
 414                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 415                 #dma-cells = <1>;
 416                 dma-channels = <13>;
 417         };
 418
 419         usb_dmac0: dma-controller@e65a0000 {
 420                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 421                 reg = <0 0xe65a0000 0 0x100>;
 422                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 423                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 424                 interrupt-names = "ch0", "ch1";
 425                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 426                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 427                 #dma-cells = <1>;
 428                 dma-channels = <2>;
 429         };
 430
 431         usb_dmac1: dma-controller@e65b0000 {
 432                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 433                 reg = <0 0xe65b0000 0 0x100>;
 434                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 435                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 436                 interrupt-names = "ch0", "ch1";
 437                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 438                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 439                 #dma-cells = <1>;
 440                 dma-channels = <2>;
 441         };
 442
 443         /* The memory map in the User's Manual maps the cores to bus numbers */
 444         i2c0: i2c@e6508000 {
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 448                 reg = <0 0xe6508000 0 0x40>;
 449                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 451                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 452                 i2c-scl-internal-delay-ns = <6>;
 453                 status = "disabled";
 454         };
 455
 456         i2c1: i2c@e6518000 {
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 460                 reg = <0 0xe6518000 0 0x40>;
 461                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 463                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 464                 i2c-scl-internal-delay-ns = <6>;
 465                 status = "disabled";
 466         };
 467
 468         i2c2: i2c@e6530000 {
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 472                 reg = <0 0xe6530000 0 0x40>;
 473                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 474                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 475                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 476                 i2c-scl-internal-delay-ns = <6>;
 477                 status = "disabled";
 478         };
 479
 480         i2c3: i2c@e6540000 {
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 484                 reg = <0 0xe6540000 0 0x40>;
 485                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 487                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 488                 i2c-scl-internal-delay-ns = <6>;
 489                 status = "disabled";
 490         };
 491
 492         i2c4: i2c@e6520000 {
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 496                 reg = <0 0xe6520000 0 0x40>;
 497                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 499                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 500                 i2c-scl-internal-delay-ns = <6>;
 501                 status = "disabled";
 502         };
 503
 504         i2c5: i2c@e6528000 {
 505                 /* doesn't need pinmux */
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
 509                 reg = <0 0xe6528000 0 0x40>;
 510                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 511                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 512                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 513                 i2c-scl-internal-delay-ns = <110>;
 514                 status = "disabled";
 515         };
 516
 517         i2c6: i2c@e60b0000 {
 518                 /* doesn't need pinmux */
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 522                              "renesas,rmobile-iic";
 523                 reg = <0 0xe60b0000 0 0x425>;
 524                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 526                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 527                        <&dmac1 0x77>, <&dmac1 0x78>;
 528                 dma-names = "tx", "rx", "tx", "rx";
 529                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 530                 status = "disabled";
 531         };
 532
 533         i2c7: i2c@e6500000 {
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 537                              "renesas,rmobile-iic";
 538                 reg = <0 0xe6500000 0 0x425>;
 539                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 541                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 542                        <&dmac1 0x61>, <&dmac1 0x62>;
 543                 dma-names = "tx", "rx", "tx", "rx";
 544                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 545                 status = "disabled";
 546         };
 547
 548         i2c8: i2c@e6510000 {
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
 552                              "renesas,rmobile-iic";
 553                 reg = <0 0xe6510000 0 0x425>;
 554                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 555                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 556                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 557                        <&dmac1 0x65>, <&dmac1 0x66>;
 558                 dma-names = "tx", "rx", "tx", "rx";
 559                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 560                 status = "disabled";
 561         };
 562
 563         pfc: pfc@e6060000 {
 564                 compatible = "renesas,pfc-r8a7791";
 565                 reg = <0 0xe6060000 0 0x250>;
 566         };
 567
 568         mmcif0: mmc@ee200000 {
 569                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 570                 reg = <0 0xee200000 0 0x80>;
 571                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 573                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 574                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 575                 dma-names = "tx", "rx", "tx", "rx";
 576                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 577                 reg-io-width = <4>;
 578                 status = "disabled";
 579                 max-frequency = <97500000>;
 580         };
 581
 582         sdhi0: sd@ee100000 {
 583                 compatible = "renesas,sdhi-r8a7791";
 584                 reg = <0 0xee100000 0 0x328>;
 585                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 586                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 587                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 588                        <&dmac1 0xcd>, <&dmac1 0xce>;
 589                 dma-names = "tx", "rx", "tx", "rx";
 590                 max-frequency = <195000000>;
 591                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 592                 status = "disabled";
 593         };
 594
 595         sdhi1: sd@ee140000 {
 596                 compatible = "renesas,sdhi-r8a7791";
 597                 reg = <0 0xee140000 0 0x100>;
 598                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 599                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 600                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 601                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 602                 dma-names = "tx", "rx", "tx", "rx";
 603                 max-frequency = <97500000>;
 604                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 605                 status = "disabled";
 606         };
 607
 608         sdhi2: sd@ee160000 {
 609                 compatible = "renesas,sdhi-r8a7791";
 610                 reg = <0 0xee160000 0 0x100>;
 611                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 613                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 614                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 615                 dma-names = "tx", "rx", "tx", "rx";
 616                 max-frequency = <97500000>;
 617                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 618                 status = "disabled";
 619         };
 620
 621         scifa0: serial@e6c40000 {
 622                 compatible = "renesas,scifa-r8a7791",
 623                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 624                 reg = <0 0xe6c40000 0 64>;
 625                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 626                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 627                 clock-names = "fck";
 628                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 629                        <&dmac1 0x21>, <&dmac1 0x22>;
 630                 dma-names = "tx", "rx", "tx", "rx";
 631                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 632                 status = "disabled";
 633         };
 634
 635         scifa1: serial@e6c50000 {
 636                 compatible = "renesas,scifa-r8a7791",
 637                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 638                 reg = <0 0xe6c50000 0 64>;
 639                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 641                 clock-names = "fck";
 642                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 643                        <&dmac1 0x25>, <&dmac1 0x26>;
 644                 dma-names = "tx", "rx", "tx", "rx";
 645                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 646                 status = "disabled";
 647         };
 648
 649         scifa2: serial@e6c60000 {
 650                 compatible = "renesas,scifa-r8a7791",
 651                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 652                 reg = <0 0xe6c60000 0 64>;
 653                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 655                 clock-names = "fck";
 656                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 657                        <&dmac1 0x27>, <&dmac1 0x28>;
 658                 dma-names = "tx", "rx", "tx", "rx";
 659                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 660                 status = "disabled";
 661         };
 662
 663         scifa3: serial@e6c70000 {
 664                 compatible = "renesas,scifa-r8a7791",
 665                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 666                 reg = <0 0xe6c70000 0 64>;
 667                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 669                 clock-names = "fck";
 670                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 671                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 672                 dma-names = "tx", "rx", "tx", "rx";
 673                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 674                 status = "disabled";
 675         };
 676
 677         scifa4: serial@e6c78000 {
 678                 compatible = "renesas,scifa-r8a7791",
 679                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 680                 reg = <0 0xe6c78000 0 64>;
 681                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 682                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 683                 clock-names = "fck";
 684                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 685                        <&dmac1 0x1f>, <&dmac1 0x20>;
 686                 dma-names = "tx", "rx", "tx", "rx";
 687                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 688                 status = "disabled";
 689         };
 690
 691         scifa5: serial@e6c80000 {
 692                 compatible = "renesas,scifa-r8a7791",
 693                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 694                 reg = <0 0xe6c80000 0 64>;
 695                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 697                 clock-names = "fck";
 698                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 699                        <&dmac1 0x23>, <&dmac1 0x24>;
 700                 dma-names = "tx", "rx", "tx", "rx";
 701                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 702                 status = "disabled";
 703         };
 704
 705         scifb0: serial@e6c20000 {
 706                 compatible = "renesas,scifb-r8a7791",
 707                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 708                 reg = <0 0xe6c20000 0 0x100>;
 709                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 710                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 711                 clock-names = "fck";
 712                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 713                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 714                 dma-names = "tx", "rx", "tx", "rx";
 715                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 716                 status = "disabled";
 717         };
 718
 719         scifb1: serial@e6c30000 {
 720                 compatible = "renesas,scifb-r8a7791",
 721                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 722                 reg = <0 0xe6c30000 0 0x100>;
 723                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 725                 clock-names = "fck";
 726                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 727                        <&dmac1 0x19>, <&dmac1 0x1a>;
 728                 dma-names = "tx", "rx", "tx", "rx";
 729                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 730                 status = "disabled";
 731         };
 732
 733         scifb2: serial@e6ce0000 {
 734                 compatible = "renesas,scifb-r8a7791",
 735                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 736                 reg = <0 0xe6ce0000 0 0x100>;
 737                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 738                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 739                 clock-names = "fck";
 740                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 741                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 742                 dma-names = "tx", "rx", "tx", "rx";
 743                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 744                 status = "disabled";
 745         };
 746
 747         scif0: serial@e6e60000 {
 748                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 749                              "renesas,scif";
 750                 reg = <0 0xe6e60000 0 64>;
 751                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 752                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
 753                          <&scif_clk>;
 754                 clock-names = "fck", "brg_int", "scif_clk";
 755                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 756                        <&dmac1 0x29>, <&dmac1 0x2a>;
 757                 dma-names = "tx", "rx", "tx", "rx";
 758                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 759                 status = "disabled";
 760         };
 761
 762         scif1: serial@e6e68000 {
 763                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 764                              "renesas,scif";
 765                 reg = <0 0xe6e68000 0 64>;
 766                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 767                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
 768                          <&scif_clk>;
 769                 clock-names = "fck", "brg_int", "scif_clk";
 770                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 771                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 772                 dma-names = "tx", "rx", "tx", "rx";
 773                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 774                 status = "disabled";
 775         };
 776
 777         scif2: serial@e6e58000 {
 778                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 779                              "renesas,scif";
 780                 reg = <0 0xe6e58000 0 64>;
 781                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 782                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
 783                          <&scif_clk>;
 784                 clock-names = "fck", "brg_int", "scif_clk";
 785                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 786                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 787                 dma-names = "tx", "rx", "tx", "rx";
 788                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 789                 status = "disabled";
 790         };
 791
 792         scif3: serial@e6ea8000 {
 793                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 794                              "renesas,scif";
 795                 reg = <0 0xe6ea8000 0 64>;
 796                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 797                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
 798                          <&scif_clk>;
 799                 clock-names = "fck", "brg_int", "scif_clk";
 800                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 801                        <&dmac1 0x2f>, <&dmac1 0x30>;
 802                 dma-names = "tx", "rx", "tx", "rx";
 803                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 804                 status = "disabled";
 805         };
 806
 807         scif4: serial@e6ee0000 {
 808                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 809                              "renesas,scif";
 810                 reg = <0 0xe6ee0000 0 64>;
 811                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 812                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
 813                          <&scif_clk>;
 814                 clock-names = "fck", "brg_int", "scif_clk";
 815                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 816                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 817                 dma-names = "tx", "rx", "tx", "rx";
 818                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 819                 status = "disabled";
 820         };
 821
 822         scif5: serial@e6ee8000 {
 823                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 824                              "renesas,scif";
 825                 reg = <0 0xe6ee8000 0 64>;
 826                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 827                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
 828                          <&scif_clk>;
 829                 clock-names = "fck", "brg_int", "scif_clk";
 830                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 831                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 832                 dma-names = "tx", "rx", "tx", "rx";
 833                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 834                 status = "disabled";
 835         };
 836
 837         hscif0: serial@e62c0000 {
 838                 compatible = "renesas,hscif-r8a7791",
 839                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 840                 reg = <0 0xe62c0000 0 96>;
 841                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 842                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
 843                          <&scif_clk>;
 844                 clock-names = "fck", "brg_int", "scif_clk";
 845                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 846                        <&dmac1 0x39>, <&dmac1 0x3a>;
 847                 dma-names = "tx", "rx", "tx", "rx";
 848                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 849                 status = "disabled";
 850         };
 851
 852         hscif1: serial@e62c8000 {
 853                 compatible = "renesas,hscif-r8a7791",
 854                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 855                 reg = <0 0xe62c8000 0 96>;
 856                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 857                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
 858                          <&scif_clk>;
 859                 clock-names = "fck", "brg_int", "scif_clk";
 860                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 861                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 862                 dma-names = "tx", "rx", "tx", "rx";
 863                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 864                 status = "disabled";
 865         };
 866
 867         hscif2: serial@e62d0000 {
 868                 compatible = "renesas,hscif-r8a7791",
 869                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 870                 reg = <0 0xe62d0000 0 96>;
 871                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
 873                          <&scif_clk>;
 874                 clock-names = "fck", "brg_int", "scif_clk";
 875                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 876                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 877                 dma-names = "tx", "rx", "tx", "rx";
 878                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 879                 status = "disabled";
 880         };
 881
 882         ether: ethernet@ee700000 {
 883                 compatible = "renesas,ether-r8a7791";
 884                 reg = <0 0xee700000 0 0x400>;
 885                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 887                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 888                 phy-mode = "rmii";
 889                 #address-cells = <1>;
 890                 #size-cells = <0>;
 891                 status = "disabled";
 892         };
 893
 894         avb: ethernet@e6800000 {
 895                 compatible = "renesas,etheravb-r8a7791",
 896                              "renesas,etheravb-rcar-gen2";
 897                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 898                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 899                 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
 900                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 901                 #address-cells = <1>;
 902                 #size-cells = <0>;
 903                 status = "disabled";
 904         };
 905
 906         sata0: sata@ee300000 {
 907                 compatible = "renesas,sata-r8a7791";
 908                 reg = <0 0xee300000 0 0x2000>;
 909                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 910                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 911                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 912                 status = "disabled";
 913         };
 914
 915         sata1: sata@ee500000 {
 916                 compatible = "renesas,sata-r8a7791";
 917                 reg = <0 0xee500000 0 0x2000>;
 918                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 919                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 920                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 921                 status = "disabled";
 922         };
 923
 924         hsusb: usb@e6590000 {
 925                 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
 926                 reg = <0 0xe6590000 0 0x100>;
 927                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 928                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 929                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 930                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 931                 dma-names = "ch0", "ch1", "ch2", "ch3";
 932                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 933                 renesas,buswait = <4>;
 934                 phys = <&usb0 1>;
 935                 phy-names = "usb";
 936                 status = "disabled";
 937         };
 938
 939         usbphy: usb-phy@e6590100 {
 940                 compatible = "renesas,usb-phy-r8a7791",
 941                              "renesas,rcar-gen2-usb-phy";
 942                 reg = <0 0xe6590100 0 0x100>;
 943                 #address-cells = <1>;
 944                 #size-cells = <0>;
 945                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 946                 clock-names = "usbhs";
 947                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 948                 status = "disabled";
 949
 950                 usb0: usb-channel@0 {
 951                         reg = <0>;
 952                         #phy-cells = <1>;
 953                 };
 954                 usb2: usb-channel@2 {
 955                         reg = <2>;
 956                         #phy-cells = <1>;
 957                 };
 958         };
 959
 960         vin0: video@e6ef0000 {
 961                 compatible = "renesas,vin-r8a7791";
 962                 reg = <0 0xe6ef0000 0 0x1000>;
 963                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 964                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 965                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 966                 status = "disabled";
 967         };
 968
 969         vin1: video@e6ef1000 {
 970                 compatible = "renesas,vin-r8a7791";
 971                 reg = <0 0xe6ef1000 0 0x1000>;
 972                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 973                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 974                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 975                 status = "disabled";
 976         };
 977
 978         vin2: video@e6ef2000 {
 979                 compatible = "renesas,vin-r8a7791";
 980                 reg = <0 0xe6ef2000 0 0x1000>;
 981                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 982                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 983                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 984                 status = "disabled";
 985         };
 986
 987         vsp1@fe928000 {
 988                 compatible = "renesas,vsp1";
 989                 reg = <0 0xfe928000 0 0x8000>;
 990                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 991                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 992                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 993         };
 994
 995         vsp1@fe930000 {
 996                 compatible = "renesas,vsp1";
 997                 reg = <0 0xfe930000 0 0x8000>;
 998                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 999                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
1000                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1001         };
1002
1003         vsp1@fe938000 {
1004                 compatible = "renesas,vsp1";
1005                 reg = <0 0xfe938000 0 0x8000>;
1006                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
1008                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1009         };
1010
1011         du: display@feb00000 {
1012                 compatible = "renesas,du-r8a7791";
1013                 reg = <0 0xfeb00000 0 0x40000>,
1014                       <0 0xfeb90000 0 0x1c>;
1015                 reg-names = "du", "lvds.0";
1016                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1017                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
1019                          <&mstp7_clks R8A7791_CLK_DU1>,
1020                          <&mstp7_clks R8A7791_CLK_LVDS0>;
1021                 clock-names = "du.0", "du.1", "lvds.0";
1022                 status = "disabled";
1023
1024                 ports {
1025                         #address-cells = <1>;
1026                         #size-cells = <0>;
1027
1028                         port@0 {
1029                                 reg = <0>;
1030                                 du_out_rgb: endpoint {
1031                                 };
1032                         };
1033                         port@1 {
1034                                 reg = <1>;
1035                                 du_out_lvds0: endpoint {
1036                                 };
1037                         };
1038                 };
1039         };
1040
1041         can0: can@e6e80000 {
1042                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1043                 reg = <0 0xe6e80000 0 0x1000>;
1044                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1045                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1046                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1047                 clock-names = "clkp1", "clkp2", "can_clk";
1048                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1049                 status = "disabled";
1050         };
1051
1052         can1: can@e6e88000 {
1053                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1054                 reg = <0 0xe6e88000 0 0x1000>;
1055                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1056                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1057                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1058                 clock-names = "clkp1", "clkp2", "can_clk";
1059                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1060                 status = "disabled";
1061         };
1062
1063         jpu: jpeg-codec@fe980000 {
1064                 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1065                 reg = <0 0xfe980000 0 0x10300>;
1066                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1068                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1069         };
1070
1071         clocks {
1072                 #address-cells = <2>;
1073                 #size-cells = <2>;
1074                 ranges;
1075
1076                 /* External root clock */
1077                 extal_clk: extal {
1078                         compatible = "fixed-clock";
1079                         #clock-cells = <0>;
1080                         /* This value must be overriden by the board. */
1081                         clock-frequency = <0>;
1082                 };
1083
1084                 /*
1085                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1086                  * default. Boards that provide audio clocks should override them.
1087                  */
1088                 audio_clk_a: audio_clk_a {
1089                         compatible = "fixed-clock";
1090                         #clock-cells = <0>;
1091                         clock-frequency = <0>;
1092                 };
1093                 audio_clk_b: audio_clk_b {
1094                         compatible = "fixed-clock";
1095                         #clock-cells = <0>;
1096                         clock-frequency = <0>;
1097                 };
1098                 audio_clk_c: audio_clk_c {
1099                         compatible = "fixed-clock";
1100                         #clock-cells = <0>;
1101                         clock-frequency = <0>;
1102                 };
1103
1104                 /* External PCIe clock - can be overridden by the board */
1105                 pcie_bus_clk: pcie_bus {
1106                         compatible = "fixed-clock";
1107                         #clock-cells = <0>;
1108                         clock-frequency = <0>;
1109                 };
1110
1111                 /* External SCIF clock */
1112                 scif_clk: scif {
1113                         compatible = "fixed-clock";
1114                         #clock-cells = <0>;
1115                         /* This value must be overridden by the board. */
1116                         clock-frequency = <0>;
1117                 };
1118
1119                 /* External USB clock - can be overridden by the board */
1120                 usb_extal_clk: usb_extal {
1121                         compatible = "fixed-clock";
1122                         #clock-cells = <0>;
1123                         clock-frequency = <48000000>;
1124                 };
1125
1126                 /* External CAN clock */
1127                 can_clk: can_clk {
1128                         compatible = "fixed-clock";
1129                         #clock-cells = <0>;
1130                         /* This value must be overridden by the board. */
1131                         clock-frequency = <0>;
1132                 };
1133
1134                 /* Special CPG clocks */
1135                 cpg_clocks: cpg_clocks@e6150000 {
1136                         compatible = "renesas,r8a7791-cpg-clocks",
1137                                      "renesas,rcar-gen2-cpg-clocks";
1138                         reg = <0 0xe6150000 0 0x1000>;
1139                         clocks = <&extal_clk &usb_extal_clk>;
1140                         #clock-cells = <1>;
1141                         clock-output-names = "main", "pll0", "pll1", "pll3",
1142                                              "lb", "qspi", "sdh", "sd0", "z",
1143                                              "rcan", "adsp";
1144                         #power-domain-cells = <0>;
1145                 };
1146
1147                 /* Variable factor clocks */
1148                 sd2_clk: sd2@e6150078 {
1149                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1150                         reg = <0 0xe6150078 0 4>;
1151                         clocks = <&pll1_div2_clk>;
1152                         #clock-cells = <0>;
1153                 };
1154                 sd3_clk: sd3@e615026c {
1155                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1156                         reg = <0 0xe615026c 0 4>;
1157                         clocks = <&pll1_div2_clk>;
1158                         #clock-cells = <0>;
1159                 };
1160                 mmc0_clk: mmc0@e6150240 {
1161                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1162                         reg = <0 0xe6150240 0 4>;
1163                         clocks = <&pll1_div2_clk>;
1164                         #clock-cells = <0>;
1165                 };
1166                 ssp_clk: ssp@e6150248 {
1167                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1168                         reg = <0 0xe6150248 0 4>;
1169                         clocks = <&pll1_div2_clk>;
1170                         #clock-cells = <0>;
1171                 };
1172                 ssprs_clk: ssprs@e615024c {
1173                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1174                         reg = <0 0xe615024c 0 4>;
1175                         clocks = <&pll1_div2_clk>;
1176                         #clock-cells = <0>;
1177                 };
1178
1179                 /* Fixed factor clocks */
1180                 pll1_div2_clk: pll1_div2 {
1181                         compatible = "fixed-factor-clock";
1182                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1183                         #clock-cells = <0>;
1184                         clock-div = <2>;
1185                         clock-mult = <1>;
1186                 };
1187                 zg_clk: zg {
1188                         compatible = "fixed-factor-clock";
1189                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1190                         #clock-cells = <0>;
1191                         clock-div = <3>;
1192                         clock-mult = <1>;
1193                 };
1194                 zx_clk: zx {
1195                         compatible = "fixed-factor-clock";
1196                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1197                         #clock-cells = <0>;
1198                         clock-div = <3>;
1199                         clock-mult = <1>;
1200                 };
1201                 zs_clk: zs {
1202                         compatible = "fixed-factor-clock";
1203                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1204                         #clock-cells = <0>;
1205                         clock-div = <6>;
1206                         clock-mult = <1>;
1207                 };
1208                 hp_clk: hp {
1209                         compatible = "fixed-factor-clock";
1210                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1211                         #clock-cells = <0>;
1212                         clock-div = <12>;
1213                         clock-mult = <1>;
1214                 };
1215                 i_clk: i {
1216                         compatible = "fixed-factor-clock";
1217                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1218                         #clock-cells = <0>;
1219                         clock-div = <2>;
1220                         clock-mult = <1>;
1221                 };
1222                 b_clk: b {
1223                         compatible = "fixed-factor-clock";
1224                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1225                         #clock-cells = <0>;
1226                         clock-div = <12>;
1227                         clock-mult = <1>;
1228                 };
1229                 p_clk: p {
1230                         compatible = "fixed-factor-clock";
1231                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1232                         #clock-cells = <0>;
1233                         clock-div = <24>;
1234                         clock-mult = <1>;
1235                 };
1236                 cl_clk: cl {
1237                         compatible = "fixed-factor-clock";
1238                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1239                         #clock-cells = <0>;
1240                         clock-div = <48>;
1241                         clock-mult = <1>;
1242                 };
1243                 m2_clk: m2 {
1244                         compatible = "fixed-factor-clock";
1245                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1246                         #clock-cells = <0>;
1247                         clock-div = <8>;
1248                         clock-mult = <1>;
1249                 };
1250                 rclk_clk: rclk {
1251                         compatible = "fixed-factor-clock";
1252                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1253                         #clock-cells = <0>;
1254                         clock-div = <(48 * 1024)>;
1255                         clock-mult = <1>;
1256                 };
1257                 oscclk_clk: oscclk {
1258                         compatible = "fixed-factor-clock";
1259                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1260                         #clock-cells = <0>;
1261                         clock-div = <(12 * 1024)>;
1262                         clock-mult = <1>;
1263                 };
1264                 zb3_clk: zb3 {
1265                         compatible = "fixed-factor-clock";
1266                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1267                         #clock-cells = <0>;
1268                         clock-div = <4>;
1269                         clock-mult = <1>;
1270                 };
1271                 zb3d2_clk: zb3d2 {
1272                         compatible = "fixed-factor-clock";
1273                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1274                         #clock-cells = <0>;
1275                         clock-div = <8>;
1276                         clock-mult = <1>;
1277                 };
1278                 ddr_clk: ddr {
1279                         compatible = "fixed-factor-clock";
1280                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1281                         #clock-cells = <0>;
1282                         clock-div = <8>;
1283                         clock-mult = <1>;
1284                 };
1285                 mp_clk: mp {
1286                         compatible = "fixed-factor-clock";
1287                         clocks = <&pll1_div2_clk>;
1288                         #clock-cells = <0>;
1289                         clock-div = <15>;
1290                         clock-mult = <1>;
1291                 };
1292                 cp_clk: cp {
1293                         compatible = "fixed-factor-clock";
1294                         clocks = <&extal_clk>;
1295                         #clock-cells = <0>;
1296                         clock-div = <2>;
1297                         clock-mult = <1>;
1298                 };
1299
1300                 /* Gate clocks */
1301                 mstp0_clks: mstp0_clks@e6150130 {
1302                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1303                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1304                         clocks = <&mp_clk>;
1305                         #clock-cells = <1>;
1306                         clock-indices = <R8A7791_CLK_MSIOF0>;
1307                         clock-output-names = "msiof0";
1308                 };
1309                 mstp1_clks: mstp1_clks@e6150134 {
1310                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1311                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1312                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1313                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1314                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1315                                  <&zs_clk>;
1316                         #clock-cells = <1>;
1317                         clock-indices = <
1318                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1319                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1320                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1321                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1322                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1323                                 R8A7791_CLK_VSP1_S
1324                         >;
1325                         clock-output-names =
1326                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1327                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1328                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1329                 };
1330                 mstp2_clks: mstp2_clks@e6150138 {
1331                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1332                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1333                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1334                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1335                                  <&zs_clk>, <&zs_clk>;
1336                         #clock-cells = <1>;
1337                         clock-indices = <
1338                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1339                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1340                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1341                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1342                         >;
1343                         clock-output-names =
1344                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1345                                 "scifb1", "msiof1", "scifb2",
1346                                 "sys-dmac1", "sys-dmac0";
1347                 };
1348                 mstp3_clks: mstp3_clks@e615013c {
1349                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1350                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1351                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1352                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1353                                  <&hp_clk>, <&hp_clk>;
1354                         #clock-cells = <1>;
1355                         clock-indices = <
1356                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1357                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1358                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1359                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1360                         >;
1361                         clock-output-names =
1362                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1363                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1364                                 "usbdmac0", "usbdmac1";
1365                 };
1366                 mstp4_clks: mstp4_clks@e6150140 {
1367                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1368                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1369                         clocks = <&cp_clk>;
1370                         #clock-cells = <1>;
1371                         clock-indices = <R8A7791_CLK_IRQC>;
1372                         clock-output-names = "irqc";
1373                 };
1374                 mstp5_clks: mstp5_clks@e6150144 {
1375                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1376                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1377                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1378                                  <&extal_clk>, <&p_clk>;
1379                         #clock-cells = <1>;
1380                         clock-indices = <
1381                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1382                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1383                                 R8A7791_CLK_PWM
1384                         >;
1385                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1386                                              "thermal", "pwm";
1387                 };
1388                 mstp7_clks: mstp7_clks@e615014c {
1389                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1390                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1391                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1392                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1393                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1394                         #clock-cells = <1>;
1395                         clock-indices = <
1396                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1397                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1398                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1399                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1400                                 R8A7791_CLK_LVDS0
1401                         >;
1402                         clock-output-names =
1403                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1404                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1405                 };
1406                 mstp8_clks: mstp8_clks@e6150990 {
1407                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1408                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1409                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1410                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1411                                  <&zs_clk>;
1412                         #clock-cells = <1>;
1413                         clock-indices = <
1414                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1415                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1416                                 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1417                                 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1418                         >;
1419                         clock-output-names =
1420                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1421                                 "etheravb", "ether", "sata1", "sata0";
1422                 };
1423                 mstp9_clks: mstp9_clks@e6150994 {
1424                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1425                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1426                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1427                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1428                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1429                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1430                                  <&hp_clk>, <&hp_clk>;
1431                         #clock-cells = <1>;
1432                         clock-indices = <
1433                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1434                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1435                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1436                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1437                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1438                         >;
1439                         clock-output-names =
1440                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1441                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1442                                 "i2c1", "i2c0";
1443                 };
1444                 mstp10_clks: mstp10_clks@e6150998 {
1445                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1446                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1447                         clocks = <&p_clk>,
1448                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1449                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1450                                 <&p_clk>,
1451                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1452                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1453                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1454                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1455                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1456                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1457                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1458
1459                         #clock-cells = <1>;
1460                         clock-indices = <
1461                                 R8A7791_CLK_SSI_ALL
1462                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1463                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1464                                 R8A7791_CLK_SCU_ALL
1465                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1466                                 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1467                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1468                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1469                         >;
1470                         clock-output-names =
1471                                 "ssi-all",
1472                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1473                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1474                                 "scu-all",
1475                                 "scu-dvc1", "scu-dvc0",
1476                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1477                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1478                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1479                 };
1480                 mstp11_clks: mstp11_clks@e615099c {
1481                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1482                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1483                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1484                         #clock-cells = <1>;
1485                         clock-indices = <
1486                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1487                         >;
1488                         clock-output-names = "scifa3", "scifa4", "scifa5";
1489                 };
1490         };
1491
1492         rst: reset-controller@e6160000 {
1493                 compatible = "renesas,r8a7791-rst";
1494                 reg = <0 0xe6160000 0 0x0100>;
1495         };
1496
1497         prr: chipid@ff000044 {
1498                 compatible = "renesas,prr";
1499                 reg = <0 0xff000044 0 4>;
1500         };
1501
1502         sysc: system-controller@e6180000 {
1503                 compatible = "renesas,r8a7791-sysc";
1504                 reg = <0 0xe6180000 0 0x0200>;
1505                 #power-domain-cells = <1>;
1506         };
1507
1508         qspi: spi@e6b10000 {
1509                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1510                 reg = <0 0xe6b10000 0 0x2c>;
1511                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1512                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1513                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1514                        <&dmac1 0x17>, <&dmac1 0x18>;
1515                 dma-names = "tx", "rx", "tx", "rx";
1516                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1517                 num-cs = <1>;
1518                 #address-cells = <1>;
1519                 #size-cells = <0>;
1520                 status = "disabled";
1521         };
1522
1523         msiof0: spi@e6e20000 {
1524                 compatible = "renesas,msiof-r8a7791",
1525                              "renesas,rcar-gen2-msiof";
1526                 reg = <0 0xe6e20000 0 0x0064>;
1527                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1528                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1529                 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1530                        <&dmac1 0x51>, <&dmac1 0x52>;
1531                 dma-names = "tx", "rx", "tx", "rx";
1532                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1533                 #address-cells = <1>;
1534                 #size-cells = <0>;
1535                 status = "disabled";
1536         };
1537
1538         msiof1: spi@e6e10000 {
1539                 compatible = "renesas,msiof-r8a7791",
1540                              "renesas,rcar-gen2-msiof";
1541                 reg = <0 0xe6e10000 0 0x0064>;
1542                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1543                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1544                 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1545                        <&dmac1 0x55>, <&dmac1 0x56>;
1546                 dma-names = "tx", "rx", "tx", "rx";
1547                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1548                 #address-cells = <1>;
1549                 #size-cells = <0>;
1550                 status = "disabled";
1551         };
1552
1553         msiof2: spi@e6e00000 {
1554                 compatible = "renesas,msiof-r8a7791",
1555                              "renesas,rcar-gen2-msiof";
1556                 reg = <0 0xe6e00000 0 0x0064>;
1557                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1558                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1559                 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1560                        <&dmac1 0x41>, <&dmac1 0x42>;
1561                 dma-names = "tx", "rx", "tx", "rx";
1562                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1563                 #address-cells = <1>;
1564                 #size-cells = <0>;
1565                 status = "disabled";
1566         };
1567
1568         xhci: usb@ee000000 {
1569                 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1570                 reg = <0 0xee000000 0 0xc00>;
1571                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1572                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1573                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1574                 phys = <&usb2 1>;
1575                 phy-names = "usb";
1576                 status = "disabled";
1577         };
1578
1579         pci0: pci@ee090000 {
1580                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1581                 device_type = "pci";
1582                 reg = <0 0xee090000 0 0xc00>,
1583                       <0 0xee080000 0 0x1100>;
1584                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1585                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1586                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1587                 status = "disabled";
1588
1589                 bus-range = <0 0>;
1590                 #address-cells = <3>;
1591                 #size-cells = <2>;
1592                 #interrupt-cells = <1>;
1593                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1594                 interrupt-map-mask = <0xff00 0 0 0x7>;
1595                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1596                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1597                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1598
1599                 usb@0,1 {
1600                         reg = <0x800 0 0 0 0>;
1601                         device_type = "pci";
1602                         phys = <&usb0 0>;
1603                         phy-names = "usb";
1604                 };
1605
1606                 usb@0,2 {
1607                         reg = <0x1000 0 0 0 0>;
1608                         device_type = "pci";
1609                         phys = <&usb0 0>;
1610                         phy-names = "usb";
1611                 };
1612         };
1613
1614         pci1: pci@ee0d0000 {
1615                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1616                 device_type = "pci";
1617                 reg = <0 0xee0d0000 0 0xc00>,
1618                       <0 0xee0c0000 0 0x1100>;
1619                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1620                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1621                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1622                 status = "disabled";
1623
1624                 bus-range = <1 1>;
1625                 #address-cells = <3>;
1626                 #size-cells = <2>;
1627                 #interrupt-cells = <1>;
1628                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1629                 interrupt-map-mask = <0xff00 0 0 0x7>;
1630                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1631                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1632                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1633
1634                 usb@0,1 {
1635                         reg = <0x800 0 0 0 0>;
1636                         device_type = "pci";
1637                         phys = <&usb2 0>;
1638                         phy-names = "usb";
1639                 };
1640
1641                 usb@0,2 {
1642                         reg = <0x1000 0 0 0 0>;
1643                         device_type = "pci";
1644                         phys = <&usb2 0>;
1645                         phy-names = "usb";
1646                 };
1647         };
1648
1649         pciec: pcie@fe000000 {
1650                 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
1651                 reg = <0 0xfe000000 0 0x80000>;
1652                 #address-cells = <3>;
1653                 #size-cells = <2>;
1654                 bus-range = <0x00 0xff>;
1655                 device_type = "pci";
1656                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1657                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1658                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1659                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1660                 /* Map all possible DDR as inbound ranges */
1661                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1662                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1663                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1664                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1665                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1666                 #interrupt-cells = <1>;
1667                 interrupt-map-mask = <0 0 0 0>;
1668                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1669                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1670                 clock-names = "pcie", "pcie_bus";
1671                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1672                 status = "disabled";
1673         };
1674
1675         ipmmu_sy0: mmu@e6280000 {
1676                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1677                 reg = <0 0xe6280000 0 0x1000>;
1678                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1679                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1680                 #iommu-cells = <1>;
1681                 status = "disabled";
1682         };
1683
1684         ipmmu_sy1: mmu@e6290000 {
1685                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1686                 reg = <0 0xe6290000 0 0x1000>;
1687                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1688                 #iommu-cells = <1>;
1689                 status = "disabled";
1690         };
1691
1692         ipmmu_ds: mmu@e6740000 {
1693                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1694                 reg = <0 0xe6740000 0 0x1000>;
1695                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1696                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1697                 #iommu-cells = <1>;
1698                 status = "disabled";
1699         };
1700
1701         ipmmu_mp: mmu@ec680000 {
1702                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1703                 reg = <0 0xec680000 0 0x1000>;
1704                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1705                 #iommu-cells = <1>;
1706                 status = "disabled";
1707         };
1708
1709         ipmmu_mx: mmu@fe951000 {
1710                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1711                 reg = <0 0xfe951000 0 0x1000>;
1712                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1713                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1714                 #iommu-cells = <1>;
1715                 status = "disabled";
1716         };
1717
1718         ipmmu_rt: mmu@ffc80000 {
1719                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1720                 reg = <0 0xffc80000 0 0x1000>;
1721                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1722                 #iommu-cells = <1>;
1723                 status = "disabled";
1724         };
1725
1726         ipmmu_gp: mmu@e62a0000 {
1727                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1728                 reg = <0 0xe62a0000 0 0x1000>;
1729                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1730                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1731                 #iommu-cells = <1>;
1732                 status = "disabled";
1733         };
1734
1735         rcar_sound: sound@ec500000 {
1736                 /*
1737                  * #sound-dai-cells is required
1738                  *
1739                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1740                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1741                  */
1742                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1743                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1744                         <0 0xec5a0000 0 0x100>,  /* ADG */
1745                         <0 0xec540000 0 0x1000>, /* SSIU */
1746                         <0 0xec541000 0 0x280>,  /* SSI */
1747                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1748                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1749
1750                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1751                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1752                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1753                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1754                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1755                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1756                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1757                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1758                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1759                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1760                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1761                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1762                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1763                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1764                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1765                 clock-names = "ssi-all",
1766                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1767                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1768                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1769                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1770                                 "ctu.0", "ctu.1",
1771                                 "mix.0", "mix.1",
1772                                 "dvc.0", "dvc.1",
1773                                 "clk_a", "clk_b", "clk_c", "clk_i";
1774                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1775
1776                 status = "disabled";
1777
1778                 rcar_sound,dvc {
1779                         dvc0: dvc-0 {
1780                                 dmas = <&audma0 0xbc>;
1781                                 dma-names = "tx";
1782                         };
1783                         dvc1: dvc-1 {
1784                                 dmas = <&audma0 0xbe>;
1785                                 dma-names = "tx";
1786                         };
1787                 };
1788
1789                 rcar_sound,mix {
1790                         mix0: mix-0 { };
1791                         mix1: mix-1 { };
1792                 };
1793
1794                 rcar_sound,ctu {
1795                         ctu00: ctu-0 { };
1796                         ctu01: ctu-1 { };
1797                         ctu02: ctu-2 { };
1798                         ctu03: ctu-3 { };
1799                         ctu10: ctu-4 { };
1800                         ctu11: ctu-5 { };
1801                         ctu12: ctu-6 { };
1802                         ctu13: ctu-7 { };
1803                 };
1804
1805                 rcar_sound,src {
1806                         src0: src-0 {
1807                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1808                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1809                                 dma-names = "rx", "tx";
1810                         };
1811                         src1: src-1 {
1812                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1813                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1814                                 dma-names = "rx", "tx";
1815                         };
1816                         src2: src-2 {
1817                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1818                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1819                                 dma-names = "rx", "tx";
1820                         };
1821                         src3: src-3 {
1822                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1823                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1824                                 dma-names = "rx", "tx";
1825                         };
1826                         src4: src-4 {
1827                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1828                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1829                                 dma-names = "rx", "tx";
1830                         };
1831                         src5: src-5 {
1832                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1833                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1834                                 dma-names = "rx", "tx";
1835                         };
1836                         src6: src-6 {
1837                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1838                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1839                                 dma-names = "rx", "tx";
1840                         };
1841                         src7: src-7 {
1842                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1843                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1844                                 dma-names = "rx", "tx";
1845                         };
1846                         src8: src-8 {
1847                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1848                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1849                                 dma-names = "rx", "tx";
1850                         };
1851                         src9: src-9 {
1852                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1853                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1854                                 dma-names = "rx", "tx";
1855                         };
1856                 };
1857
1858                 rcar_sound,ssi {
1859                         ssi0: ssi-0 {
1860                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1861                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1862                                 dma-names = "rx", "tx", "rxu", "txu";
1863                         };
1864                         ssi1: ssi-1 {
1865                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1866                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1867                                 dma-names = "rx", "tx", "rxu", "txu";
1868                         };
1869                         ssi2: ssi-2 {
1870                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1871                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1872                                 dma-names = "rx", "tx", "rxu", "txu";
1873                         };
1874                         ssi3: ssi-3 {
1875                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1876                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1877                                 dma-names = "rx", "tx", "rxu", "txu";
1878                         };
1879                         ssi4: ssi-4 {
1880                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1881                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1882                                 dma-names = "rx", "tx", "rxu", "txu";
1883                         };
1884                         ssi5: ssi-5 {
1885                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1886                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1887                                 dma-names = "rx", "tx", "rxu", "txu";
1888                         };
1889                         ssi6: ssi-6 {
1890                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1891                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1892                                 dma-names = "rx", "tx", "rxu", "txu";
1893                         };
1894                         ssi7: ssi-7 {
1895                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1896                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1897                                 dma-names = "rx", "tx", "rxu", "txu";
1898                         };
1899                         ssi8: ssi-8 {
1900                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1901                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1902                                 dma-names = "rx", "tx", "rxu", "txu";
1903                         };
1904                         ssi9: ssi-9 {
1905                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1906                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1907                                 dma-names = "rx", "tx", "rxu", "txu";
1908                         };
1909                 };
1910         };
1911 };