arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &iic0;
  28                 i2c5 = &iic1;
  29                 i2c6 = &iic2;
  30                 i2c7 = &iic3;
  31                 spi0 = &qspi;
  32                 spi1 = &msiof0;
  33                 spi2 = &msiof1;
  34                 spi3 = &msiof2;
  35                 spi4 = &msiof3;
  36                 vin0 = &vin0;
  37                 vin1 = &vin1;
  38                 vin2 = &vin2;
  39                 vin3 = &vin3;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1300000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1400000 1000000>,
  57                                            <1225000 1000000>,
  58                                            <1050000 1000000>,
  59                                            < 875000 1000000>,
  60                                            < 700000 1000000>,
  61                                            < 350000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1300000000>;
  69                 };
  70
  71                 cpu2: cpu@2 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a15";
  74                         reg = <2>;
  75                         clock-frequency = <1300000000>;
  76                 };
  77
  78                 cpu3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a15";
  81                         reg = <3>;
  82                         clock-frequency = <1300000000>;
  83                 };
  84
  85                 cpu4: cpu@4 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0x100>;
  89                         clock-frequency = <780000000>;
  90                 };
  91
  92                 cpu5: cpu@5 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0x101>;
  96                         clock-frequency = <780000000>;
  97                 };
  98
  99                 cpu6: cpu@6 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a7";
 102                         reg = <0x102>;
 103                         clock-frequency = <780000000>;
 104                 };
 105
 106                 cpu7: cpu@7 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x103>;
 110                         clock-frequency = <780000000>;
 111                 };
 112         };
 113
 114         gic: interrupt-controller@f1001000 {
 115                 compatible = "arm,cortex-a15-gic";
 116                 #interrupt-cells = <3>;
 117                 #address-cells = <0>;
 118                 interrupt-controller;
 119                 reg = <0 0xf1001000 0 0x1000>,
 120                         <0 0xf1002000 0 0x1000>,
 121                         <0 0xf1004000 0 0x2000>,
 122                         <0 0xf1006000 0 0x2000>;
 123                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 124         };
 125
 126         gpio0: gpio@e6050000 {
 127                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 128                 reg = <0 0xe6050000 0 0x50>;
 129                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132                 gpio-ranges = <&pfc 0 0 32>;
 133                 #interrupt-cells = <2>;
 134                 interrupt-controller;
 135                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 136         };
 137
 138         gpio1: gpio@e6051000 {
 139                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 140                 reg = <0 0xe6051000 0 0x50>;
 141                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 32 32>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 148         };
 149
 150         gpio2: gpio@e6052000 {
 151                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 152                 reg = <0 0xe6052000 0 0x50>;
 153                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 154                 #gpio-cells = <2>;
 155                 gpio-controller;
 156                 gpio-ranges = <&pfc 0 64 32>;
 157                 #interrupt-cells = <2>;
 158                 interrupt-controller;
 159                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 160         };
 161
 162         gpio3: gpio@e6053000 {
 163                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 164                 reg = <0 0xe6053000 0 0x50>;
 165                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 166                 #gpio-cells = <2>;
 167                 gpio-controller;
 168                 gpio-ranges = <&pfc 0 96 32>;
 169                 #interrupt-cells = <2>;
 170                 interrupt-controller;
 171                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 172         };
 173
 174         gpio4: gpio@e6054000 {
 175                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 176                 reg = <0 0xe6054000 0 0x50>;
 177                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 178                 #gpio-cells = <2>;
 179                 gpio-controller;
 180                 gpio-ranges = <&pfc 0 128 32>;
 181                 #interrupt-cells = <2>;
 182                 interrupt-controller;
 183                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 184         };
 185
 186         gpio5: gpio@e6055000 {
 187                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 188                 reg = <0 0xe6055000 0 0x50>;
 189                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 190                 #gpio-cells = <2>;
 191                 gpio-controller;
 192                 gpio-ranges = <&pfc 0 160 32>;
 193                 #interrupt-cells = <2>;
 194                 interrupt-controller;
 195                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 196         };
 197
 198         thermal@e61f0000 {
 199                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 200                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 201                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         cmt0: timer@ffca0000 {
 214                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 215                 reg = <0 0xffca0000 0 0x1004>;
 216                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 219                 clock-names = "fck";
 220
 221                 renesas,channels-mask = <0x60>;
 222
 223                 status = "disabled";
 224         };
 225
 226         cmt1: timer@e6130000 {
 227                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 228                 reg = <0 0xe6130000 0 0x1004>;
 229                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 230                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 238                 clock-names = "fck";
 239
 240                 renesas,channels-mask = <0xff>;
 241
 242                 status = "disabled";
 243         };
 244
 245         irqc0: interrupt-controller@e61c0000 {
 246                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 247                 #interrupt-cells = <2>;
 248                 interrupt-controller;
 249                 reg = <0 0xe61c0000 0 0x200>;
 250                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 251                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 252                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 253                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 254         };
 255
 256         dmac0: dma-controller@e6700000 {
 257                 compatible = "renesas,rcar-dmac";
 258                 reg = <0 0xe6700000 0 0x20000>;
 259                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 260                               0 200 IRQ_TYPE_LEVEL_HIGH
 261                               0 201 IRQ_TYPE_LEVEL_HIGH
 262                               0 202 IRQ_TYPE_LEVEL_HIGH
 263                               0 203 IRQ_TYPE_LEVEL_HIGH
 264                               0 204 IRQ_TYPE_LEVEL_HIGH
 265                               0 205 IRQ_TYPE_LEVEL_HIGH
 266                               0 206 IRQ_TYPE_LEVEL_HIGH
 267                               0 207 IRQ_TYPE_LEVEL_HIGH
 268                               0 208 IRQ_TYPE_LEVEL_HIGH
 269                               0 209 IRQ_TYPE_LEVEL_HIGH
 270                               0 210 IRQ_TYPE_LEVEL_HIGH
 271                               0 211 IRQ_TYPE_LEVEL_HIGH
 272                               0 212 IRQ_TYPE_LEVEL_HIGH
 273                               0 213 IRQ_TYPE_LEVEL_HIGH
 274                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 275                 interrupt-names = "error",
 276                                 "ch0", "ch1", "ch2", "ch3",
 277                                 "ch4", "ch5", "ch6", "ch7",
 278                                 "ch8", "ch9", "ch10", "ch11",
 279                                 "ch12", "ch13", "ch14";
 280                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 281                 clock-names = "fck";
 282                 #dma-cells = <1>;
 283                 dma-channels = <15>;
 284         };
 285
 286         dmac1: dma-controller@e6720000 {
 287                 compatible = "renesas,rcar-dmac";
 288                 reg = <0 0xe6720000 0 0x20000>;
 289                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 290                               0 216 IRQ_TYPE_LEVEL_HIGH
 291                               0 217 IRQ_TYPE_LEVEL_HIGH
 292                               0 218 IRQ_TYPE_LEVEL_HIGH
 293                               0 219 IRQ_TYPE_LEVEL_HIGH
 294                               0 308 IRQ_TYPE_LEVEL_HIGH
 295                               0 309 IRQ_TYPE_LEVEL_HIGH
 296                               0 310 IRQ_TYPE_LEVEL_HIGH
 297                               0 311 IRQ_TYPE_LEVEL_HIGH
 298                               0 312 IRQ_TYPE_LEVEL_HIGH
 299                               0 313 IRQ_TYPE_LEVEL_HIGH
 300                               0 314 IRQ_TYPE_LEVEL_HIGH
 301                               0 315 IRQ_TYPE_LEVEL_HIGH
 302                               0 316 IRQ_TYPE_LEVEL_HIGH
 303                               0 317 IRQ_TYPE_LEVEL_HIGH
 304                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 305                 interrupt-names = "error",
 306                                 "ch0", "ch1", "ch2", "ch3",
 307                                 "ch4", "ch5", "ch6", "ch7",
 308                                 "ch8", "ch9", "ch10", "ch11",
 309                                 "ch12", "ch13", "ch14";
 310                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 311                 clock-names = "fck";
 312                 #dma-cells = <1>;
 313                 dma-channels = <15>;
 314         };
 315         i2c0: i2c@e6508000 {
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 compatible = "renesas,i2c-r8a7790";
 319                 reg = <0 0xe6508000 0 0x40>;
 320                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 322                 status = "disabled";
 323         };
 324
 325         i2c1: i2c@e6518000 {
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 compatible = "renesas,i2c-r8a7790";
 329                 reg = <0 0xe6518000 0 0x40>;
 330                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 332                 status = "disabled";
 333         };
 334
 335         i2c2: i2c@e6530000 {
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 compatible = "renesas,i2c-r8a7790";
 339                 reg = <0 0xe6530000 0 0x40>;
 340                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 342                 status = "disabled";
 343         };
 344
 345         i2c3: i2c@e6540000 {
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 compatible = "renesas,i2c-r8a7790";
 349                 reg = <0 0xe6540000 0 0x40>;
 350                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 352                 status = "disabled";
 353         };
 354
 355         iic0: i2c@e6500000 {
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 359                 reg = <0 0xe6500000 0 0x425>;
 360                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 361                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 362                 status = "disabled";
 363         };
 364
 365         iic1: i2c@e6510000 {
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 369                 reg = <0 0xe6510000 0 0x425>;
 370                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 372                 status = "disabled";
 373         };
 374
 375         iic2: i2c@e6520000 {
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 379                 reg = <0 0xe6520000 0 0x425>;
 380                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 382                 status = "disabled";
 383         };
 384
 385         iic3: i2c@e60b0000 {
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 389                 reg = <0 0xe60b0000 0 0x425>;
 390                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 392                 status = "disabled";
 393         };
 394
 395         mmcif0: mmcif@ee200000 {
 396                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 397                 reg = <0 0xee200000 0 0x80>;
 398                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 400                 reg-io-width = <4>;
 401                 status = "disabled";
 402         };
 403
 404         mmcif1: mmc@ee220000 {
 405                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 406                 reg = <0 0xee220000 0 0x80>;
 407                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 409                 reg-io-width = <4>;
 410                 status = "disabled";
 411         };
 412
 413         pfc: pfc@e6060000 {
 414                 compatible = "renesas,pfc-r8a7790";
 415                 reg = <0 0xe6060000 0 0x250>;
 416         };
 417
 418         sdhi0: sd@ee100000 {
 419                 compatible = "renesas,sdhi-r8a7790";
 420                 reg = <0 0xee100000 0 0x200>;
 421                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 423                 cap-sd-highspeed;
 424                 status = "disabled";
 425         };
 426
 427         sdhi1: sd@ee120000 {
 428                 compatible = "renesas,sdhi-r8a7790";
 429                 reg = <0 0xee120000 0 0x200>;
 430                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 432                 cap-sd-highspeed;
 433                 status = "disabled";
 434         };
 435
 436         sdhi2: sd@ee140000 {
 437                 compatible = "renesas,sdhi-r8a7790";
 438                 reg = <0 0xee140000 0 0x100>;
 439                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 440                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 441                 cap-sd-highspeed;
 442                 status = "disabled";
 443         };
 444
 445         sdhi3: sd@ee160000 {
 446                 compatible = "renesas,sdhi-r8a7790";
 447                 reg = <0 0xee160000 0 0x100>;
 448                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 449                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 450                 cap-sd-highspeed;
 451                 status = "disabled";
 452         };
 453
 454         scifa0: serial@e6c40000 {
 455                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 456                 reg = <0 0xe6c40000 0 64>;
 457                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 459                 clock-names = "sci_ick";
 460                 status = "disabled";
 461         };
 462
 463         scifa1: serial@e6c50000 {
 464                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 465                 reg = <0 0xe6c50000 0 64>;
 466                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 468                 clock-names = "sci_ick";
 469                 status = "disabled";
 470         };
 471
 472         scifa2: serial@e6c60000 {
 473                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 474                 reg = <0 0xe6c60000 0 64>;
 475                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 477                 clock-names = "sci_ick";
 478                 status = "disabled";
 479         };
 480
 481         scifb0: serial@e6c20000 {
 482                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 483                 reg = <0 0xe6c20000 0 64>;
 484                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 485                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 486                 clock-names = "sci_ick";
 487                 status = "disabled";
 488         };
 489
 490         scifb1: serial@e6c30000 {
 491                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 492                 reg = <0 0xe6c30000 0 64>;
 493                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 494                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 495                 clock-names = "sci_ick";
 496                 status = "disabled";
 497         };
 498
 499         scifb2: serial@e6ce0000 {
 500                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 501                 reg = <0 0xe6ce0000 0 64>;
 502                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 504                 clock-names = "sci_ick";
 505                 status = "disabled";
 506         };
 507
 508         scif0: serial@e6e60000 {
 509                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 510                 reg = <0 0xe6e60000 0 64>;
 511                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 513                 clock-names = "sci_ick";
 514                 status = "disabled";
 515         };
 516
 517         scif1: serial@e6e68000 {
 518                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 519                 reg = <0 0xe6e68000 0 64>;
 520                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 521                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 522                 clock-names = "sci_ick";
 523                 status = "disabled";
 524         };
 525
 526         hscif0: serial@e62c0000 {
 527                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 528                 reg = <0 0xe62c0000 0 96>;
 529                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 531                 clock-names = "sci_ick";
 532                 status = "disabled";
 533         };
 534
 535         hscif1: serial@e62c8000 {
 536                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 537                 reg = <0 0xe62c8000 0 96>;
 538                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 540                 clock-names = "sci_ick";
 541                 status = "disabled";
 542         };
 543
 544         ether: ethernet@ee700000 {
 545                 compatible = "renesas,ether-r8a7790";
 546                 reg = <0 0xee700000 0 0x400>;
 547                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 549                 phy-mode = "rmii";
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         sata0: sata@ee300000 {
 556                 compatible = "renesas,sata-r8a7790";
 557                 reg = <0 0xee300000 0 0x2000>;
 558                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 559                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 560                 status = "disabled";
 561         };
 562
 563         sata1: sata@ee500000 {
 564                 compatible = "renesas,sata-r8a7790";
 565                 reg = <0 0xee500000 0 0x2000>;
 566                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 568                 status = "disabled";
 569         };
 570
 571         vin0: video@e6ef0000 {
 572                 compatible = "renesas,vin-r8a7790";
 573                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 574                 reg = <0 0xe6ef0000 0 0x1000>;
 575                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 576                 status = "disabled";
 577         };
 578
 579         vin1: video@e6ef1000 {
 580                 compatible = "renesas,vin-r8a7790";
 581                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 582                 reg = <0 0xe6ef1000 0 0x1000>;
 583                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 584                 status = "disabled";
 585         };
 586
 587         vin2: video@e6ef2000 {
 588                 compatible = "renesas,vin-r8a7790";
 589                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 590                 reg = <0 0xe6ef2000 0 0x1000>;
 591                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 592                 status = "disabled";
 593         };
 594
 595         vin3: video@e6ef3000 {
 596                 compatible = "renesas,vin-r8a7790";
 597                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 598                 reg = <0 0xe6ef3000 0 0x1000>;
 599                 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
 600                 status = "disabled";
 601         };
 602
 603         clocks {
 604                 #address-cells = <2>;
 605                 #size-cells = <2>;
 606                 ranges;
 607
 608                 /* External root clock */
 609                 extal_clk: extal_clk {
 610                         compatible = "fixed-clock";
 611                         #clock-cells = <0>;
 612                         /* This value must be overriden by the board. */
 613                         clock-frequency = <0>;
 614                         clock-output-names = "extal";
 615                 };
 616
 617                 /* External PCIe clock - can be overridden by the board */
 618                 pcie_bus_clk: pcie_bus_clk {
 619                         compatible = "fixed-clock";
 620                         #clock-cells = <0>;
 621                         clock-frequency = <100000000>;
 622                         clock-output-names = "pcie_bus";
 623                         status = "disabled";
 624                 };
 625
 626                 /*
 627                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 628                  * default. Boards that provide audio clocks should override them.
 629                  */
 630                 audio_clk_a: audio_clk_a {
 631                         compatible = "fixed-clock";
 632                         #clock-cells = <0>;
 633                         clock-frequency = <0>;
 634                         clock-output-names = "audio_clk_a";
 635                 };
 636                 audio_clk_b: audio_clk_b {
 637                         compatible = "fixed-clock";
 638                         #clock-cells = <0>;
 639                         clock-frequency = <0>;
 640                         clock-output-names = "audio_clk_b";
 641                 };
 642                 audio_clk_c: audio_clk_c {
 643                         compatible = "fixed-clock";
 644                         #clock-cells = <0>;
 645                         clock-frequency = <0>;
 646                         clock-output-names = "audio_clk_c";
 647                 };
 648
 649                 /* Special CPG clocks */
 650                 cpg_clocks: cpg_clocks@e6150000 {
 651                         compatible = "renesas,r8a7790-cpg-clocks",
 652                                      "renesas,rcar-gen2-cpg-clocks";
 653                         reg = <0 0xe6150000 0 0x1000>;
 654                         clocks = <&extal_clk>;
 655                         #clock-cells = <1>;
 656                         clock-output-names = "main", "pll0", "pll1", "pll3",
 657                                              "lb", "qspi", "sdh", "sd0", "sd1",
 658                                              "z";
 659                 };
 660
 661                 /* Variable factor clocks */
 662                 sd2_clk: sd2_clk@e6150078 {
 663                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 664                         reg = <0 0xe6150078 0 4>;
 665                         clocks = <&pll1_div2_clk>;
 666                         #clock-cells = <0>;
 667                         clock-output-names = "sd2";
 668                 };
 669                 sd3_clk: sd3_clk@e615007c {
 670                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 671                         reg = <0 0xe615007c 0 4>;
 672                         clocks = <&pll1_div2_clk>;
 673                         #clock-cells = <0>;
 674                         clock-output-names = "sd3";
 675                 };
 676                 mmc0_clk: mmc0_clk@e6150240 {
 677                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 678                         reg = <0 0xe6150240 0 4>;
 679                         clocks = <&pll1_div2_clk>;
 680                         #clock-cells = <0>;
 681                         clock-output-names = "mmc0";
 682                 };
 683                 mmc1_clk: mmc1_clk@e6150244 {
 684                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 685                         reg = <0 0xe6150244 0 4>;
 686                         clocks = <&pll1_div2_clk>;
 687                         #clock-cells = <0>;
 688                         clock-output-names = "mmc1";
 689                 };
 690                 ssp_clk: ssp_clk@e6150248 {
 691                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 692                         reg = <0 0xe6150248 0 4>;
 693                         clocks = <&pll1_div2_clk>;
 694                         #clock-cells = <0>;
 695                         clock-output-names = "ssp";
 696                 };
 697                 ssprs_clk: ssprs_clk@e615024c {
 698                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 699                         reg = <0 0xe615024c 0 4>;
 700                         clocks = <&pll1_div2_clk>;
 701                         #clock-cells = <0>;
 702                         clock-output-names = "ssprs";
 703                 };
 704
 705                 /* Fixed factor clocks */
 706                 pll1_div2_clk: pll1_div2_clk {
 707                         compatible = "fixed-factor-clock";
 708                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 709                         #clock-cells = <0>;
 710                         clock-div = <2>;
 711                         clock-mult = <1>;
 712                         clock-output-names = "pll1_div2";
 713                 };
 714                 z2_clk: z2_clk {
 715                         compatible = "fixed-factor-clock";
 716                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 717                         #clock-cells = <0>;
 718                         clock-div = <2>;
 719                         clock-mult = <1>;
 720                         clock-output-names = "z2";
 721                 };
 722                 zg_clk: zg_clk {
 723                         compatible = "fixed-factor-clock";
 724                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 725                         #clock-cells = <0>;
 726                         clock-div = <3>;
 727                         clock-mult = <1>;
 728                         clock-output-names = "zg";
 729                 };
 730                 zx_clk: zx_clk {
 731                         compatible = "fixed-factor-clock";
 732                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 733                         #clock-cells = <0>;
 734                         clock-div = <3>;
 735                         clock-mult = <1>;
 736                         clock-output-names = "zx";
 737                 };
 738                 zs_clk: zs_clk {
 739                         compatible = "fixed-factor-clock";
 740                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 741                         #clock-cells = <0>;
 742                         clock-div = <6>;
 743                         clock-mult = <1>;
 744                         clock-output-names = "zs";
 745                 };
 746                 hp_clk: hp_clk {
 747                         compatible = "fixed-factor-clock";
 748                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 749                         #clock-cells = <0>;
 750                         clock-div = <12>;
 751                         clock-mult = <1>;
 752                         clock-output-names = "hp";
 753                 };
 754                 i_clk: i_clk {
 755                         compatible = "fixed-factor-clock";
 756                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 757                         #clock-cells = <0>;
 758                         clock-div = <2>;
 759                         clock-mult = <1>;
 760                         clock-output-names = "i";
 761                 };
 762                 b_clk: b_clk {
 763                         compatible = "fixed-factor-clock";
 764                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 765                         #clock-cells = <0>;
 766                         clock-div = <12>;
 767                         clock-mult = <1>;
 768                         clock-output-names = "b";
 769                 };
 770                 p_clk: p_clk {
 771                         compatible = "fixed-factor-clock";
 772                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 773                         #clock-cells = <0>;
 774                         clock-div = <24>;
 775                         clock-mult = <1>;
 776                         clock-output-names = "p";
 777                 };
 778                 cl_clk: cl_clk {
 779                         compatible = "fixed-factor-clock";
 780                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 781                         #clock-cells = <0>;
 782                         clock-div = <48>;
 783                         clock-mult = <1>;
 784                         clock-output-names = "cl";
 785                 };
 786                 m2_clk: m2_clk {
 787                         compatible = "fixed-factor-clock";
 788                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 789                         #clock-cells = <0>;
 790                         clock-div = <8>;
 791                         clock-mult = <1>;
 792                         clock-output-names = "m2";
 793                 };
 794                 imp_clk: imp_clk {
 795                         compatible = "fixed-factor-clock";
 796                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 797                         #clock-cells = <0>;
 798                         clock-div = <4>;
 799                         clock-mult = <1>;
 800                         clock-output-names = "imp";
 801                 };
 802                 rclk_clk: rclk_clk {
 803                         compatible = "fixed-factor-clock";
 804                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 805                         #clock-cells = <0>;
 806                         clock-div = <(48 * 1024)>;
 807                         clock-mult = <1>;
 808                         clock-output-names = "rclk";
 809                 };
 810                 oscclk_clk: oscclk_clk {
 811                         compatible = "fixed-factor-clock";
 812                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 813                         #clock-cells = <0>;
 814                         clock-div = <(12 * 1024)>;
 815                         clock-mult = <1>;
 816                         clock-output-names = "oscclk";
 817                 };
 818                 zb3_clk: zb3_clk {
 819                         compatible = "fixed-factor-clock";
 820                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 821                         #clock-cells = <0>;
 822                         clock-div = <4>;
 823                         clock-mult = <1>;
 824                         clock-output-names = "zb3";
 825                 };
 826                 zb3d2_clk: zb3d2_clk {
 827                         compatible = "fixed-factor-clock";
 828                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 829                         #clock-cells = <0>;
 830                         clock-div = <8>;
 831                         clock-mult = <1>;
 832                         clock-output-names = "zb3d2";
 833                 };
 834                 ddr_clk: ddr_clk {
 835                         compatible = "fixed-factor-clock";
 836                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 837                         #clock-cells = <0>;
 838                         clock-div = <8>;
 839                         clock-mult = <1>;
 840                         clock-output-names = "ddr";
 841                 };
 842                 mp_clk: mp_clk {
 843                         compatible = "fixed-factor-clock";
 844                         clocks = <&pll1_div2_clk>;
 845                         #clock-cells = <0>;
 846                         clock-div = <15>;
 847                         clock-mult = <1>;
 848                         clock-output-names = "mp";
 849                 };
 850                 cp_clk: cp_clk {
 851                         compatible = "fixed-factor-clock";
 852                         clocks = <&extal_clk>;
 853                         #clock-cells = <0>;
 854                         clock-div = <2>;
 855                         clock-mult = <1>;
 856                         clock-output-names = "cp";
 857                 };
 858
 859                 /* Gate clocks */
 860                 mstp0_clks: mstp0_clks@e6150130 {
 861                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 862                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 863                         clocks = <&mp_clk>;
 864                         #clock-cells = <1>;
 865                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 866                         clock-output-names = "msiof0";
 867                 };
 868                 mstp1_clks: mstp1_clks@e6150134 {
 869                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 870                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 871                         clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 872                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 873                                  <&zs_clk>;
 874                         #clock-cells = <1>;
 875                         renesas,clock-indices = <
 876                                 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 877                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 878                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
 879                         >;
 880                         clock-output-names =
 881                                 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 882                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 883                 };
 884                 mstp2_clks: mstp2_clks@e6150138 {
 885                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 886                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 887                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 888                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
 889                                  <&zs_clk>;
 890                         #clock-cells = <1>;
 891                         renesas,clock-indices = <
 892                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 893                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 894                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 895                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
 896                         >;
 897                         clock-output-names =
 898                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 899                                 "scifb1", "msiof1", "msiof3", "scifb2",
 900                                 "sys-dmac1", "sys-dmac0";
 901                 };
 902                 mstp3_clks: mstp3_clks@e615013c {
 903                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 904                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 905                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
 906                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 907                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 908                         #clock-cells = <1>;
 909                         renesas,clock-indices = <
 910                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 911                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 912                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 913                         >;
 914                         clock-output-names =
 915                                 "iic2", "tpu0", "mmcif1", "sdhi3",
 916                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 917                                 "iic0", "pciec", "iic1", "ssusb", "cmt1";
 918                 };
 919                 mstp5_clks: mstp5_clks@e6150144 {
 920                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 921                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 922                         clocks = <&extal_clk>, <&p_clk>;
 923                         #clock-cells = <1>;
 924                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 925                         clock-output-names = "thermal", "pwm";
 926                 };
 927                 mstp7_clks: mstp7_clks@e615014c {
 928                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 929                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 930                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 931                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 932                                  <&zx_clk>;
 933                         #clock-cells = <1>;
 934                         renesas,clock-indices = <
 935                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 936                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 937                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 938                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 939                         >;
 940                         clock-output-names =
 941                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 942                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 943                 };
 944                 mstp8_clks: mstp8_clks@e6150990 {
 945                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 946                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 947                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 948                                  <&zs_clk>, <&zs_clk>;
 949                         #clock-cells = <1>;
 950                         renesas,clock-indices = <
 951                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 952                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 953                                 R8A7790_CLK_SATA0
 954                         >;
 955                         clock-output-names =
 956                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 957                 };
 958                 mstp9_clks: mstp9_clks@e6150994 {
 959                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 960                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 961                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
 962                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
 963                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 964                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 965                         #clock-cells = <1>;
 966                         renesas,clock-indices = <
 967                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
 968                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
 969                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
 970                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 971                         >;
 972                         clock-output-names =
 973                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 974                                 "rcan1", "rcan0", "qspi_mod", "iic3",
 975                                 "i2c3", "i2c2", "i2c1", "i2c0";
 976                 };
 977                 mstp10_clks: mstp10_clks@e6150998 {
 978                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 979                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 980                         clocks = <&p_clk>,
 981                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 982                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 983                                 <&p_clk>,
 984                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 985                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 986                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 987                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 988                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 989                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 990
 991                         #clock-cells = <1>;
 992                         clock-indices = <
 993                                 R8A7790_CLK_SSI_ALL
 994                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
 995                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
 996                                 R8A7790_CLK_SCU_ALL
 997                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
 998                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
 999                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1000                         >;
1001                         clock-output-names =
1002                                 "ssi-all",
1003                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1004                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1005                                 "scu-all",
1006                                 "scu-dvc1", "scu-dvc0",
1007                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1008                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1009                 };
1010         };
1011
1012         qspi: spi@e6b10000 {
1013                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1014                 reg = <0 0xe6b10000 0 0x2c>;
1015                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1016                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1017                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1018                 dma-names = "tx", "rx";
1019                 num-cs = <1>;
1020                 #address-cells = <1>;
1021                 #size-cells = <0>;
1022                 status = "disabled";
1023         };
1024
1025         msiof0: spi@e6e20000 {
1026                 compatible = "renesas,msiof-r8a7790";
1027                 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1028                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1029                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1030                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1031                 dma-names = "tx", "rx";
1032                 #address-cells = <1>;
1033                 #size-cells = <0>;
1034                 status = "disabled";
1035         };
1036
1037         msiof1: spi@e6e10000 {
1038                 compatible = "renesas,msiof-r8a7790";
1039                 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1040                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1041                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1042                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1043                 dma-names = "tx", "rx";
1044                 #address-cells = <1>;
1045                 #size-cells = <0>;
1046                 status = "disabled";
1047         };
1048
1049         msiof2: spi@e6e00000 {
1050                 compatible = "renesas,msiof-r8a7790";
1051                 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1052                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1053                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1054                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1055                 dma-names = "tx", "rx";
1056                 #address-cells = <1>;
1057                 #size-cells = <0>;
1058                 status = "disabled";
1059         };
1060
1061         msiof3: spi@e6c90000 {
1062                 compatible = "renesas,msiof-r8a7790";
1063                 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1064                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1065                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1066                 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1067                 dma-names = "tx", "rx";
1068                 #address-cells = <1>;
1069                 #size-cells = <0>;
1070                 status = "disabled";
1071         };
1072
1073         pci0: pci@ee090000 {
1074                 compatible = "renesas,pci-r8a7790";
1075                 device_type = "pci";
1076                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1077                 reg = <0 0xee090000 0 0xc00>,
1078                       <0 0xee080000 0 0x1100>;
1079                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1080                 status = "disabled";
1081
1082                 bus-range = <0 0>;
1083                 #address-cells = <3>;
1084                 #size-cells = <2>;
1085                 #interrupt-cells = <1>;
1086                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1087                 interrupt-map-mask = <0xff00 0 0 0x7>;
1088                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1089                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1090                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1091         };
1092
1093         pci1: pci@ee0b0000 {
1094                 compatible = "renesas,pci-r8a7790";
1095                 device_type = "pci";
1096                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1097                 reg = <0 0xee0b0000 0 0xc00>,
1098                       <0 0xee0a0000 0 0x1100>;
1099                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1100                 status = "disabled";
1101
1102                 bus-range = <1 1>;
1103                 #address-cells = <3>;
1104                 #size-cells = <2>;
1105                 #interrupt-cells = <1>;
1106                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1107                 interrupt-map-mask = <0xff00 0 0 0x7>;
1108                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1109                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1110                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1111         };
1112
1113         pci2: pci@ee0d0000 {
1114                 compatible = "renesas,pci-r8a7790";
1115                 device_type = "pci";
1116                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1117                 reg = <0 0xee0d0000 0 0xc00>,
1118                       <0 0xee0c0000 0 0x1100>;
1119                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1120                 status = "disabled";
1121
1122                 bus-range = <2 2>;
1123                 #address-cells = <3>;
1124                 #size-cells = <2>;
1125                 #interrupt-cells = <1>;
1126                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1127                 interrupt-map-mask = <0xff00 0 0 0x7>;
1128                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1129                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1130                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1131         };
1132
1133         pciec: pcie@fe000000 {
1134                 compatible = "renesas,pcie-r8a7790";
1135                 reg = <0 0xfe000000 0 0x80000>;
1136                 #address-cells = <3>;
1137                 #size-cells = <2>;
1138                 bus-range = <0x00 0xff>;
1139                 device_type = "pci";
1140                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1141                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1142                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1143                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1144                 /* Map all possible DDR as inbound ranges */
1145                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1146                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1147                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1148                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1149                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1150                 #interrupt-cells = <1>;
1151                 interrupt-map-mask = <0 0 0 0>;
1152                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1153                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1154                 clock-names = "pcie", "pcie_bus";
1155                 status = "disabled";
1156         };
1157
1158         rcar_sound: rcar_sound@0xec500000 {
1159                 #sound-dai-cells = <1>;
1160                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1161                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1162                         <0 0xec5a0000 0 0x100>,  /* ADG */
1163                         <0 0xec540000 0 0x1000>, /* SSIU */
1164                         <0 0xec541000 0 0x1280>; /* SSI */
1165                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1166                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1167                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1168                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1169                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1170                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1171                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1172                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1173                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1174                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1175                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1176                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1177                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1178                 clock-names = "ssi-all",
1179                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1180                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1181                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1182                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1183                                 "dvc.0", "dvc.1",
1184                                 "clk_a", "clk_b", "clk_c", "clk_i";
1185
1186                 status = "disabled";
1187
1188                 rcar_sound,dvc {
1189                         dvc0: dvc@0 { };
1190                         dvc1: dvc@1 { };
1191                 };
1192
1193                 rcar_sound,src {
1194                         src0: src@0 { };
1195                         src1: src@1 { };
1196                         src2: src@2 { };
1197                         src3: src@3 { };
1198                         src4: src@4 { };
1199                         src5: src@5 { };
1200                         src6: src@6 { };
1201                         src7: src@7 { };
1202                         src8: src@8 { };
1203                         src9: src@9 { };
1204                 };
1205
1206                 rcar_sound,ssi {
1207                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1208                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1209                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1210                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1211                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1212                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1213                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1214                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1215                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1216                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1217                 };
1218         };
1219 };