arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7790-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7790-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7790";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &iic0;
  30                 i2c5 = &iic1;
  31                 i2c6 = &iic2;
  32                 i2c7 = &iic3;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 spi4 = &msiof3;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41                 vin3 = &vin3;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 enable-method = "renesas,apmu";
  48
  49                 cpu0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a15";
  52                         reg = <0>;
  53                         clock-frequency = <1300000000>;
  54                         voltage-tolerance = <1>; /* 1% */
  55                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  56                         clock-latency = <300000>; /* 300 us */
  57                         power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
  58                         next-level-cache = <&L2_CA15>;
  59
  60                         /* kHz - uV - OPPs unknown yet */
  61                         operating-points = <1400000 1000000>,
  62                                            <1225000 1000000>,
  63                                            <1050000 1000000>,
  64                                            < 875000 1000000>,
  65                                            < 700000 1000000>,
  66                                            < 350000 1000000>;
  67                 };
  68
  69                 cpu1: cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <1>;
  73                         clock-frequency = <1300000000>;
  74                         power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
  75                         next-level-cache = <&L2_CA15>;
  76                 };
  77
  78                 cpu2: cpu@2 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a15";
  81                         reg = <2>;
  82                         clock-frequency = <1300000000>;
  83                         power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
  84                         next-level-cache = <&L2_CA15>;
  85                 };
  86
  87                 cpu3: cpu@3 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a15";
  90                         reg = <3>;
  91                         clock-frequency = <1300000000>;
  92                         power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
  93                         next-level-cache = <&L2_CA15>;
  94                 };
  95
  96                 cpu4: cpu@100 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a7";
  99                         reg = <0x100>;
 100                         clock-frequency = <780000000>;
 101                         power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
 102                         next-level-cache = <&L2_CA7>;
 103                 };
 104
 105                 cpu5: cpu@101 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x101>;
 109                         clock-frequency = <780000000>;
 110                         power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
 111                         next-level-cache = <&L2_CA7>;
 112                 };
 113
 114                 cpu6: cpu@102 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x102>;
 118                         clock-frequency = <780000000>;
 119                         power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
 120                         next-level-cache = <&L2_CA7>;
 121                 };
 122
 123                 cpu7: cpu@103 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a7";
 126                         reg = <0x103>;
 127                         clock-frequency = <780000000>;
 128                         power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
 129                         next-level-cache = <&L2_CA7>;
 130                 };
 131
 132                 L2_CA15: cache-controller-0 {
 133                         compatible = "cache";
 134                         power-domains = <&sysc R8A7790_PD_CA15_SCU>;
 135                         cache-unified;
 136                         cache-level = <2>;
 137                 };
 138
 139                 L2_CA7: cache-controller-1 {
 140                         compatible = "cache";
 141                         power-domains = <&sysc R8A7790_PD_CA7_SCU>;
 142                         cache-unified;
 143                         cache-level = <2>;
 144                 };
 145         };
 146
 147         thermal-zones {
 148                 cpu_thermal: cpu-thermal {
 149                         polling-delay-passive   = <0>;
 150                         polling-delay           = <0>;
 151
 152                         thermal-sensors = <&thermal>;
 153
 154                         trips {
 155                                 cpu-crit {
 156                                         temperature     = <115000>;
 157                                         hysteresis      = <0>;
 158                                         type            = "critical";
 159                                 };
 160                         };
 161                         cooling-maps {
 162                         };
 163                 };
 164         };
 165
 166         apmu@e6151000 {
 167                 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
 168                 reg = <0 0xe6151000 0 0x188>;
 169                 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
 170         };
 171
 172         apmu@e6152000 {
 173                 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
 174                 reg = <0 0xe6152000 0 0x188>;
 175                 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
 176         };
 177
 178         gic: interrupt-controller@f1001000 {
 179                 compatible = "arm,gic-400";
 180                 #interrupt-cells = <3>;
 181                 #address-cells = <0>;
 182                 interrupt-controller;
 183                 reg = <0 0xf1001000 0 0x1000>,
 184                         <0 0xf1002000 0 0x2000>,
 185                         <0 0xf1004000 0 0x2000>,
 186                         <0 0xf1006000 0 0x2000>;
 187                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 188                 clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
 189                 clock-names = "clk";
 190                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 191         };
 192
 193         gpio0: gpio@e6050000 {
 194                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 195                 reg = <0 0xe6050000 0 0x50>;
 196                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 197                 #gpio-cells = <2>;
 198                 gpio-controller;
 199                 gpio-ranges = <&pfc 0 0 32>;
 200                 #interrupt-cells = <2>;
 201                 interrupt-controller;
 202                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 203                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 204         };
 205
 206         gpio1: gpio@e6051000 {
 207                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 208                 reg = <0 0xe6051000 0 0x50>;
 209                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 210                 #gpio-cells = <2>;
 211                 gpio-controller;
 212                 gpio-ranges = <&pfc 0 32 30>;
 213                 #interrupt-cells = <2>;
 214                 interrupt-controller;
 215                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 216                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 217         };
 218
 219         gpio2: gpio@e6052000 {
 220                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 221                 reg = <0 0xe6052000 0 0x50>;
 222                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 223                 #gpio-cells = <2>;
 224                 gpio-controller;
 225                 gpio-ranges = <&pfc 0 64 30>;
 226                 #interrupt-cells = <2>;
 227                 interrupt-controller;
 228                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 229                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 230         };
 231
 232         gpio3: gpio@e6053000 {
 233                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 234                 reg = <0 0xe6053000 0 0x50>;
 235                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 236                 #gpio-cells = <2>;
 237                 gpio-controller;
 238                 gpio-ranges = <&pfc 0 96 32>;
 239                 #interrupt-cells = <2>;
 240                 interrupt-controller;
 241                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 242                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 243         };
 244
 245         gpio4: gpio@e6054000 {
 246                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 247                 reg = <0 0xe6054000 0 0x50>;
 248                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 249                 #gpio-cells = <2>;
 250                 gpio-controller;
 251                 gpio-ranges = <&pfc 0 128 32>;
 252                 #interrupt-cells = <2>;
 253                 interrupt-controller;
 254                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 255                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 256         };
 257
 258         gpio5: gpio@e6055000 {
 259                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 260                 reg = <0 0xe6055000 0 0x50>;
 261                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 262                 #gpio-cells = <2>;
 263                 gpio-controller;
 264                 gpio-ranges = <&pfc 0 160 32>;
 265                 #interrupt-cells = <2>;
 266                 interrupt-controller;
 267                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 268                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 269         };
 270
 271         thermal: thermal@e61f0000 {
 272                 compatible =    "renesas,thermal-r8a7790",
 273                                 "renesas,rcar-gen2-thermal",
 274                                 "renesas,rcar-thermal";
 275                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 276                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 277                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 278                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 279                 #thermal-sensor-cells = <0>;
 280         };
 281
 282         timer {
 283                 compatible = "arm,armv7-timer";
 284                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 285                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 286                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 287                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 288         };
 289
 290         cmt0: timer@ffca0000 {
 291                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 292                 reg = <0 0xffca0000 0 0x1004>;
 293                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 296                 clock-names = "fck";
 297                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 298
 299                 renesas,channels-mask = <0x60>;
 300
 301                 status = "disabled";
 302         };
 303
 304         cmt1: timer@e6130000 {
 305                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 306                 reg = <0 0xe6130000 0 0x1004>;
 307                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 316                 clock-names = "fck";
 317                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 318
 319                 renesas,channels-mask = <0xff>;
 320
 321                 status = "disabled";
 322         };
 323
 324         irqc0: interrupt-controller@e61c0000 {
 325                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 326                 #interrupt-cells = <2>;
 327                 interrupt-controller;
 328                 reg = <0 0xe61c0000 0 0x200>;
 329                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
 334                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 335         };
 336
 337         dmac0: dma-controller@e6700000 {
 338                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 339                 reg = <0 0xe6700000 0 0x20000>;
 340                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 343                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 344                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 345                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 346                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 347                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 348                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 349                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 350                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 351                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 352                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 353                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 354                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 355                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 356                 interrupt-names = "error",
 357                                 "ch0", "ch1", "ch2", "ch3",
 358                                 "ch4", "ch5", "ch6", "ch7",
 359                                 "ch8", "ch9", "ch10", "ch11",
 360                                 "ch12", "ch13", "ch14";
 361                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 362                 clock-names = "fck";
 363                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 364                 #dma-cells = <1>;
 365                 dma-channels = <15>;
 366         };
 367
 368         dmac1: dma-controller@e6720000 {
 369                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 370                 reg = <0 0xe6720000 0 0x20000>;
 371                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 372                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 373                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 374                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 375                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 376                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 377                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 378                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 379                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 380                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 381                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 382                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 383                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 384                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 385                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 386                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 387                 interrupt-names = "error",
 388                                 "ch0", "ch1", "ch2", "ch3",
 389                                 "ch4", "ch5", "ch6", "ch7",
 390                                 "ch8", "ch9", "ch10", "ch11",
 391                                 "ch12", "ch13", "ch14";
 392                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 393                 clock-names = "fck";
 394                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 395                 #dma-cells = <1>;
 396                 dma-channels = <15>;
 397         };
 398
 399         audma0: dma-controller@ec700000 {
 400                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 401                 reg = <0 0xec700000 0 0x10000>;
 402                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 403                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 404                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 405                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 406                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 407                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 408                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 409                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 410                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 411                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 412                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 413                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 414                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 415                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 416                 interrupt-names = "error",
 417                                 "ch0", "ch1", "ch2", "ch3",
 418                                 "ch4", "ch5", "ch6", "ch7",
 419                                 "ch8", "ch9", "ch10", "ch11",
 420                                 "ch12";
 421                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 422                 clock-names = "fck";
 423                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 424                 #dma-cells = <1>;
 425                 dma-channels = <13>;
 426         };
 427
 428         audma1: dma-controller@ec720000 {
 429                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 430                 reg = <0 0xec720000 0 0x10000>;
 431                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 432                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 433                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 434                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 435                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 436                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 437                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 438                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 439                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 440                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 441                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 442                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 443                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 444                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 445                 interrupt-names = "error",
 446                                 "ch0", "ch1", "ch2", "ch3",
 447                                 "ch4", "ch5", "ch6", "ch7",
 448                                 "ch8", "ch9", "ch10", "ch11",
 449                                 "ch12";
 450                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 451                 clock-names = "fck";
 452                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 453                 #dma-cells = <1>;
 454                 dma-channels = <13>;
 455         };
 456
 457         usb_dmac0: dma-controller@e65a0000 {
 458                 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 459                 reg = <0 0xe65a0000 0 0x100>;
 460                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 461                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 462                 interrupt-names = "ch0", "ch1";
 463                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
 464                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 465                 #dma-cells = <1>;
 466                 dma-channels = <2>;
 467         };
 468
 469         usb_dmac1: dma-controller@e65b0000 {
 470                 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 471                 reg = <0 0xe65b0000 0 0x100>;
 472                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 473                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 474                 interrupt-names = "ch0", "ch1";
 475                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
 476                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 477                 #dma-cells = <1>;
 478                 dma-channels = <2>;
 479         };
 480
 481         i2c0: i2c@e6508000 {
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
 485                 reg = <0 0xe6508000 0 0x40>;
 486                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 488                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 489                 i2c-scl-internal-delay-ns = <110>;
 490                 status = "disabled";
 491         };
 492
 493         i2c1: i2c@e6518000 {
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
 497                 reg = <0 0xe6518000 0 0x40>;
 498                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 500                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 501                 i2c-scl-internal-delay-ns = <6>;
 502                 status = "disabled";
 503         };
 504
 505         i2c2: i2c@e6530000 {
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
 509                 reg = <0 0xe6530000 0 0x40>;
 510                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 511                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 512                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 513                 i2c-scl-internal-delay-ns = <6>;
 514                 status = "disabled";
 515         };
 516
 517         i2c3: i2c@e6540000 {
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
 521                 reg = <0 0xe6540000 0 0x40>;
 522                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 524                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 525                 i2c-scl-internal-delay-ns = <110>;
 526                 status = "disabled";
 527         };
 528
 529         iic0: i2c@e6500000 {
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
 533                              "renesas,rmobile-iic";
 534                 reg = <0 0xe6500000 0 0x425>;
 535                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 537                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 538                        <&dmac1 0x61>, <&dmac1 0x62>;
 539                 dma-names = "tx", "rx", "tx", "rx";
 540                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 541                 status = "disabled";
 542         };
 543
 544         iic1: i2c@e6510000 {
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
 548                              "renesas,rmobile-iic";
 549                 reg = <0 0xe6510000 0 0x425>;
 550                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 552                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 553                        <&dmac1 0x65>, <&dmac1 0x66>;
 554                 dma-names = "tx", "rx", "tx", "rx";
 555                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 556                 status = "disabled";
 557         };
 558
 559         iic2: i2c@e6520000 {
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
 563                              "renesas,rmobile-iic";
 564                 reg = <0 0xe6520000 0 0x425>;
 565                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 566                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 567                 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
 568                        <&dmac1 0x69>, <&dmac1 0x6a>;
 569                 dma-names = "tx", "rx", "tx", "rx";
 570                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 571                 status = "disabled";
 572         };
 573
 574         iic3: i2c@e60b0000 {
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
 578                              "renesas,rmobile-iic";
 579                 reg = <0 0xe60b0000 0 0x425>;
 580                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 581                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 582                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 583                        <&dmac1 0x77>, <&dmac1 0x78>;
 584                 dma-names = "tx", "rx", "tx", "rx";
 585                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 586                 status = "disabled";
 587         };
 588
 589         mmcif0: mmc@ee200000 {
 590                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 591                 reg = <0 0xee200000 0 0x80>;
 592                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 594                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 595                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 596                 dma-names = "tx", "rx", "tx", "rx";
 597                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 598                 reg-io-width = <4>;
 599                 status = "disabled";
 600                 max-frequency = <97500000>;
 601         };
 602
 603         mmcif1: mmc@ee220000 {
 604                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 605                 reg = <0 0xee220000 0 0x80>;
 606                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 607                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 608                 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
 609                        <&dmac1 0xe1>, <&dmac1 0xe2>;
 610                 dma-names = "tx", "rx", "tx", "rx";
 611                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 612                 reg-io-width = <4>;
 613                 status = "disabled";
 614                 max-frequency = <97500000>;
 615         };
 616
 617         pfc: pin-controller@e6060000 {
 618                 compatible = "renesas,pfc-r8a7790";
 619                 reg = <0 0xe6060000 0 0x250>;
 620         };
 621
 622         sdhi0: sd@ee100000 {
 623                 compatible = "renesas,sdhi-r8a7790";
 624                 reg = <0 0xee100000 0 0x328>;
 625                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 626                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 627                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 628                        <&dmac1 0xcd>, <&dmac1 0xce>;
 629                 dma-names = "tx", "rx", "tx", "rx";
 630                 max-frequency = <195000000>;
 631                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 632                 status = "disabled";
 633         };
 634
 635         sdhi1: sd@ee120000 {
 636                 compatible = "renesas,sdhi-r8a7790";
 637                 reg = <0 0xee120000 0 0x328>;
 638                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 640                 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
 641                        <&dmac1 0xc9>, <&dmac1 0xca>;
 642                 dma-names = "tx", "rx", "tx", "rx";
 643                 max-frequency = <195000000>;
 644                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 645                 status = "disabled";
 646         };
 647
 648         sdhi2: sd@ee140000 {
 649                 compatible = "renesas,sdhi-r8a7790";
 650                 reg = <0 0xee140000 0 0x100>;
 651                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 653                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 654                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 655                 dma-names = "tx", "rx", "tx", "rx";
 656                 max-frequency = <97500000>;
 657                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 658                 status = "disabled";
 659         };
 660
 661         sdhi3: sd@ee160000 {
 662                 compatible = "renesas,sdhi-r8a7790";
 663                 reg = <0 0xee160000 0 0x100>;
 664                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 666                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 667                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 668                 dma-names = "tx", "rx", "tx", "rx";
 669                 max-frequency = <97500000>;
 670                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 671                 status = "disabled";
 672         };
 673
 674         scifa0: serial@e6c40000 {
 675                 compatible = "renesas,scifa-r8a7790",
 676                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 677                 reg = <0 0xe6c40000 0 64>;
 678                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 679                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 680                 clock-names = "fck";
 681                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 682                        <&dmac1 0x21>, <&dmac1 0x22>;
 683                 dma-names = "tx", "rx", "tx", "rx";
 684                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 685                 status = "disabled";
 686         };
 687
 688         scifa1: serial@e6c50000 {
 689                 compatible = "renesas,scifa-r8a7790",
 690                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 691                 reg = <0 0xe6c50000 0 64>;
 692                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 693                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 694                 clock-names = "fck";
 695                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 696                        <&dmac1 0x25>, <&dmac1 0x26>;
 697                 dma-names = "tx", "rx", "tx", "rx";
 698                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 699                 status = "disabled";
 700         };
 701
 702         scifa2: serial@e6c60000 {
 703                 compatible = "renesas,scifa-r8a7790",
 704                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 705                 reg = <0 0xe6c60000 0 64>;
 706                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 708                 clock-names = "fck";
 709                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 710                        <&dmac1 0x27>, <&dmac1 0x28>;
 711                 dma-names = "tx", "rx", "tx", "rx";
 712                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 713                 status = "disabled";
 714         };
 715
 716         scifb0: serial@e6c20000 {
 717                 compatible = "renesas,scifb-r8a7790",
 718                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 719                 reg = <0 0xe6c20000 0 0x100>;
 720                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 722                 clock-names = "fck";
 723                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 724                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 725                 dma-names = "tx", "rx", "tx", "rx";
 726                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 727                 status = "disabled";
 728         };
 729
 730         scifb1: serial@e6c30000 {
 731                 compatible = "renesas,scifb-r8a7790",
 732                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 733                 reg = <0 0xe6c30000 0 0x100>;
 734                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 735                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 736                 clock-names = "fck";
 737                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 738                        <&dmac1 0x19>, <&dmac1 0x1a>;
 739                 dma-names = "tx", "rx", "tx", "rx";
 740                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 741                 status = "disabled";
 742         };
 743
 744         scifb2: serial@e6ce0000 {
 745                 compatible = "renesas,scifb-r8a7790",
 746                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 747                 reg = <0 0xe6ce0000 0 0x100>;
 748                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 750                 clock-names = "fck";
 751                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 752                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 753                 dma-names = "tx", "rx", "tx", "rx";
 754                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 755                 status = "disabled";
 756         };
 757
 758         scif0: serial@e6e60000 {
 759                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 760                              "renesas,scif";
 761                 reg = <0 0xe6e60000 0 64>;
 762                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 763                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
 764                          <&scif_clk>;
 765                 clock-names = "fck", "brg_int", "scif_clk";
 766                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 767                        <&dmac1 0x29>, <&dmac1 0x2a>;
 768                 dma-names = "tx", "rx", "tx", "rx";
 769                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 770                 status = "disabled";
 771         };
 772
 773         scif1: serial@e6e68000 {
 774                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 775                              "renesas,scif";
 776                 reg = <0 0xe6e68000 0 64>;
 777                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
 779                          <&scif_clk>;
 780                 clock-names = "fck", "brg_int", "scif_clk";
 781                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 782                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 783                 dma-names = "tx", "rx", "tx", "rx";
 784                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 785                 status = "disabled";
 786         };
 787
 788         scif2: serial@e6e56000 {
 789                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 790                              "renesas,scif";
 791                 reg = <0 0xe6e56000 0 64>;
 792                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
 794                          <&scif_clk>;
 795                 clock-names = "fck", "brg_int", "scif_clk";
 796                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 797                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 798                 dma-names = "tx", "rx", "tx", "rx";
 799                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 800                 status = "disabled";
 801         };
 802
 803         hscif0: serial@e62c0000 {
 804                 compatible = "renesas,hscif-r8a7790",
 805                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 806                 reg = <0 0xe62c0000 0 96>;
 807                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
 809                          <&scif_clk>;
 810                 clock-names = "fck", "brg_int", "scif_clk";
 811                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 812                        <&dmac1 0x39>, <&dmac1 0x3a>;
 813                 dma-names = "tx", "rx", "tx", "rx";
 814                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 815                 status = "disabled";
 816         };
 817
 818         hscif1: serial@e62c8000 {
 819                 compatible = "renesas,hscif-r8a7790",
 820                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 821                 reg = <0 0xe62c8000 0 96>;
 822                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 823                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
 824                          <&scif_clk>;
 825                 clock-names = "fck", "brg_int", "scif_clk";
 826                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 827                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 828                 dma-names = "tx", "rx", "tx", "rx";
 829                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 830                 status = "disabled";
 831         };
 832
 833         icram0: sram@e63a0000 {
 834                 compatible = "mmio-sram";
 835                 reg = <0 0xe63a0000 0 0x12000>;
 836         };
 837
 838         icram1: sram@e63c0000 {
 839                 compatible = "mmio-sram";
 840                 reg = <0 0xe63c0000 0 0x1000>;
 841                 #address-cells = <1>;
 842                 #size-cells = <1>;
 843                 ranges = <0 0 0xe63c0000 0x1000>;
 844
 845                 smp-sram@0 {
 846                         compatible = "renesas,smp-sram";
 847                         reg = <0 0x10>;
 848                 };
 849         };
 850
 851         ether: ethernet@ee700000 {
 852                 compatible = "renesas,ether-r8a7790";
 853                 reg = <0 0xee700000 0 0x400>;
 854                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 855                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 856                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 857                 phy-mode = "rmii";
 858                 #address-cells = <1>;
 859                 #size-cells = <0>;
 860                 status = "disabled";
 861         };
 862
 863         avb: ethernet@e6800000 {
 864                 compatible = "renesas,etheravb-r8a7790",
 865                              "renesas,etheravb-rcar-gen2";
 866                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 867                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 868                 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
 869                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 870                 #address-cells = <1>;
 871                 #size-cells = <0>;
 872                 status = "disabled";
 873         };
 874
 875         sata0: sata@ee300000 {
 876                 compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
 877                 reg = <0 0xee300000 0 0x2000>;
 878                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 879                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 880                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 881                 status = "disabled";
 882         };
 883
 884         sata1: sata@ee500000 {
 885                 compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
 886                 reg = <0 0xee500000 0 0x2000>;
 887                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 889                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 890                 status = "disabled";
 891         };
 892
 893         hsusb: usb@e6590000 {
 894                 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
 895                 reg = <0 0xe6590000 0 0x100>;
 896                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 898                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 899                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 900                 dma-names = "ch0", "ch1", "ch2", "ch3";
 901                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 902                 renesas,buswait = <4>;
 903                 phys = <&usb0 1>;
 904                 phy-names = "usb";
 905                 status = "disabled";
 906         };
 907
 908         usbphy: usb-phy@e6590100 {
 909                 compatible = "renesas,usb-phy-r8a7790",
 910                              "renesas,rcar-gen2-usb-phy";
 911                 reg = <0 0xe6590100 0 0x100>;
 912                 #address-cells = <1>;
 913                 #size-cells = <0>;
 914                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 915                 clock-names = "usbhs";
 916                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 917                 status = "disabled";
 918
 919                 usb0: usb-channel@0 {
 920                         reg = <0>;
 921                         #phy-cells = <1>;
 922                 };
 923                 usb2: usb-channel@2 {
 924                         reg = <2>;
 925                         #phy-cells = <1>;
 926                 };
 927         };
 928
 929         vin0: video@e6ef0000 {
 930                 compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
 931                 reg = <0 0xe6ef0000 0 0x1000>;
 932                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 933                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 934                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 935                 status = "disabled";
 936         };
 937
 938         vin1: video@e6ef1000 {
 939                 compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
 940                 reg = <0 0xe6ef1000 0 0x1000>;
 941                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 942                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 943                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 944                 status = "disabled";
 945         };
 946
 947         vin2: video@e6ef2000 {
 948                 compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
 949                 reg = <0 0xe6ef2000 0 0x1000>;
 950                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 951                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 952                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 953                 status = "disabled";
 954         };
 955
 956         vin3: video@e6ef3000 {
 957                 compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
 958                 reg = <0 0xe6ef3000 0 0x1000>;
 959                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 960                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 961                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 962                 status = "disabled";
 963         };
 964
 965         vsp1@fe920000 {
 966                 compatible = "renesas,vsp1";
 967                 reg = <0 0xfe920000 0 0x8000>;
 968                 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 969                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
 970                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 971         };
 972
 973         vsp1@fe928000 {
 974                 compatible = "renesas,vsp1";
 975                 reg = <0 0xfe928000 0 0x8000>;
 976                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 977                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
 978                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 979         };
 980
 981         vsp1@fe930000 {
 982                 compatible = "renesas,vsp1";
 983                 reg = <0 0xfe930000 0 0x8000>;
 984                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 985                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
 986                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 987         };
 988
 989         vsp1@fe938000 {
 990                 compatible = "renesas,vsp1";
 991                 reg = <0 0xfe938000 0 0x8000>;
 992                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 993                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
 994                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 995         };
 996
 997         du: display@feb00000 {
 998                 compatible = "renesas,du-r8a7790";
 999                 reg = <0 0xfeb00000 0 0x70000>,
1000                       <0 0xfeb90000 0 0x1c>,
1001                       <0 0xfeb94000 0 0x1c>;
1002                 reg-names = "du", "lvds.0", "lvds.1";
1003                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1004                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1005                              <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1006                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
1007                          <&mstp7_clks R8A7790_CLK_DU1>,
1008                          <&mstp7_clks R8A7790_CLK_DU2>,
1009                          <&mstp7_clks R8A7790_CLK_LVDS0>,
1010                          <&mstp7_clks R8A7790_CLK_LVDS1>;
1011                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
1012                 status = "disabled";
1013
1014                 ports {
1015                         #address-cells = <1>;
1016                         #size-cells = <0>;
1017
1018                         port@0 {
1019                                 reg = <0>;
1020                                 du_out_rgb: endpoint {
1021                                 };
1022                         };
1023                         port@1 {
1024                                 reg = <1>;
1025                                 du_out_lvds0: endpoint {
1026                                 };
1027                         };
1028                         port@2 {
1029                                 reg = <2>;
1030                                 du_out_lvds1: endpoint {
1031                                 };
1032                         };
1033                 };
1034         };
1035
1036         can0: can@e6e80000 {
1037                 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1038                 reg = <0 0xe6e80000 0 0x1000>;
1039                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1040                 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1041                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1042                 clock-names = "clkp1", "clkp2", "can_clk";
1043                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1044                 status = "disabled";
1045         };
1046
1047         can1: can@e6e88000 {
1048                 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1049                 reg = <0 0xe6e88000 0 0x1000>;
1050                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1051                 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1052                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1053                 clock-names = "clkp1", "clkp2", "can_clk";
1054                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1055                 status = "disabled";
1056         };
1057
1058         jpu: jpeg-codec@fe980000 {
1059                 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1060                 reg = <0 0xfe980000 0 0x10300>;
1061                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1062                 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1063                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1064         };
1065
1066         clocks {
1067                 #address-cells = <2>;
1068                 #size-cells = <2>;
1069                 ranges;
1070
1071                 /* External root clock */
1072                 extal_clk: extal {
1073                         compatible = "fixed-clock";
1074                         #clock-cells = <0>;
1075                         /* This value must be overriden by the board. */
1076                         clock-frequency = <0>;
1077                 };
1078
1079                 /* External PCIe clock - can be overridden by the board */
1080                 pcie_bus_clk: pcie_bus {
1081                         compatible = "fixed-clock";
1082                         #clock-cells = <0>;
1083                         clock-frequency = <0>;
1084                 };
1085
1086                 /*
1087                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1088                  * default. Boards that provide audio clocks should override them.
1089                  */
1090                 audio_clk_a: audio_clk_a {
1091                         compatible = "fixed-clock";
1092                         #clock-cells = <0>;
1093                         clock-frequency = <0>;
1094                 };
1095                 audio_clk_b: audio_clk_b {
1096                         compatible = "fixed-clock";
1097                         #clock-cells = <0>;
1098                         clock-frequency = <0>;
1099                 };
1100                 audio_clk_c: audio_clk_c {
1101                         compatible = "fixed-clock";
1102                         #clock-cells = <0>;
1103                         clock-frequency = <0>;
1104                 };
1105
1106                 /* External SCIF clock */
1107                 scif_clk: scif {
1108                         compatible = "fixed-clock";
1109                         #clock-cells = <0>;
1110                         /* This value must be overridden by the board. */
1111                         clock-frequency = <0>;
1112                 };
1113
1114                 /* External USB clock - can be overridden by the board */
1115                 usb_extal_clk: usb_extal {
1116                         compatible = "fixed-clock";
1117                         #clock-cells = <0>;
1118                         clock-frequency = <48000000>;
1119                 };
1120
1121                 /* External CAN clock */
1122                 can_clk: can {
1123                         compatible = "fixed-clock";
1124                         #clock-cells = <0>;
1125                         /* This value must be overridden by the board. */
1126                         clock-frequency = <0>;
1127                 };
1128
1129                 /* Special CPG clocks */
1130                 cpg_clocks: cpg_clocks@e6150000 {
1131                         compatible = "renesas,r8a7790-cpg-clocks",
1132                                      "renesas,rcar-gen2-cpg-clocks";
1133                         reg = <0 0xe6150000 0 0x1000>;
1134                         clocks = <&extal_clk &usb_extal_clk>;
1135                         #clock-cells = <1>;
1136                         clock-output-names = "main", "pll0", "pll1", "pll3",
1137                                              "lb", "qspi", "sdh", "sd0", "sd1",
1138                                              "z", "rcan", "adsp";
1139                         #power-domain-cells = <0>;
1140                 };
1141
1142                 /* Variable factor clocks */
1143                 sd2_clk: sd2@e6150078 {
1144                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1145                         reg = <0 0xe6150078 0 4>;
1146                         clocks = <&pll1_div2_clk>;
1147                         #clock-cells = <0>;
1148                 };
1149                 sd3_clk: sd3@e615026c {
1150                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1151                         reg = <0 0xe615026c 0 4>;
1152                         clocks = <&pll1_div2_clk>;
1153                         #clock-cells = <0>;
1154                 };
1155                 mmc0_clk: mmc0@e6150240 {
1156                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1157                         reg = <0 0xe6150240 0 4>;
1158                         clocks = <&pll1_div2_clk>;
1159                         #clock-cells = <0>;
1160                 };
1161                 mmc1_clk: mmc1@e6150244 {
1162                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1163                         reg = <0 0xe6150244 0 4>;
1164                         clocks = <&pll1_div2_clk>;
1165                         #clock-cells = <0>;
1166                 };
1167                 ssp_clk: ssp@e6150248 {
1168                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1169                         reg = <0 0xe6150248 0 4>;
1170                         clocks = <&pll1_div2_clk>;
1171                         #clock-cells = <0>;
1172                 };
1173                 ssprs_clk: ssprs@e615024c {
1174                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1175                         reg = <0 0xe615024c 0 4>;
1176                         clocks = <&pll1_div2_clk>;
1177                         #clock-cells = <0>;
1178                 };
1179
1180                 /* Fixed factor clocks */
1181                 pll1_div2_clk: pll1_div2 {
1182                         compatible = "fixed-factor-clock";
1183                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1184                         #clock-cells = <0>;
1185                         clock-div = <2>;
1186                         clock-mult = <1>;
1187                 };
1188                 z2_clk: z2 {
1189                         compatible = "fixed-factor-clock";
1190                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1191                         #clock-cells = <0>;
1192                         clock-div = <2>;
1193                         clock-mult = <1>;
1194                 };
1195                 zg_clk: zg {
1196                         compatible = "fixed-factor-clock";
1197                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198                         #clock-cells = <0>;
1199                         clock-div = <3>;
1200                         clock-mult = <1>;
1201                 };
1202                 zx_clk: zx {
1203                         compatible = "fixed-factor-clock";
1204                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1205                         #clock-cells = <0>;
1206                         clock-div = <3>;
1207                         clock-mult = <1>;
1208                 };
1209                 zs_clk: zs {
1210                         compatible = "fixed-factor-clock";
1211                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1212                         #clock-cells = <0>;
1213                         clock-div = <6>;
1214                         clock-mult = <1>;
1215                 };
1216                 hp_clk: hp {
1217                         compatible = "fixed-factor-clock";
1218                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1219                         #clock-cells = <0>;
1220                         clock-div = <12>;
1221                         clock-mult = <1>;
1222                 };
1223                 i_clk: i {
1224                         compatible = "fixed-factor-clock";
1225                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1226                         #clock-cells = <0>;
1227                         clock-div = <2>;
1228                         clock-mult = <1>;
1229                 };
1230                 b_clk: b {
1231                         compatible = "fixed-factor-clock";
1232                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1233                         #clock-cells = <0>;
1234                         clock-div = <12>;
1235                         clock-mult = <1>;
1236                 };
1237                 p_clk: p {
1238                         compatible = "fixed-factor-clock";
1239                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1240                         #clock-cells = <0>;
1241                         clock-div = <24>;
1242                         clock-mult = <1>;
1243                 };
1244                 cl_clk: cl {
1245                         compatible = "fixed-factor-clock";
1246                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1247                         #clock-cells = <0>;
1248                         clock-div = <48>;
1249                         clock-mult = <1>;
1250                 };
1251                 m2_clk: m2 {
1252                         compatible = "fixed-factor-clock";
1253                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1254                         #clock-cells = <0>;
1255                         clock-div = <8>;
1256                         clock-mult = <1>;
1257                 };
1258                 imp_clk: imp {
1259                         compatible = "fixed-factor-clock";
1260                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1261                         #clock-cells = <0>;
1262                         clock-div = <4>;
1263                         clock-mult = <1>;
1264                 };
1265                 rclk_clk: rclk {
1266                         compatible = "fixed-factor-clock";
1267                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1268                         #clock-cells = <0>;
1269                         clock-div = <(48 * 1024)>;
1270                         clock-mult = <1>;
1271                 };
1272                 oscclk_clk: oscclk {
1273                         compatible = "fixed-factor-clock";
1274                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1275                         #clock-cells = <0>;
1276                         clock-div = <(12 * 1024)>;
1277                         clock-mult = <1>;
1278                 };
1279                 zb3_clk: zb3 {
1280                         compatible = "fixed-factor-clock";
1281                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1282                         #clock-cells = <0>;
1283                         clock-div = <4>;
1284                         clock-mult = <1>;
1285                 };
1286                 zb3d2_clk: zb3d2 {
1287                         compatible = "fixed-factor-clock";
1288                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1289                         #clock-cells = <0>;
1290                         clock-div = <8>;
1291                         clock-mult = <1>;
1292                 };
1293                 ddr_clk: ddr {
1294                         compatible = "fixed-factor-clock";
1295                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1296                         #clock-cells = <0>;
1297                         clock-div = <8>;
1298                         clock-mult = <1>;
1299                 };
1300                 mp_clk: mp {
1301                         compatible = "fixed-factor-clock";
1302                         clocks = <&pll1_div2_clk>;
1303                         #clock-cells = <0>;
1304                         clock-div = <15>;
1305                         clock-mult = <1>;
1306                 };
1307                 cp_clk: cp {
1308                         compatible = "fixed-factor-clock";
1309                         clocks = <&extal_clk>;
1310                         #clock-cells = <0>;
1311                         clock-div = <2>;
1312                         clock-mult = <1>;
1313                 };
1314
1315                 /* Gate clocks */
1316                 mstp0_clks: mstp0_clks@e6150130 {
1317                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1318                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1319                         clocks = <&mp_clk>;
1320                         #clock-cells = <1>;
1321                         clock-indices = <R8A7790_CLK_MSIOF0>;
1322                         clock-output-names = "msiof0";
1323                 };
1324                 mstp1_clks: mstp1_clks@e6150134 {
1325                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1326                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1327                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1328                                  <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1329                                  <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1330                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1331                         #clock-cells = <1>;
1332                         clock-indices = <
1333                                 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1334                                 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1335                                 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1336                                 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1337                                 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1338                                 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1339                                 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1340                         >;
1341                         clock-output-names =
1342                                 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1343                                 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1344                                 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1345                                 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1346                 };
1347                 mstp2_clks: mstp2_clks@e6150138 {
1348                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1349                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1350                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1351                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1352                                  <&zs_clk>;
1353                         #clock-cells = <1>;
1354                         clock-indices = <
1355                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1356                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1357                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1358                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1359                         >;
1360                         clock-output-names =
1361                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1362                                 "scifb1", "msiof1", "msiof3", "scifb2",
1363                                 "sys-dmac1", "sys-dmac0";
1364                 };
1365                 mstp3_clks: mstp3_clks@e615013c {
1366                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1367                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1368                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1369                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1370                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1371                                  <&hp_clk>, <&hp_clk>;
1372                         #clock-cells = <1>;
1373                         clock-indices = <
1374                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1375                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1376                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1377                                 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1378                         >;
1379                         clock-output-names =
1380                                 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1381                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1382                                 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1383                                 "usbdmac0", "usbdmac1";
1384                 };
1385                 mstp4_clks: mstp4_clks@e6150140 {
1386                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1387                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1388                         clocks = <&cp_clk>, <&zs_clk>;
1389                         #clock-cells = <1>;
1390                         clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;
1391                         clock-output-names = "irqc", "intc-sys";
1392                 };
1393                 mstp5_clks: mstp5_clks@e6150144 {
1394                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1395                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1396                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1397                                  <&extal_clk>, <&p_clk>;
1398                         #clock-cells = <1>;
1399                         clock-indices = <
1400                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1401                                 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1402                                 R8A7790_CLK_PWM
1403                         >;
1404                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1405                                              "thermal", "pwm";
1406                 };
1407                 mstp7_clks: mstp7_clks@e615014c {
1408                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1409                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1410                         clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1411                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1412                                  <&zx_clk>;
1413                         #clock-cells = <1>;
1414                         clock-indices = <
1415                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1416                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1417                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1418                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1419                         >;
1420                         clock-output-names =
1421                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1422                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1423                 };
1424                 mstp8_clks: mstp8_clks@e6150990 {
1425                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1426                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1427                         clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1428                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1429                                  <&zs_clk>;
1430                         #clock-cells = <1>;
1431                         clock-indices = <
1432                                 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1433                                 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1434                                 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1435                                 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1436                         >;
1437                         clock-output-names =
1438                                 "mlb", "vin3", "vin2", "vin1", "vin0",
1439                                 "etheravb", "ether", "sata1", "sata0";
1440                 };
1441                 mstp9_clks: mstp9_clks@e6150994 {
1442                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1443                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1444                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1445                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1446                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1447                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1448                         #clock-cells = <1>;
1449                         clock-indices = <
1450                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1451                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1452                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1453                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1454                         >;
1455                         clock-output-names =
1456                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1457                                 "rcan1", "rcan0", "qspi_mod", "iic3",
1458                                 "i2c3", "i2c2", "i2c1", "i2c0";
1459                 };
1460                 mstp10_clks: mstp10_clks@e6150998 {
1461                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1462                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1463                         clocks = <&p_clk>,
1464                                 <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1465                                 <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1466                                 <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1467                                 <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1468                                 <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1469                                 <&p_clk>,
1470                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1471                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1472                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1473                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1474                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1475                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1476                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1477
1478                         #clock-cells = <1>;
1479                         clock-indices = <
1480                                 R8A7790_CLK_SSI_ALL
1481                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1482                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1483                                 R8A7790_CLK_SCU_ALL
1484                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1485                                 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1486                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1487                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1488                         >;
1489                         clock-output-names =
1490                                 "ssi-all",
1491                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1492                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1493                                 "scu-all",
1494                                 "scu-dvc1", "scu-dvc0",
1495                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1496                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1497                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1498                 };
1499         };
1500
1501         prr: chipid@ff000044 {
1502                 compatible = "renesas,prr";
1503                 reg = <0 0xff000044 0 4>;
1504         };
1505
1506         rst: reset-controller@e6160000 {
1507                 compatible = "renesas,r8a7790-rst";
1508                 reg = <0 0xe6160000 0 0x0100>;
1509         };
1510
1511         sysc: system-controller@e6180000 {
1512                 compatible = "renesas,r8a7790-sysc";
1513                 reg = <0 0xe6180000 0 0x0200>;
1514                 #power-domain-cells = <1>;
1515         };
1516
1517         qspi: spi@e6b10000 {
1518                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1519                 reg = <0 0xe6b10000 0 0x2c>;
1520                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1521                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1522                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1523                        <&dmac1 0x17>, <&dmac1 0x18>;
1524                 dma-names = "tx", "rx", "tx", "rx";
1525                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1526                 num-cs = <1>;
1527                 #address-cells = <1>;
1528                 #size-cells = <0>;
1529                 status = "disabled";
1530         };
1531
1532         msiof0: spi@e6e20000 {
1533                 compatible = "renesas,msiof-r8a7790",
1534                              "renesas,rcar-gen2-msiof";
1535                 reg = <0 0xe6e20000 0 0x0064>;
1536                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1537                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1538                 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1539                        <&dmac1 0x51>, <&dmac1 0x52>;
1540                 dma-names = "tx", "rx", "tx", "rx";
1541                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1542                 #address-cells = <1>;
1543                 #size-cells = <0>;
1544                 status = "disabled";
1545         };
1546
1547         msiof1: spi@e6e10000 {
1548                 compatible = "renesas,msiof-r8a7790",
1549                              "renesas,rcar-gen2-msiof";
1550                 reg = <0 0xe6e10000 0 0x0064>;
1551                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1552                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1553                 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1554                        <&dmac1 0x55>, <&dmac1 0x56>;
1555                 dma-names = "tx", "rx", "tx", "rx";
1556                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1557                 #address-cells = <1>;
1558                 #size-cells = <0>;
1559                 status = "disabled";
1560         };
1561
1562         msiof2: spi@e6e00000 {
1563                 compatible = "renesas,msiof-r8a7790",
1564                              "renesas,rcar-gen2-msiof";
1565                 reg = <0 0xe6e00000 0 0x0064>;
1566                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1567                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1568                 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1569                        <&dmac1 0x41>, <&dmac1 0x42>;
1570                 dma-names = "tx", "rx", "tx", "rx";
1571                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1572                 #address-cells = <1>;
1573                 #size-cells = <0>;
1574                 status = "disabled";
1575         };
1576
1577         msiof3: spi@e6c90000 {
1578                 compatible = "renesas,msiof-r8a7790",
1579                              "renesas,rcar-gen2-msiof";
1580                 reg = <0 0xe6c90000 0 0x0064>;
1581                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1582                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1583                 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1584                        <&dmac1 0x45>, <&dmac1 0x46>;
1585                 dma-names = "tx", "rx", "tx", "rx";
1586                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1587                 #address-cells = <1>;
1588                 #size-cells = <0>;
1589                 status = "disabled";
1590         };
1591
1592         xhci: usb@ee000000 {
1593                 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1594                 reg = <0 0xee000000 0 0xc00>;
1595                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1596                 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1597                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1598                 phys = <&usb2 1>;
1599                 phy-names = "usb";
1600                 status = "disabled";
1601         };
1602
1603         pci0: pci@ee090000 {
1604                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1605                 device_type = "pci";
1606                 reg = <0 0xee090000 0 0xc00>,
1607                       <0 0xee080000 0 0x1100>;
1608                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1610                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1611                 status = "disabled";
1612
1613                 bus-range = <0 0>;
1614                 #address-cells = <3>;
1615                 #size-cells = <2>;
1616                 #interrupt-cells = <1>;
1617                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1618                 interrupt-map-mask = <0xff00 0 0 0x7>;
1619                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1620                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1621                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1622
1623                 usb@1,0 {
1624                         reg = <0x800 0 0 0 0>;
1625                         phys = <&usb0 0>;
1626                         phy-names = "usb";
1627                 };
1628
1629                 usb@2,0 {
1630                         reg = <0x1000 0 0 0 0>;
1631                         phys = <&usb0 0>;
1632                         phy-names = "usb";
1633                 };
1634         };
1635
1636         pci1: pci@ee0b0000 {
1637                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1638                 device_type = "pci";
1639                 reg = <0 0xee0b0000 0 0xc00>,
1640                       <0 0xee0a0000 0 0x1100>;
1641                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1642                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1643                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1644                 status = "disabled";
1645
1646                 bus-range = <1 1>;
1647                 #address-cells = <3>;
1648                 #size-cells = <2>;
1649                 #interrupt-cells = <1>;
1650                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1651                 interrupt-map-mask = <0xff00 0 0 0x7>;
1652                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1653                                  0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1654                                  0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1655         };
1656
1657         pci2: pci@ee0d0000 {
1658                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1659                 device_type = "pci";
1660                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1661                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1662                 reg = <0 0xee0d0000 0 0xc00>,
1663                       <0 0xee0c0000 0 0x1100>;
1664                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1665                 status = "disabled";
1666
1667                 bus-range = <2 2>;
1668                 #address-cells = <3>;
1669                 #size-cells = <2>;
1670                 #interrupt-cells = <1>;
1671                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1672                 interrupt-map-mask = <0xff00 0 0 0x7>;
1673                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1674                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1675                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1676
1677                 usb@1,0 {
1678                         reg = <0x20800 0 0 0 0>;
1679                         phys = <&usb2 0>;
1680                         phy-names = "usb";
1681                 };
1682
1683                 usb@2,0 {
1684                         reg = <0x21000 0 0 0 0>;
1685                         phys = <&usb2 0>;
1686                         phy-names = "usb";
1687                 };
1688         };
1689
1690         pciec: pcie@fe000000 {
1691                 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1692                 reg = <0 0xfe000000 0 0x80000>;
1693                 #address-cells = <3>;
1694                 #size-cells = <2>;
1695                 bus-range = <0x00 0xff>;
1696                 device_type = "pci";
1697                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1698                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1699                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1700                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1701                 /* Map all possible DDR as inbound ranges */
1702                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1703                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1704                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1705                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1706                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1707                 #interrupt-cells = <1>;
1708                 interrupt-map-mask = <0 0 0 0>;
1709                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1710                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1711                 clock-names = "pcie", "pcie_bus";
1712                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1713                 status = "disabled";
1714         };
1715
1716         rcar_sound: sound@ec500000 {
1717                 /*
1718                  * #sound-dai-cells is required
1719                  *
1720                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1721                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1722                  */
1723                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1724                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1725                         <0 0xec5a0000 0 0x100>,  /* ADG */
1726                         <0 0xec540000 0 0x1000>, /* SSIU */
1727                         <0 0xec541000 0 0x280>,  /* SSI */
1728                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1729                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1730
1731                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1732                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1733                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1734                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1735                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1736                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1737                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1738                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1739                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1740                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1741                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1742                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1743                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1744                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1745                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1746                 clock-names = "ssi-all",
1747                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1748                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1749                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1750                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1751                                 "ctu.0", "ctu.1",
1752                                 "mix.0", "mix.1",
1753                                 "dvc.0", "dvc.1",
1754                                 "clk_a", "clk_b", "clk_c", "clk_i";
1755                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1756
1757                 status = "disabled";
1758
1759                 rcar_sound,dvc {
1760                         dvc0: dvc-0 {
1761                                 dmas = <&audma1 0xbc>;
1762                                 dma-names = "tx";
1763                         };
1764                         dvc1: dvc-1 {
1765                                 dmas = <&audma1 0xbe>;
1766                                 dma-names = "tx";
1767                         };
1768                 };
1769
1770                 rcar_sound,mix {
1771                         mix0: mix-0 { };
1772                         mix1: mix-1 { };
1773                 };
1774
1775                 rcar_sound,ctu {
1776                         ctu00: ctu-0 { };
1777                         ctu01: ctu-1 { };
1778                         ctu02: ctu-2 { };
1779                         ctu03: ctu-3 { };
1780                         ctu10: ctu-4 { };
1781                         ctu11: ctu-5 { };
1782                         ctu12: ctu-6 { };
1783                         ctu13: ctu-7 { };
1784                 };
1785
1786                 rcar_sound,src {
1787                         src0: src-0 {
1788                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1789                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1790                                 dma-names = "rx", "tx";
1791                         };
1792                         src1: src-1 {
1793                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1794                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1795                                 dma-names = "rx", "tx";
1796                         };
1797                         src2: src-2 {
1798                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1799                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1800                                 dma-names = "rx", "tx";
1801                         };
1802                         src3: src-3 {
1803                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1804                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1805                                 dma-names = "rx", "tx";
1806                         };
1807                         src4: src-4 {
1808                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1809                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1810                                 dma-names = "rx", "tx";
1811                         };
1812                         src5: src-5 {
1813                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1814                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1815                                 dma-names = "rx", "tx";
1816                         };
1817                         src6: src-6 {
1818                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1819                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1820                                 dma-names = "rx", "tx";
1821                         };
1822                         src7: src-7 {
1823                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1824                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1825                                 dma-names = "rx", "tx";
1826                         };
1827                         src8: src-8 {
1828                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1829                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1830                                 dma-names = "rx", "tx";
1831                         };
1832                         src9: src-9 {
1833                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1834                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1835                                 dma-names = "rx", "tx";
1836                         };
1837                 };
1838
1839                 rcar_sound,ssi {
1840                         ssi0: ssi-0 {
1841                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1842                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1843                                 dma-names = "rx", "tx", "rxu", "txu";
1844                         };
1845                         ssi1: ssi-1 {
1846                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1847                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1848                                 dma-names = "rx", "tx", "rxu", "txu";
1849                         };
1850                         ssi2: ssi-2 {
1851                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1852                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1853                                 dma-names = "rx", "tx", "rxu", "txu";
1854                         };
1855                         ssi3: ssi-3 {
1856                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1857                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1858                                 dma-names = "rx", "tx", "rxu", "txu";
1859                         };
1860                         ssi4: ssi-4 {
1861                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1862                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1863                                 dma-names = "rx", "tx", "rxu", "txu";
1864                         };
1865                         ssi5: ssi-5 {
1866                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1867                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1868                                 dma-names = "rx", "tx", "rxu", "txu";
1869                         };
1870                         ssi6: ssi-6 {
1871                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1872                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1873                                 dma-names = "rx", "tx", "rxu", "txu";
1874                         };
1875                         ssi7: ssi-7 {
1876                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1877                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1878                                 dma-names = "rx", "tx", "rxu", "txu";
1879                         };
1880                         ssi8: ssi-8 {
1881                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1882                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1883                                 dma-names = "rx", "tx", "rxu", "txu";
1884                         };
1885                         ssi9: ssi-9 {
1886                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1887                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1888                                 dma-names = "rx", "tx", "rxu", "txu";
1889                         };
1890                 };
1891         };
1892
1893         ipmmu_sy0: mmu@e6280000 {
1894                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1895                 reg = <0 0xe6280000 0 0x1000>;
1896                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1897                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1898                 #iommu-cells = <1>;
1899                 status = "disabled";
1900         };
1901
1902         ipmmu_sy1: mmu@e6290000 {
1903                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1904                 reg = <0 0xe6290000 0 0x1000>;
1905                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1906                 #iommu-cells = <1>;
1907                 status = "disabled";
1908         };
1909
1910         ipmmu_ds: mmu@e6740000 {
1911                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1912                 reg = <0 0xe6740000 0 0x1000>;
1913                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1914                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1915                 #iommu-cells = <1>;
1916                 status = "disabled";
1917         };
1918
1919         ipmmu_mp: mmu@ec680000 {
1920                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1921                 reg = <0 0xec680000 0 0x1000>;
1922                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1923                 #iommu-cells = <1>;
1924                 status = "disabled";
1925         };
1926
1927         ipmmu_mx: mmu@fe951000 {
1928                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1929                 reg = <0 0xfe951000 0 0x1000>;
1930                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1931                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1932                 #iommu-cells = <1>;
1933                 status = "disabled";
1934         };
1935
1936         ipmmu_rt: mmu@ffc80000 {
1937                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1938                 reg = <0 0xffc80000 0 0x1000>;
1939                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1940                 #iommu-cells = <1>;
1941                 status = "disabled";
1942         };
1943 };