arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /include/ "skeleton.dtsi"
  13
  14 #include <dt-bindings/clock/r8a7779-clock.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7779";
  19         interrupt-parent = <&gic>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <0>;
  29                         clock-frequency = <1000000000>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clock-frequency = <1000000000>;
  36                 };
  37                 cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <2>;
  41                         clock-frequency = <1000000000>;
  42                 };
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a9";
  46                         reg = <3>;
  47                         clock-frequency = <1000000000>;
  48                 };
  49         };
  50
  51         aliases {
  52                 spi0 = &hspi0;
  53                 spi1 = &hspi1;
  54                 spi2 = &hspi2;
  55         };
  56
  57         gic: interrupt-controller@f0001000 {
  58                 compatible = "arm,cortex-a9-gic";
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0xf0001000 0x1000>,
  62                       <0xf0000100 0x100>;
  63         };
  64
  65         gpio0: gpio@ffc40000 {
  66                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  67                 reg = <0xffc40000 0x2c>;
  68                 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
  69                 #gpio-cells = <2>;
  70                 gpio-controller;
  71                 gpio-ranges = <&pfc 0 0 32>;
  72                 #interrupt-cells = <2>;
  73                 interrupt-controller;
  74         };
  75
  76         gpio1: gpio@ffc41000 {
  77                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  78                 reg = <0xffc41000 0x2c>;
  79                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
  80                 #gpio-cells = <2>;
  81                 gpio-controller;
  82                 gpio-ranges = <&pfc 0 32 32>;
  83                 #interrupt-cells = <2>;
  84                 interrupt-controller;
  85         };
  86
  87         gpio2: gpio@ffc42000 {
  88                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  89                 reg = <0xffc42000 0x2c>;
  90                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
  91                 #gpio-cells = <2>;
  92                 gpio-controller;
  93                 gpio-ranges = <&pfc 0 64 32>;
  94                 #interrupt-cells = <2>;
  95                 interrupt-controller;
  96         };
  97
  98         gpio3: gpio@ffc43000 {
  99                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 100                 reg = <0xffc43000 0x2c>;
 101                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 102                 #gpio-cells = <2>;
 103                 gpio-controller;
 104                 gpio-ranges = <&pfc 0 96 32>;
 105                 #interrupt-cells = <2>;
 106                 interrupt-controller;
 107         };
 108
 109         gpio4: gpio@ffc44000 {
 110                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 111                 reg = <0xffc44000 0x2c>;
 112                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 113                 #gpio-cells = <2>;
 114                 gpio-controller;
 115                 gpio-ranges = <&pfc 0 128 32>;
 116                 #interrupt-cells = <2>;
 117                 interrupt-controller;
 118         };
 119
 120         gpio5: gpio@ffc45000 {
 121                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 122                 reg = <0xffc45000 0x2c>;
 123                 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 160 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129         };
 130
 131         gpio6: gpio@ffc46000 {
 132                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 133                 reg = <0xffc46000 0x2c>;
 134                 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 192 9>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140         };
 141
 142         irqpin0: irqpin@fe780010 {
 143                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 144                 #interrupt-cells = <2>;
 145                 status = "disabled";
 146                 interrupt-controller;
 147                 reg = <0xfe78001c 4>,
 148                         <0xfe780010 4>,
 149                         <0xfe780024 4>,
 150                         <0xfe780044 4>,
 151                         <0xfe780064 4>;
 152                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
 153                               0 28 IRQ_TYPE_LEVEL_HIGH
 154                               0 29 IRQ_TYPE_LEVEL_HIGH
 155                               0 30 IRQ_TYPE_LEVEL_HIGH>;
 156                 sense-bitfield-width = <2>;
 157         };
 158
 159         i2c0: i2c@ffc70000 {
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162                 compatible = "renesas,i2c-r8a7779";
 163                 reg = <0xffc70000 0x1000>;
 164                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 165                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 166                 status = "disabled";
 167         };
 168
 169         i2c1: i2c@ffc71000 {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172                 compatible = "renesas,i2c-r8a7779";
 173                 reg = <0xffc71000 0x1000>;
 174                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 176                 status = "disabled";
 177         };
 178
 179         i2c2: i2c@ffc72000 {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 compatible = "renesas,i2c-r8a7779";
 183                 reg = <0xffc72000 0x1000>;
 184                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 186                 status = "disabled";
 187         };
 188
 189         i2c3: i2c@ffc73000 {
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 compatible = "renesas,i2c-r8a7779";
 193                 reg = <0xffc73000 0x1000>;
 194                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 196                 status = "disabled";
 197         };
 198
 199         scif0: serial@ffe40000 {
 200                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 201                 reg = <0xffe40000 0x100>;
 202                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 204                 clock-names = "sci_ick";
 205                 status = "disabled";
 206         };
 207
 208         scif1: serial@ffe41000 {
 209                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 210                 reg = <0xffe41000 0x100>;
 211                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 213                 clock-names = "sci_ick";
 214                 status = "disabled";
 215         };
 216
 217         scif2: serial@ffe42000 {
 218                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 219                 reg = <0xffe42000 0x100>;
 220                 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 222                 clock-names = "sci_ick";
 223                 status = "disabled";
 224         };
 225
 226         scif3: serial@ffe43000 {
 227                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 228                 reg = <0xffe43000 0x100>;
 229                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 231                 clock-names = "sci_ick";
 232                 status = "disabled";
 233         };
 234
 235         scif4: serial@ffe44000 {
 236                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 237                 reg = <0xffe44000 0x100>;
 238                 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 240                 clock-names = "sci_ick";
 241                 status = "disabled";
 242         };
 243
 244         scif5: serial@ffe45000 {
 245                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 246                 reg = <0xffe45000 0x100>;
 247                 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&cpg_clocks R8A7779_CLK_P>;
 249                 clock-names = "sci_ick";
 250                 status = "disabled";
 251         };
 252
 253         pfc: pfc@fffc0000 {
 254                 compatible = "renesas,pfc-r8a7779";
 255                 reg = <0xfffc0000 0x23c>;
 256         };
 257
 258         thermal@ffc48000 {
 259                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 260                 reg = <0xffc48000 0x38>;
 261         };
 262
 263         tmu0: timer@ffd80000 {
 264                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 265                 reg = <0xffd80000 0x30>;
 266                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 267                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 268                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 270                 clock-names = "fck";
 271
 272                 #renesas,channels = <3>;
 273
 274                 status = "disabled";
 275         };
 276
 277         tmu1: timer@ffd81000 {
 278                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 279                 reg = <0xffd81000 0x30>;
 280                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 281                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 282                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 284                 clock-names = "fck";
 285
 286                 #renesas,channels = <3>;
 287
 288                 status = "disabled";
 289         };
 290
 291         tmu2: timer@ffd82000 {
 292                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 293                 reg = <0xffd82000 0x30>;
 294                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 295                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 296                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 298                 clock-names = "fck";
 299
 300                 #renesas,channels = <3>;
 301
 302                 status = "disabled";
 303         };
 304
 305         sata: sata@fc600000 {
 306                 compatible = "renesas,rcar-sata";
 307                 reg = <0xfc600000 0x2000>;
 308                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 310         };
 311
 312         sdhi0: sd@ffe4c000 {
 313                 compatible = "renesas,sdhi-r8a7779";
 314                 reg = <0xffe4c000 0x100>;
 315                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 317                 cap-sd-highspeed;
 318                 cap-sdio-irq;
 319                 status = "disabled";
 320         };
 321
 322         sdhi1: sd@ffe4d000 {
 323                 compatible = "renesas,sdhi-r8a7779";
 324                 reg = <0xffe4d000 0x100>;
 325                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 327                 cap-sd-highspeed;
 328                 cap-sdio-irq;
 329                 status = "disabled";
 330         };
 331
 332         sdhi2: sd@ffe4e000 {
 333                 compatible = "renesas,sdhi-r8a7779";
 334                 reg = <0xffe4e000 0x100>;
 335                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 337                 cap-sd-highspeed;
 338                 cap-sdio-irq;
 339                 status = "disabled";
 340         };
 341
 342         sdhi3: sd@ffe4f000 {
 343                 compatible = "renesas,sdhi-r8a7779";
 344                 reg = <0xffe4f000 0x100>;
 345                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 347                 cap-sd-highspeed;
 348                 cap-sdio-irq;
 349                 status = "disabled";
 350         };
 351
 352         hspi0: spi@fffc7000 {
 353                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 354                 reg = <0xfffc7000 0x18>;
 355                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 359                 status = "disabled";
 360         };
 361
 362         hspi1: spi@fffc8000 {
 363                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 364                 reg = <0xfffc8000 0x18>;
 365                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 369                 status = "disabled";
 370         };
 371
 372         hspi2: spi@fffc6000 {
 373                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 374                 reg = <0xfffc6000 0x18>;
 375                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 379                 status = "disabled";
 380         };
 381
 382         clocks {
 383                 #address-cells = <1>;
 384                 #size-cells = <1>;
 385                 ranges;
 386
 387                 /* External root clock */
 388                 extal_clk: extal_clk {
 389                         compatible = "fixed-clock";
 390                         #clock-cells = <0>;
 391                         /* This value must be overriden by the board. */
 392                         clock-frequency = <0>;
 393                         clock-output-names = "extal";
 394                 };
 395
 396                 /* Special CPG clocks */
 397                 cpg_clocks: clocks@ffc80000 {
 398                         compatible = "renesas,r8a7779-cpg-clocks";
 399                         reg = <0xffc80000 0x30>;
 400                         clocks = <&extal_clk>;
 401                         #clock-cells = <1>;
 402                         clock-output-names = "plla", "z", "zs", "s",
 403                                              "s1", "p", "b", "out";
 404                 };
 405
 406                 /* Fixed factor clocks */
 407                 i_clk: i_clk {
 408                         compatible = "fixed-factor-clock";
 409                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 410                         #clock-cells = <0>;
 411                         clock-div = <2>;
 412                         clock-mult = <1>;
 413                         clock-output-names = "i";
 414                 };
 415                 s3_clk: s3_clk {
 416                         compatible = "fixed-factor-clock";
 417                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 418                         #clock-cells = <0>;
 419                         clock-div = <8>;
 420                         clock-mult = <1>;
 421                         clock-output-names = "s3";
 422                 };
 423                 s4_clk: s4_clk {
 424                         compatible = "fixed-factor-clock";
 425                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 426                         #clock-cells = <0>;
 427                         clock-div = <16>;
 428                         clock-mult = <1>;
 429                         clock-output-names = "s4";
 430                 };
 431                 g_clk: g_clk {
 432                         compatible = "fixed-factor-clock";
 433                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 434                         #clock-cells = <0>;
 435                         clock-div = <24>;
 436                         clock-mult = <1>;
 437                         clock-output-names = "g";
 438                 };
 439
 440                 /* Gate clocks */
 441                 mstp0_clks: clocks@ffc80030 {
 442                         compatible = "renesas,r8a7779-mstp-clocks",
 443                                      "renesas,cpg-mstp-clocks";
 444                         reg = <0xffc80030 4>;
 445                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 446                                  <&cpg_clocks R8A7779_CLK_P>,
 447                                  <&cpg_clocks R8A7779_CLK_P>,
 448                                  <&cpg_clocks R8A7779_CLK_P>,
 449                                  <&cpg_clocks R8A7779_CLK_S>,
 450                                  <&cpg_clocks R8A7779_CLK_S>,
 451                                  <&cpg_clocks R8A7779_CLK_S1>,
 452                                  <&cpg_clocks R8A7779_CLK_S1>,
 453                                  <&cpg_clocks R8A7779_CLK_S1>,
 454                                  <&cpg_clocks R8A7779_CLK_S1>,
 455                                  <&cpg_clocks R8A7779_CLK_S1>,
 456                                  <&cpg_clocks R8A7779_CLK_S1>,
 457                                  <&cpg_clocks R8A7779_CLK_P>,
 458                                  <&cpg_clocks R8A7779_CLK_P>,
 459                                  <&cpg_clocks R8A7779_CLK_P>,
 460                                  <&cpg_clocks R8A7779_CLK_P>;
 461                         #clock-cells = <1>;
 462                         renesas,clock-indices = <
 463                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 464                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 465                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 466                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 467                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 468                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 469                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 470                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 471                         >;
 472                         clock-output-names =
 473                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 474                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 475                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 476                                 "i2c0";
 477                 };
 478                 mstp1_clks: clocks@ffc80034 {
 479                         compatible = "renesas,r8a7779-mstp-clocks",
 480                                      "renesas,cpg-mstp-clocks";
 481                         reg = <0xffc80034 4>, <0xffc80044 4>;
 482                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 483                                  <&cpg_clocks R8A7779_CLK_P>,
 484                                  <&cpg_clocks R8A7779_CLK_S>,
 485                                  <&cpg_clocks R8A7779_CLK_S>,
 486                                  <&cpg_clocks R8A7779_CLK_S>,
 487                                  <&cpg_clocks R8A7779_CLK_S>,
 488                                  <&cpg_clocks R8A7779_CLK_P>,
 489                                  <&cpg_clocks R8A7779_CLK_P>,
 490                                  <&cpg_clocks R8A7779_CLK_P>,
 491                                  <&cpg_clocks R8A7779_CLK_S>;
 492                         #clock-cells = <1>;
 493                         renesas,clock-indices = <
 494                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 495                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 496                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 497                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 498                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 499                         >;
 500                         clock-output-names =
 501                                 "usb01", "usb2",
 502                                 "du", "vin2",
 503                                 "vin1", "vin0",
 504                                 "ether", "sata",
 505                                 "pcie", "vin3";
 506                 };
 507                 mstp3_clks: clocks@ffc8003c {
 508                         compatible = "renesas,r8a7779-mstp-clocks",
 509                                      "renesas,cpg-mstp-clocks";
 510                         reg = <0xffc8003c 4>;
 511                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 512                                  <&s4_clk>, <&s4_clk>;
 513                         #clock-cells = <1>;
 514                         renesas,clock-indices = <
 515                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 516                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 517                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 518                         >;
 519                         clock-output-names =
 520                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 521                                 "mmc1", "mmc0";
 522                 };
 523         };
 524 };