arch/arm/boot/dts/r8a7779.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for Renesas r8a7779
   4  *
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  * Copyright (C) 2013 Simon Horman
   7  */
   8
   9 #include <dt-bindings/clock/r8a7779-clock.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/power/r8a7779-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a7779";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         reg = <0>;
  28                         clock-frequency = <1000000000>;
  29                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clock-frequency = <1000000000>;
  36                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  37                         power-domains = <&sysc R8A7779_PD_ARM1>;
  38                 };
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <2>;
  43                         clock-frequency = <1000000000>;
  44                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  45                         power-domains = <&sysc R8A7779_PD_ARM2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <3>;
  51                         clock-frequency = <1000000000>;
  52                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  53                         power-domains = <&sysc R8A7779_PD_ARM3>;
  54                 };
  55         };
  56
  57         aliases {
  58                 spi0 = &hspi0;
  59                 spi1 = &hspi1;
  60                 spi2 = &hspi2;
  61         };
  62
  63         gic: interrupt-controller@f0001000 {
  64                 compatible = "arm,cortex-a9-gic";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xf0001000 0x1000>,
  68                       <0xf0000100 0x100>;
  69         };
  70
  71         timer@f0000600 {
  72                 compatible = "arm,cortex-a9-twd-timer";
  73                 reg = <0xf0000600 0x20>;
  74                 interrupts = <GIC_PPI 13
  75                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  76                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  77         };
  78
  79         gpio0: gpio@ffc40000 {
  80                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
  81                 reg = <0xffc40000 0x2c>;
  82                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  83                 #gpio-cells = <2>;
  84                 gpio-controller;
  85                 gpio-ranges = <&pfc 0 0 32>;
  86                 #interrupt-cells = <2>;
  87                 interrupt-controller;
  88         };
  89
  90         gpio1: gpio@ffc41000 {
  91                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
  92                 reg = <0xffc41000 0x2c>;
  93                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
  94                 #gpio-cells = <2>;
  95                 gpio-controller;
  96                 gpio-ranges = <&pfc 0 32 32>;
  97                 #interrupt-cells = <2>;
  98                 interrupt-controller;
  99         };
 100
 101         gpio2: gpio@ffc42000 {
 102                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 103                 reg = <0xffc42000 0x2c>;
 104                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 105                 #gpio-cells = <2>;
 106                 gpio-controller;
 107                 gpio-ranges = <&pfc 0 64 32>;
 108                 #interrupt-cells = <2>;
 109                 interrupt-controller;
 110         };
 111
 112         gpio3: gpio@ffc43000 {
 113                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 114                 reg = <0xffc43000 0x2c>;
 115                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 96 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121         };
 122
 123         gpio4: gpio@ffc44000 {
 124                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 125                 reg = <0xffc44000 0x2c>;
 126                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 127                 #gpio-cells = <2>;
 128                 gpio-controller;
 129                 gpio-ranges = <&pfc 0 128 32>;
 130                 #interrupt-cells = <2>;
 131                 interrupt-controller;
 132         };
 133
 134         gpio5: gpio@ffc45000 {
 135                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 136                 reg = <0xffc45000 0x2c>;
 137                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 160 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143         };
 144
 145         gpio6: gpio@ffc46000 {
 146                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 147                 reg = <0xffc46000 0x2c>;
 148                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 192 9>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154         };
 155
 156         irqpin0: interrupt-controller@fe78001c {
 157                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 158                 #interrupt-cells = <2>;
 159                 status = "disabled";
 160                 interrupt-controller;
 161                 reg = <0xfe78001c 4>,
 162                         <0xfe780010 4>,
 163                         <0xfe780024 4>,
 164                         <0xfe780044 4>,
 165                         <0xfe780064 4>,
 166                         <0xfe780000 4>;
 167                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
 168                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
 169                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
 170                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 171                 sense-bitfield-width = <2>;
 172         };
 173
 174         i2c0: i2c@ffc70000 {
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 178                 reg = <0xffc70000 0x1000>;
 179                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 180                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 181                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 182                 status = "disabled";
 183         };
 184
 185         i2c1: i2c@ffc71000 {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 189                 reg = <0xffc71000 0x1000>;
 190                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 191                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 192                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 193                 status = "disabled";
 194         };
 195
 196         i2c2: i2c@ffc72000 {
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 200                 reg = <0xffc72000 0x1000>;
 201                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 203                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 204                 status = "disabled";
 205         };
 206
 207         i2c3: i2c@ffc73000 {
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 211                 reg = <0xffc73000 0x1000>;
 212                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 214                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 215                 status = "disabled";
 216         };
 217
 218         scif0: serial@ffe40000 {
 219                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 220                              "renesas,scif";
 221                 reg = <0xffe40000 0x100>;
 222                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
 224                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 225                 clock-names = "fck", "brg_int", "scif_clk";
 226                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 227                 status = "disabled";
 228         };
 229
 230         scif1: serial@ffe41000 {
 231                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 232                              "renesas,scif";
 233                 reg = <0xffe41000 0x100>;
 234                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
 236                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 237                 clock-names = "fck", "brg_int", "scif_clk";
 238                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 239                 status = "disabled";
 240         };
 241
 242         scif2: serial@ffe42000 {
 243                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 244                              "renesas,scif";
 245                 reg = <0xffe42000 0x100>;
 246                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
 248                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 249                 clock-names = "fck", "brg_int", "scif_clk";
 250                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 251                 status = "disabled";
 252         };
 253
 254         scif3: serial@ffe43000 {
 255                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 256                              "renesas,scif";
 257                 reg = <0xffe43000 0x100>;
 258                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
 260                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 261                 clock-names = "fck", "brg_int", "scif_clk";
 262                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 263                 status = "disabled";
 264         };
 265
 266         scif4: serial@ffe44000 {
 267                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 268                              "renesas,scif";
 269                 reg = <0xffe44000 0x100>;
 270                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
 272                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 273                 clock-names = "fck", "brg_int", "scif_clk";
 274                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 275                 status = "disabled";
 276         };
 277
 278         scif5: serial@ffe45000 {
 279                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 280                              "renesas,scif";
 281                 reg = <0xffe45000 0x100>;
 282                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
 284                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 285                 clock-names = "fck", "brg_int", "scif_clk";
 286                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 287                 status = "disabled";
 288         };
 289
 290         pfc: pin-controller@fffc0000 {
 291                 compatible = "renesas,pfc-r8a7779";
 292                 reg = <0xfffc0000 0x23c>;
 293         };
 294
 295         thermal@ffc48000 {
 296                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 297                 reg = <0xffc48000 0x38>;
 298         };
 299
 300         tmu0: timer@ffd80000 {
 301                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 302                 reg = <0xffd80000 0x30>;
 303                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 307                 clock-names = "fck";
 308                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 309
 310                 #renesas,channels = <3>;
 311
 312                 status = "disabled";
 313         };
 314
 315         tmu1: timer@ffd81000 {
 316                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 317                 reg = <0xffd81000 0x30>;
 318                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 322                 clock-names = "fck";
 323                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 324
 325                 #renesas,channels = <3>;
 326
 327                 status = "disabled";
 328         };
 329
 330         tmu2: timer@ffd82000 {
 331                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 332                 reg = <0xffd82000 0x30>;
 333                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 337                 clock-names = "fck";
 338                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 339
 340                 #renesas,channels = <3>;
 341
 342                 status = "disabled";
 343         };
 344
 345         sata: sata@fc600000 {
 346                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 347                 reg = <0xfc600000 0x2000>;
 348                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 350                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 351                 status = "disabled";
 352         };
 353
 354         sdhi0: sd@ffe4c000 {
 355                 compatible = "renesas,sdhi-r8a7779",
 356                              "renesas,rcar-gen1-sdhi";
 357                 reg = <0xffe4c000 0x100>;
 358                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 360                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 361                 status = "disabled";
 362         };
 363
 364         sdhi1: sd@ffe4d000 {
 365                 compatible = "renesas,sdhi-r8a7779",
 366                              "renesas,rcar-gen1-sdhi";
 367                 reg = <0xffe4d000 0x100>;
 368                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 370                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 371                 status = "disabled";
 372         };
 373
 374         sdhi2: sd@ffe4e000 {
 375                 compatible = "renesas,sdhi-r8a7779",
 376                              "renesas,rcar-gen1-sdhi";
 377                 reg = <0xffe4e000 0x100>;
 378                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 380                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 381                 status = "disabled";
 382         };
 383
 384         sdhi3: sd@ffe4f000 {
 385                 compatible = "renesas,sdhi-r8a7779",
 386                              "renesas,rcar-gen1-sdhi";
 387                 reg = <0xffe4f000 0x100>;
 388                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 390                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 391                 status = "disabled";
 392         };
 393
 394         hspi0: spi@fffc7000 {
 395                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 396                 reg = <0xfffc7000 0x18>;
 397                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 401                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 402                 status = "disabled";
 403         };
 404
 405         hspi1: spi@fffc8000 {
 406                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 407                 reg = <0xfffc8000 0x18>;
 408                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 412                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 413                 status = "disabled";
 414         };
 415
 416         hspi2: spi@fffc6000 {
 417                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 418                 reg = <0xfffc6000 0x18>;
 419                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 423                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 424                 status = "disabled";
 425         };
 426
 427         du: display@fff80000 {
 428                 compatible = "renesas,du-r8a7779";
 429                 reg = <0xfff80000 0x40000>;
 430                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 432                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 433                 status = "disabled";
 434
 435                 ports {
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438
 439                         port@0 {
 440                                 reg = <0>;
 441                                 du_out_rgb0: endpoint {
 442                                 };
 443                         };
 444                         port@1 {
 445                                 reg = <1>;
 446                                 du_out_rgb1: endpoint {
 447                                 };
 448                         };
 449                 };
 450         };
 451
 452         clocks {
 453                 #address-cells = <1>;
 454                 #size-cells = <1>;
 455                 ranges;
 456
 457                 /* External root clock */
 458                 extal_clk: extal {
 459                         compatible = "fixed-clock";
 460                         #clock-cells = <0>;
 461                         /* This value must be overriden by the board. */
 462                         clock-frequency = <0>;
 463                 };
 464
 465                 /* External SCIF clock */
 466                 scif_clk: scif {
 467                         compatible = "fixed-clock";
 468                         #clock-cells = <0>;
 469                         /* This value must be overridden by the board. */
 470                         clock-frequency = <0>;
 471                 };
 472
 473                 /* Special CPG clocks */
 474                 cpg_clocks: clocks@ffc80000 {
 475                         compatible = "renesas,r8a7779-cpg-clocks";
 476                         reg = <0xffc80000 0x30>;
 477                         clocks = <&extal_clk>;
 478                         #clock-cells = <1>;
 479                         clock-output-names = "plla", "z", "zs", "s",
 480                                              "s1", "p", "b", "out";
 481                         #power-domain-cells = <0>;
 482                 };
 483
 484                 /* Fixed factor clocks */
 485                 i_clk: i {
 486                         compatible = "fixed-factor-clock";
 487                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 488                         #clock-cells = <0>;
 489                         clock-div = <2>;
 490                         clock-mult = <1>;
 491                 };
 492                 s3_clk: s3 {
 493                         compatible = "fixed-factor-clock";
 494                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 495                         #clock-cells = <0>;
 496                         clock-div = <8>;
 497                         clock-mult = <1>;
 498                 };
 499                 s4_clk: s4 {
 500                         compatible = "fixed-factor-clock";
 501                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 502                         #clock-cells = <0>;
 503                         clock-div = <16>;
 504                         clock-mult = <1>;
 505                 };
 506                 g_clk: g {
 507                         compatible = "fixed-factor-clock";
 508                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 509                         #clock-cells = <0>;
 510                         clock-div = <24>;
 511                         clock-mult = <1>;
 512                 };
 513
 514                 /* Gate clocks */
 515                 mstp0_clks: clocks@ffc80030 {
 516                         compatible = "renesas,r8a7779-mstp-clocks",
 517                                      "renesas,cpg-mstp-clocks";
 518                         reg = <0xffc80030 4>;
 519                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 520                                  <&cpg_clocks R8A7779_CLK_P>,
 521                                  <&cpg_clocks R8A7779_CLK_P>,
 522                                  <&cpg_clocks R8A7779_CLK_P>,
 523                                  <&cpg_clocks R8A7779_CLK_S>,
 524                                  <&cpg_clocks R8A7779_CLK_S>,
 525                                  <&cpg_clocks R8A7779_CLK_P>,
 526                                  <&cpg_clocks R8A7779_CLK_P>,
 527                                  <&cpg_clocks R8A7779_CLK_P>,
 528                                  <&cpg_clocks R8A7779_CLK_P>,
 529                                  <&cpg_clocks R8A7779_CLK_P>,
 530                                  <&cpg_clocks R8A7779_CLK_P>,
 531                                  <&cpg_clocks R8A7779_CLK_P>,
 532                                  <&cpg_clocks R8A7779_CLK_P>,
 533                                  <&cpg_clocks R8A7779_CLK_P>,
 534                                  <&cpg_clocks R8A7779_CLK_P>;
 535                         #clock-cells = <1>;
 536                         clock-indices = <
 537                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 538                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 539                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 540                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 541                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 542                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 543                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 544                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 545                         >;
 546                         clock-output-names =
 547                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 548                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 549                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 550                                 "i2c0";
 551                 };
 552                 mstp1_clks: clocks@ffc80034 {
 553                         compatible = "renesas,r8a7779-mstp-clocks",
 554                                      "renesas,cpg-mstp-clocks";
 555                         reg = <0xffc80034 4>, <0xffc80044 4>;
 556                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 557                                  <&cpg_clocks R8A7779_CLK_P>,
 558                                  <&cpg_clocks R8A7779_CLK_S>,
 559                                  <&cpg_clocks R8A7779_CLK_S>,
 560                                  <&cpg_clocks R8A7779_CLK_S>,
 561                                  <&cpg_clocks R8A7779_CLK_S>,
 562                                  <&cpg_clocks R8A7779_CLK_P>,
 563                                  <&cpg_clocks R8A7779_CLK_P>,
 564                                  <&cpg_clocks R8A7779_CLK_P>,
 565                                  <&cpg_clocks R8A7779_CLK_S>;
 566                         #clock-cells = <1>;
 567                         clock-indices = <
 568                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 569                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 570                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 571                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 572                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 573                         >;
 574                         clock-output-names =
 575                                 "usb01", "usb2",
 576                                 "du", "vin2",
 577                                 "vin1", "vin0",
 578                                 "ether", "sata",
 579                                 "pcie", "vin3";
 580                 };
 581                 mstp3_clks: clocks@ffc8003c {
 582                         compatible = "renesas,r8a7779-mstp-clocks",
 583                                      "renesas,cpg-mstp-clocks";
 584                         reg = <0xffc8003c 4>;
 585                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 586                                  <&s4_clk>, <&s4_clk>;
 587                         #clock-cells = <1>;
 588                         clock-indices = <
 589                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 590                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 591                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 592                         >;
 593                         clock-output-names =
 594                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 595                                 "mmc1", "mmc0";
 596                 };
 597         };
 598
 599         prr: chipid@ff000044 {
 600                 compatible = "renesas,prr";
 601                 reg = <0xff000044 4>;
 602         };
 603
 604         rst: reset-controller@ffcc0000 {
 605                 compatible = "renesas,r8a7779-reset-wdt";
 606                 reg = <0xffcc0000 0x48>;
 607         };
 608
 609         sysc: system-controller@ffd85000 {
 610                 compatible = "renesas,r8a7779-sysc";
 611                 reg = <0xffd85000 0x0200>;
 612                 #power-domain-cells = <1>;
 613         };
 614 };