arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21 #include <dt-bindings/interrupt-controller/irq.h>
  22
  23 / {
  24         compatible = "renesas,r8a7778";
  25         interrupt-parent = <&gic>;
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <0>;
  35                         clock-frequency = <800000000>;
  36                 };
  37         };
  38
  39         aliases {
  40                 spi0 = &hspi0;
  41                 spi1 = &hspi1;
  42                 spi2 = &hspi2;
  43         };
  44
  45         bsc: bus@1c000000 {
  46                 compatible = "simple-bus";
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 ranges = <0 0 0x1c000000>;
  50         };
  51
  52         ether: ethernet@fde00000 {
  53                 compatible = "renesas,ether-r8a7778";
  54                 reg = <0xfde00000 0x400>;
  55                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  56                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  57                 power-domains = <&cpg_clocks>;
  58                 phy-mode = "rmii";
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61                 status = "disabled";
  62         };
  63
  64         gic: interrupt-controller@fe438000 {
  65                 compatible = "arm,pl390";
  66                 #interrupt-cells = <3>;
  67                 interrupt-controller;
  68                 reg = <0xfe438000 0x1000>,
  69                       <0xfe430000 0x100>;
  70         };
  71
  72         /* irqpin: IRQ0 - IRQ3 */
  73         irqpin: interrupt-controller@fe78001c {
  74                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  75                 #interrupt-cells = <2>;
  76                 interrupt-controller;
  77                 status = "disabled"; /* default off */
  78                 reg =   <0xfe78001c 4>,
  79                         <0xfe780010 4>,
  80                         <0xfe780024 4>,
  81                         <0xfe780044 4>,
  82                         <0xfe780064 4>;
  83                 interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
  84                                 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
  85                                 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
  86                                 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  87                 sense-bitfield-width = <2>;
  88         };
  89
  90         gpio0: gpio@ffc40000 {
  91                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  92                 reg = <0xffc40000 0x2c>;
  93                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  94                 #gpio-cells = <2>;
  95                 gpio-controller;
  96                 gpio-ranges = <&pfc 0 0 32>;
  97                 #interrupt-cells = <2>;
  98                 interrupt-controller;
  99         };
 100
 101         gpio1: gpio@ffc41000 {
 102                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 103                 reg = <0xffc41000 0x2c>;
 104                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 105                 #gpio-cells = <2>;
 106                 gpio-controller;
 107                 gpio-ranges = <&pfc 0 32 32>;
 108                 #interrupt-cells = <2>;
 109                 interrupt-controller;
 110         };
 111
 112         gpio2: gpio@ffc42000 {
 113                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 114                 reg = <0xffc42000 0x2c>;
 115                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 64 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121         };
 122
 123         gpio3: gpio@ffc43000 {
 124                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 125                 reg = <0xffc43000 0x2c>;
 126                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 127                 #gpio-cells = <2>;
 128                 gpio-controller;
 129                 gpio-ranges = <&pfc 0 96 32>;
 130                 #interrupt-cells = <2>;
 131                 interrupt-controller;
 132         };
 133
 134         gpio4: gpio@ffc44000 {
 135                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 136                 reg = <0xffc44000 0x2c>;
 137                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 128 27>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143         };
 144
 145         pfc: pfc@fffc0000 {
 146                 compatible = "renesas,pfc-r8a7778";
 147                 reg = <0xfffc0000 0x118>;
 148         };
 149
 150         i2c0: i2c@ffc70000 {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 compatible = "renesas,i2c-r8a7778";
 154                 reg = <0xffc70000 0x1000>;
 155                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 157                 power-domains = <&cpg_clocks>;
 158                 status = "disabled";
 159         };
 160
 161         i2c1: i2c@ffc71000 {
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 compatible = "renesas,i2c-r8a7778";
 165                 reg = <0xffc71000 0x1000>;
 166                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 167                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 168                 power-domains = <&cpg_clocks>;
 169                 status = "disabled";
 170         };
 171
 172         i2c2: i2c@ffc72000 {
 173                 #address-cells = <1>;
 174                 #size-cells = <0>;
 175                 compatible = "renesas,i2c-r8a7778";
 176                 reg = <0xffc72000 0x1000>;
 177                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 179                 power-domains = <&cpg_clocks>;
 180                 status = "disabled";
 181         };
 182
 183         i2c3: i2c@ffc73000 {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 compatible = "renesas,i2c-r8a7778";
 187                 reg = <0xffc73000 0x1000>;
 188                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 190                 power-domains = <&cpg_clocks>;
 191                 status = "disabled";
 192         };
 193
 194         tmu0: timer@ffd80000 {
 195                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 196                 reg = <0xffd80000 0x30>;
 197                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 201                 clock-names = "fck";
 202                 power-domains = <&cpg_clocks>;
 203
 204                 #renesas,channels = <3>;
 205
 206                 status = "disabled";
 207         };
 208
 209         tmu1: timer@ffd81000 {
 210                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 211                 reg = <0xffd81000 0x30>;
 212                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 216                 clock-names = "fck";
 217                 power-domains = <&cpg_clocks>;
 218
 219                 #renesas,channels = <3>;
 220
 221                 status = "disabled";
 222         };
 223
 224         tmu2: timer@ffd82000 {
 225                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 226                 reg = <0xffd82000 0x30>;
 227                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 231                 clock-names = "fck";
 232                 power-domains = <&cpg_clocks>;
 233
 234                 #renesas,channels = <3>;
 235
 236                 status = "disabled";
 237         };
 238
 239         rcar_sound: sound@ffd90000 {
 240                 /*
 241                  * #sound-dai-cells is required
 242                  *
 243                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 244                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 245                  */
 246                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 247                 reg =   <0xffd90000 0x1000>,    /* SRU */
 248                         <0xffd91000 0x240>,     /* SSI */
 249                         <0xfffe0000 0x24>;      /* ADG */
 250                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 251                         <&mstp3_clks R8A7778_CLK_SSI7>,
 252                         <&mstp3_clks R8A7778_CLK_SSI6>,
 253                         <&mstp3_clks R8A7778_CLK_SSI5>,
 254                         <&mstp3_clks R8A7778_CLK_SSI4>,
 255                         <&mstp0_clks R8A7778_CLK_SSI3>,
 256                         <&mstp0_clks R8A7778_CLK_SSI2>,
 257                         <&mstp0_clks R8A7778_CLK_SSI1>,
 258                         <&mstp0_clks R8A7778_CLK_SSI0>,
 259                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 260                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 261                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 267                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 268                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 269                         <&cpg_clocks R8A7778_CLK_S1>;
 270                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 271                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 272                         "src.8", "src.7", "src.6", "src.5", "src.4",
 273                         "src.3", "src.2", "src.1", "src.0",
 274                         "clk_a", "clk_b", "clk_c", "clk_i";
 275
 276                 status = "disabled";
 277
 278                 rcar_sound,src {
 279                         src3: src@3 { };
 280                         src4: src@4 { };
 281                         src5: src@5 { };
 282                         src6: src@6 { };
 283                         src7: src@7 { };
 284                         src8: src@8 { };
 285                         src9: src@9 { };
 286                 };
 287
 288                 rcar_sound,ssi {
 289                         ssi3: ssi@3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 290                         ssi4: ssi@4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 291                         ssi5: ssi@5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 292                         ssi6: ssi@6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi7: ssi@7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi8: ssi@8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                         ssi9: ssi@9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 296                 };
 297         };
 298
 299         scif0: serial@ffe40000 {
 300                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 301                              "renesas,scif";
 302                 reg = <0xffe40000 0x100>;
 303                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
 305                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 306                 clock-names = "fck", "brg_int", "scif_clk";
 307                 power-domains = <&cpg_clocks>;
 308                 status = "disabled";
 309         };
 310
 311         scif1: serial@ffe41000 {
 312                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 313                              "renesas,scif";
 314                 reg = <0xffe41000 0x100>;
 315                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
 317                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 318                 clock-names = "fck", "brg_int", "scif_clk";
 319                 power-domains = <&cpg_clocks>;
 320                 status = "disabled";
 321         };
 322
 323         scif2: serial@ffe42000 {
 324                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 325                              "renesas,scif";
 326                 reg = <0xffe42000 0x100>;
 327                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
 329                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 330                 clock-names = "fck", "brg_int", "scif_clk";
 331                 power-domains = <&cpg_clocks>;
 332                 status = "disabled";
 333         };
 334
 335         scif3: serial@ffe43000 {
 336                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 337                              "renesas,scif";
 338                 reg = <0xffe43000 0x100>;
 339                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
 341                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 342                 clock-names = "fck", "brg_int", "scif_clk";
 343                 power-domains = <&cpg_clocks>;
 344                 status = "disabled";
 345         };
 346
 347         scif4: serial@ffe44000 {
 348                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 349                              "renesas,scif";
 350                 reg = <0xffe44000 0x100>;
 351                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
 353                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 354                 clock-names = "fck", "brg_int", "scif_clk";
 355                 power-domains = <&cpg_clocks>;
 356                 status = "disabled";
 357         };
 358
 359         scif5: serial@ffe45000 {
 360                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 361                              "renesas,scif";
 362                 reg = <0xffe45000 0x100>;
 363                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
 365                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 366                 clock-names = "fck", "brg_int", "scif_clk";
 367                 power-domains = <&cpg_clocks>;
 368                 status = "disabled";
 369         };
 370
 371         mmcif: mmc@ffe4e000 {
 372                 compatible = "renesas,sh-mmcif";
 373                 reg = <0xffe4e000 0x100>;
 374                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 376                 power-domains = <&cpg_clocks>;
 377                 status = "disabled";
 378         };
 379
 380         sdhi0: sd@ffe4c000 {
 381                 compatible = "renesas,sdhi-r8a7778";
 382                 reg = <0xffe4c000 0x100>;
 383                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 385                 power-domains = <&cpg_clocks>;
 386                 status = "disabled";
 387         };
 388
 389         sdhi1: sd@ffe4d000 {
 390                 compatible = "renesas,sdhi-r8a7778";
 391                 reg = <0xffe4d000 0x100>;
 392                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 394                 power-domains = <&cpg_clocks>;
 395                 status = "disabled";
 396         };
 397
 398         sdhi2: sd@ffe4f000 {
 399                 compatible = "renesas,sdhi-r8a7778";
 400                 reg = <0xffe4f000 0x100>;
 401                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 403                 power-domains = <&cpg_clocks>;
 404                 status = "disabled";
 405         };
 406
 407         hspi0: spi@fffc7000 {
 408                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 409                 reg = <0xfffc7000 0x18>;
 410                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 412                 power-domains = <&cpg_clocks>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 status = "disabled";
 416         };
 417
 418         hspi1: spi@fffc8000 {
 419                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 420                 reg = <0xfffc8000 0x18>;
 421                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 423                 power-domains = <&cpg_clocks>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 status = "disabled";
 427         };
 428
 429         hspi2: spi@fffc6000 {
 430                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 431                 reg = <0xfffc6000 0x18>;
 432                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 434                 power-domains = <&cpg_clocks>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 status = "disabled";
 438         };
 439
 440         clocks {
 441                 #address-cells = <1>;
 442                 #size-cells = <1>;
 443                 ranges;
 444
 445                 /* External input clock */
 446                 extal_clk: extal_clk {
 447                         compatible = "fixed-clock";
 448                         #clock-cells = <0>;
 449                         clock-frequency = <0>;
 450                         clock-output-names = "extal";
 451                 };
 452
 453                 /* External SCIF clock */
 454                 scif_clk: scif {
 455                         compatible = "fixed-clock";
 456                         #clock-cells = <0>;
 457                         /* This value must be overridden by the board. */
 458                         clock-frequency = <0>;
 459                         status = "disabled";
 460                 };
 461
 462                 /* Special CPG clocks */
 463                 cpg_clocks: cpg_clocks@ffc80000 {
 464                         compatible = "renesas,r8a7778-cpg-clocks";
 465                         reg = <0xffc80000 0x80>;
 466                         #clock-cells = <1>;
 467                         clocks = <&extal_clk>;
 468                         clock-output-names = "plla", "pllb", "b",
 469                                              "out", "p", "s", "s1";
 470                         #power-domain-cells = <0>;
 471                 };
 472
 473                 /* Audio clocks; frequencies are set by boards if applicable. */
 474                 audio_clk_a: audio_clk_a {
 475                         compatible = "fixed-clock";
 476                         #clock-cells = <0>;
 477                         clock-output-names = "audio_clk_a";
 478                 };
 479                 audio_clk_b: audio_clk_b {
 480                         compatible = "fixed-clock";
 481                         #clock-cells = <0>;
 482                         clock-output-names = "audio_clk_b";
 483                 };
 484                 audio_clk_c: audio_clk_c {
 485                         compatible = "fixed-clock";
 486                         #clock-cells = <0>;
 487                         clock-output-names = "audio_clk_c";
 488                 };
 489
 490                 /* Fixed ratio clocks */
 491                 g_clk: g_clk {
 492                         compatible = "fixed-factor-clock";
 493                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 494                         #clock-cells = <0>;
 495                         clock-div = <12>;
 496                         clock-mult = <1>;
 497                         clock-output-names = "g";
 498                 };
 499                 i_clk: i_clk {
 500                         compatible = "fixed-factor-clock";
 501                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 502                         #clock-cells = <0>;
 503                         clock-div = <1>;
 504                         clock-mult = <1>;
 505                         clock-output-names = "i";
 506                 };
 507                 s3_clk: s3_clk {
 508                         compatible = "fixed-factor-clock";
 509                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 510                         #clock-cells = <0>;
 511                         clock-div = <4>;
 512                         clock-mult = <1>;
 513                         clock-output-names = "s3";
 514                 };
 515                 s4_clk: s4_clk {
 516                         compatible = "fixed-factor-clock";
 517                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 518                         #clock-cells = <0>;
 519                         clock-div = <8>;
 520                         clock-mult = <1>;
 521                         clock-output-names = "s4";
 522                 };
 523                 z_clk: z_clk {
 524                         compatible = "fixed-factor-clock";
 525                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 526                         #clock-cells = <0>;
 527                         clock-div = <1>;
 528                         clock-mult = <1>;
 529                         clock-output-names = "z";
 530                 };
 531
 532                 /* Gate clocks */
 533                 mstp0_clks: mstp0_clks@ffc80030 {
 534                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 535                         reg = <0xffc80030 4>;
 536                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 537                                  <&cpg_clocks R8A7778_CLK_P>,
 538                                  <&cpg_clocks R8A7778_CLK_P>,
 539                                  <&cpg_clocks R8A7778_CLK_P>,
 540                                  <&cpg_clocks R8A7778_CLK_P>,
 541                                  <&cpg_clocks R8A7778_CLK_P>,
 542                                  <&cpg_clocks R8A7778_CLK_P>,
 543                                  <&cpg_clocks R8A7778_CLK_P>,
 544                                  <&cpg_clocks R8A7778_CLK_P>,
 545                                  <&cpg_clocks R8A7778_CLK_P>,
 546                                  <&cpg_clocks R8A7778_CLK_P>,
 547                                  <&cpg_clocks R8A7778_CLK_P>,
 548                                  <&cpg_clocks R8A7778_CLK_P>,
 549                                  <&cpg_clocks R8A7778_CLK_P>,
 550                                  <&cpg_clocks R8A7778_CLK_P>,
 551                                  <&cpg_clocks R8A7778_CLK_P>,
 552                                  <&cpg_clocks R8A7778_CLK_P>,
 553                                  <&cpg_clocks R8A7778_CLK_P>,
 554                                  <&cpg_clocks R8A7778_CLK_S>;
 555                         #clock-cells = <1>;
 556                         clock-indices = <
 557                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 558                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 559                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 560                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 561                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 562                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 563                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 564                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 565                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 566                                 R8A7778_CLK_HSPI
 567                         >;
 568                         clock-output-names =
 569                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 570                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 571                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 572                                 "ssi2", "ssi3", "sru", "hspi";
 573                 };
 574                 mstp1_clks: mstp1_clks@ffc80034 {
 575                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 576                         reg = <0xffc80034 4>, <0xffc80044 4>;
 577                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 578                                  <&cpg_clocks R8A7778_CLK_S>,
 579                                  <&cpg_clocks R8A7778_CLK_S>,
 580                                  <&cpg_clocks R8A7778_CLK_P>;
 581                         #clock-cells = <1>;
 582                         clock-indices = <
 583                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 584                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 585                         >;
 586                         clock-output-names =
 587                                 "ether", "vin0", "vin1", "usb";
 588                 };
 589                 mstp3_clks: mstp3_clks@ffc8003c {
 590                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 591                         reg = <0xffc8003c 4>;
 592                         clocks = <&s4_clk>,
 593                                  <&cpg_clocks R8A7778_CLK_P>,
 594                                  <&cpg_clocks R8A7778_CLK_P>,
 595                                  <&cpg_clocks R8A7778_CLK_P>,
 596                                  <&cpg_clocks R8A7778_CLK_P>,
 597                                  <&cpg_clocks R8A7778_CLK_P>,
 598                                  <&cpg_clocks R8A7778_CLK_P>,
 599                                  <&cpg_clocks R8A7778_CLK_P>,
 600                                  <&cpg_clocks R8A7778_CLK_P>;
 601                         #clock-cells = <1>;
 602                         clock-indices = <
 603                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 604                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 605                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 606                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 607                                 R8A7778_CLK_SSI8
 608                         >;
 609                         clock-output-names =
 610                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 611                                 "ssi5", "ssi6", "ssi7", "ssi8";
 612                 };
 613                 mstp5_clks: mstp5_clks@ffc80054 {
 614                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 615                         reg = <0xffc80054 4>;
 616                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 617                                  <&cpg_clocks R8A7778_CLK_P>,
 618                                  <&cpg_clocks R8A7778_CLK_P>,
 619                                  <&cpg_clocks R8A7778_CLK_P>,
 620                                  <&cpg_clocks R8A7778_CLK_P>,
 621                                  <&cpg_clocks R8A7778_CLK_P>,
 622                                  <&cpg_clocks R8A7778_CLK_P>,
 623                                  <&cpg_clocks R8A7778_CLK_P>,
 624                                  <&cpg_clocks R8A7778_CLK_P>;
 625                         #clock-cells = <1>;
 626                         clock-indices = <
 627                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 628                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 629                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 630                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 631                                 R8A7778_CLK_SRU_SRC8
 632                         >;
 633                         clock-output-names =
 634                                 "sru-src0", "sru-src1", "sru-src2",
 635                                 "sru-src3", "sru-src4", "sru-src5",
 636                                 "sru-src6", "sru-src7", "sru-src8";
 637                 };
 638         };
 639 };