arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /include/ "skeleton.dtsi"
  18
  19 #include <dt-bindings/clock/r8a7778-clock.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "renesas,r8a7778";
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                         clock-frequency = <800000000>;
  35                 };
  36         };
  37
  38         aliases {
  39                 spi0 = &hspi0;
  40                 spi1 = &hspi1;
  41                 spi2 = &hspi2;
  42         };
  43
  44         bsc: bus@1c000000 {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0 0 0x1c000000>;
  49         };
  50
  51         ether: ethernet@fde00000 {
  52                 compatible = "renesas,ether-r8a7778";
  53                 reg = <0xfde00000 0x400>;
  54                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  56                 power-domains = <&cpg_clocks>;
  57                 phy-mode = "rmii";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 status = "disabled";
  61         };
  62
  63         gic: interrupt-controller@fe438000 {
  64                 compatible = "arm,pl390";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xfe438000 0x1000>,
  68                       <0xfe430000 0x100>;
  69         };
  70
  71         /* irqpin: IRQ0 - IRQ3 */
  72         irqpin: interrupt-controller@fe78001c {
  73                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  74                 #interrupt-cells = <2>;
  75                 interrupt-controller;
  76                 status = "disabled"; /* default off */
  77                 reg =   <0xfe78001c 4>,
  78                         <0xfe780010 4>,
  79                         <0xfe780024 4>,
  80                         <0xfe780044 4>,
  81                         <0xfe780064 4>;
  82                 interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
  83                                 0 28 IRQ_TYPE_LEVEL_HIGH
  84                                 0 29 IRQ_TYPE_LEVEL_HIGH
  85                                 0 30 IRQ_TYPE_LEVEL_HIGH>;
  86                 sense-bitfield-width = <2>;
  87         };
  88
  89         gpio0: gpio@ffc40000 {
  90                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  91                 reg = <0xffc40000 0x2c>;
  92                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  93                 #gpio-cells = <2>;
  94                 gpio-controller;
  95                 gpio-ranges = <&pfc 0 0 32>;
  96                 #interrupt-cells = <2>;
  97                 interrupt-controller;
  98         };
  99
 100         gpio1: gpio@ffc41000 {
 101                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 102                 reg = <0xffc41000 0x2c>;
 103                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 104                 #gpio-cells = <2>;
 105                 gpio-controller;
 106                 gpio-ranges = <&pfc 0 32 32>;
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109         };
 110
 111         gpio2: gpio@ffc42000 {
 112                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 113                 reg = <0xffc42000 0x2c>;
 114                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 64 32>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120         };
 121
 122         gpio3: gpio@ffc43000 {
 123                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 124                 reg = <0xffc43000 0x2c>;
 125                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 96 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131         };
 132
 133         gpio4: gpio@ffc44000 {
 134                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 135                 reg = <0xffc44000 0x2c>;
 136                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 gpio-ranges = <&pfc 0 128 27>;
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142         };
 143
 144         pfc: pfc@fffc0000 {
 145                 compatible = "renesas,pfc-r8a7778";
 146                 reg = <0xfffc0000 0x118>;
 147         };
 148
 149         i2c0: i2c@ffc70000 {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "renesas,i2c-r8a7778";
 153                 reg = <0xffc70000 0x1000>;
 154                 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 155                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 156                 power-domains = <&cpg_clocks>;
 157                 status = "disabled";
 158         };
 159
 160         i2c1: i2c@ffc71000 {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 compatible = "renesas,i2c-r8a7778";
 164                 reg = <0xffc71000 0x1000>;
 165                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 167                 power-domains = <&cpg_clocks>;
 168                 status = "disabled";
 169         };
 170
 171         i2c2: i2c@ffc72000 {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 compatible = "renesas,i2c-r8a7778";
 175                 reg = <0xffc72000 0x1000>;
 176                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 178                 power-domains = <&cpg_clocks>;
 179                 status = "disabled";
 180         };
 181
 182         i2c3: i2c@ffc73000 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,i2c-r8a7778";
 186                 reg = <0xffc73000 0x1000>;
 187                 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 189                 power-domains = <&cpg_clocks>;
 190                 status = "disabled";
 191         };
 192
 193         tmu0: timer@ffd80000 {
 194                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 195                 reg = <0xffd80000 0x30>;
 196                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 197                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 198                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 200                 clock-names = "fck";
 201                 power-domains = <&cpg_clocks>;
 202
 203                 #renesas,channels = <3>;
 204
 205                 status = "disabled";
 206         };
 207
 208         tmu1: timer@ffd81000 {
 209                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 210                 reg = <0xffd81000 0x30>;
 211                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 215                 clock-names = "fck";
 216                 power-domains = <&cpg_clocks>;
 217
 218                 #renesas,channels = <3>;
 219
 220                 status = "disabled";
 221         };
 222
 223         tmu2: timer@ffd82000 {
 224                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 225                 reg = <0xffd82000 0x30>;
 226                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 227                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 228                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 230                 clock-names = "fck";
 231                 power-domains = <&cpg_clocks>;
 232
 233                 #renesas,channels = <3>;
 234
 235                 status = "disabled";
 236         };
 237
 238         rcar_sound: sound@ffd90000 {
 239                 /*
 240                  * #sound-dai-cells is required
 241                  *
 242                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 243                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 244                  */
 245                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 246                 reg =   <0xffd90000 0x1000>,    /* SRU */
 247                         <0xffd91000 0x240>,     /* SSI */
 248                         <0xfffe0000 0x24>;      /* ADG */
 249                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 250                         <&mstp3_clks R8A7778_CLK_SSI7>,
 251                         <&mstp3_clks R8A7778_CLK_SSI6>,
 252                         <&mstp3_clks R8A7778_CLK_SSI5>,
 253                         <&mstp3_clks R8A7778_CLK_SSI4>,
 254                         <&mstp0_clks R8A7778_CLK_SSI3>,
 255                         <&mstp0_clks R8A7778_CLK_SSI2>,
 256                         <&mstp0_clks R8A7778_CLK_SSI1>,
 257                         <&mstp0_clks R8A7778_CLK_SSI0>,
 258                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 259                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 260                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 261                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 267                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 268                         <&cpg_clocks R8A7778_CLK_S1>;
 269                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 270                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 271                         "src.8", "src.7", "src.6", "src.5", "src.4",
 272                         "src.3", "src.2", "src.1", "src.0",
 273                         "clk_a", "clk_b", "clk_c", "clk_i";
 274
 275                 status = "disabled";
 276
 277                 rcar_sound,src {
 278                         src3: src@3 { };
 279                         src4: src@4 { };
 280                         src5: src@5 { };
 281                         src6: src@6 { };
 282                         src7: src@7 { };
 283                         src8: src@8 { };
 284                         src9: src@9 { };
 285                 };
 286
 287                 rcar_sound,ssi {
 288                         ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 289                         ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 290                         ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 291                         ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 292                         ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                 };
 296         };
 297
 298         scif0: serial@ffe40000 {
 299                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 300                 reg = <0xffe40000 0x100>;
 301                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
 303                 clock-names = "sci_ick";
 304                 power-domains = <&cpg_clocks>;
 305                 status = "disabled";
 306         };
 307
 308         scif1: serial@ffe41000 {
 309                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 310                 reg = <0xffe41000 0x100>;
 311                 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
 313                 clock-names = "sci_ick";
 314                 power-domains = <&cpg_clocks>;
 315                 status = "disabled";
 316         };
 317
 318         scif2: serial@ffe42000 {
 319                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 320                 reg = <0xffe42000 0x100>;
 321                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
 323                 clock-names = "sci_ick";
 324                 power-domains = <&cpg_clocks>;
 325                 status = "disabled";
 326         };
 327
 328         scif3: serial@ffe43000 {
 329                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 330                 reg = <0xffe43000 0x100>;
 331                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
 333                 clock-names = "sci_ick";
 334                 power-domains = <&cpg_clocks>;
 335                 status = "disabled";
 336         };
 337
 338         scif4: serial@ffe44000 {
 339                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 340                 reg = <0xffe44000 0x100>;
 341                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
 343                 clock-names = "sci_ick";
 344                 power-domains = <&cpg_clocks>;
 345                 status = "disabled";
 346         };
 347
 348         scif5: serial@ffe45000 {
 349                 compatible = "renesas,scif-r8a7778", "renesas,scif";
 350                 reg = <0xffe45000 0x100>;
 351                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
 353                 clock-names = "sci_ick";
 354                 power-domains = <&cpg_clocks>;
 355                 status = "disabled";
 356         };
 357
 358         mmcif: mmc@ffe4e000 {
 359                 compatible = "renesas,sh-mmcif";
 360                 reg = <0xffe4e000 0x100>;
 361                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 363                 power-domains = <&cpg_clocks>;
 364                 status = "disabled";
 365         };
 366
 367         sdhi0: sd@ffe4c000 {
 368                 compatible = "renesas,sdhi-r8a7778";
 369                 reg = <0xffe4c000 0x100>;
 370                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 372                 power-domains = <&cpg_clocks>;
 373                 status = "disabled";
 374         };
 375
 376         sdhi1: sd@ffe4d000 {
 377                 compatible = "renesas,sdhi-r8a7778";
 378                 reg = <0xffe4d000 0x100>;
 379                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 381                 power-domains = <&cpg_clocks>;
 382                 status = "disabled";
 383         };
 384
 385         sdhi2: sd@ffe4f000 {
 386                 compatible = "renesas,sdhi-r8a7778";
 387                 reg = <0xffe4f000 0x100>;
 388                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 390                 power-domains = <&cpg_clocks>;
 391                 status = "disabled";
 392         };
 393
 394         hspi0: spi@fffc7000 {
 395                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 396                 reg = <0xfffc7000 0x18>;
 397                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 399                 power-domains = <&cpg_clocks>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 status = "disabled";
 403         };
 404
 405         hspi1: spi@fffc8000 {
 406                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 407                 reg = <0xfffc8000 0x18>;
 408                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 410                 power-domains = <&cpg_clocks>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 status = "disabled";
 414         };
 415
 416         hspi2: spi@fffc6000 {
 417                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 418                 reg = <0xfffc6000 0x18>;
 419                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 421                 power-domains = <&cpg_clocks>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 status = "disabled";
 425         };
 426
 427         clocks {
 428                 #address-cells = <1>;
 429                 #size-cells = <1>;
 430                 ranges;
 431
 432                 /* External input clock */
 433                 extal_clk: extal_clk {
 434                         compatible = "fixed-clock";
 435                         #clock-cells = <0>;
 436                         clock-frequency = <0>;
 437                         clock-output-names = "extal";
 438                 };
 439
 440                 /* Special CPG clocks */
 441                 cpg_clocks: cpg_clocks@ffc80000 {
 442                         compatible = "renesas,r8a7778-cpg-clocks";
 443                         reg = <0xffc80000 0x80>;
 444                         #clock-cells = <1>;
 445                         clocks = <&extal_clk>;
 446                         clock-output-names = "plla", "pllb", "b",
 447                                              "out", "p", "s", "s1";
 448                         #power-domain-cells = <0>;
 449                 };
 450
 451                 /* Audio clocks; frequencies are set by boards if applicable. */
 452                 audio_clk_a: audio_clk_a {
 453                         compatible = "fixed-clock";
 454                         #clock-cells = <0>;
 455                         clock-output-names = "audio_clk_a";
 456                 };
 457                 audio_clk_b: audio_clk_b {
 458                         compatible = "fixed-clock";
 459                         #clock-cells = <0>;
 460                         clock-output-names = "audio_clk_b";
 461                 };
 462                 audio_clk_c: audio_clk_c {
 463                         compatible = "fixed-clock";
 464                         #clock-cells = <0>;
 465                         clock-output-names = "audio_clk_c";
 466                 };
 467
 468                 /* Fixed ratio clocks */
 469                 g_clk: g_clk {
 470                         compatible = "fixed-factor-clock";
 471                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 472                         #clock-cells = <0>;
 473                         clock-div = <12>;
 474                         clock-mult = <1>;
 475                         clock-output-names = "g";
 476                 };
 477                 i_clk: i_clk {
 478                         compatible = "fixed-factor-clock";
 479                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 480                         #clock-cells = <0>;
 481                         clock-div = <1>;
 482                         clock-mult = <1>;
 483                         clock-output-names = "i";
 484                 };
 485                 s3_clk: s3_clk {
 486                         compatible = "fixed-factor-clock";
 487                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 488                         #clock-cells = <0>;
 489                         clock-div = <4>;
 490                         clock-mult = <1>;
 491                         clock-output-names = "s3";
 492                 };
 493                 s4_clk: s4_clk {
 494                         compatible = "fixed-factor-clock";
 495                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 496                         #clock-cells = <0>;
 497                         clock-div = <8>;
 498                         clock-mult = <1>;
 499                         clock-output-names = "s4";
 500                 };
 501                 z_clk: z_clk {
 502                         compatible = "fixed-factor-clock";
 503                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 504                         #clock-cells = <0>;
 505                         clock-div = <1>;
 506                         clock-mult = <1>;
 507                         clock-output-names = "z";
 508                 };
 509
 510                 /* Gate clocks */
 511                 mstp0_clks: mstp0_clks@ffc80030 {
 512                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 513                         reg = <0xffc80030 4>;
 514                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 515                                  <&cpg_clocks R8A7778_CLK_P>,
 516                                  <&cpg_clocks R8A7778_CLK_P>,
 517                                  <&cpg_clocks R8A7778_CLK_P>,
 518                                  <&cpg_clocks R8A7778_CLK_P>,
 519                                  <&cpg_clocks R8A7778_CLK_P>,
 520                                  <&cpg_clocks R8A7778_CLK_P>,
 521                                  <&cpg_clocks R8A7778_CLK_P>,
 522                                  <&cpg_clocks R8A7778_CLK_P>,
 523                                  <&cpg_clocks R8A7778_CLK_P>,
 524                                  <&cpg_clocks R8A7778_CLK_P>,
 525                                  <&cpg_clocks R8A7778_CLK_P>,
 526                                  <&cpg_clocks R8A7778_CLK_P>,
 527                                  <&cpg_clocks R8A7778_CLK_P>,
 528                                  <&cpg_clocks R8A7778_CLK_P>,
 529                                  <&cpg_clocks R8A7778_CLK_P>,
 530                                  <&cpg_clocks R8A7778_CLK_P>,
 531                                  <&cpg_clocks R8A7778_CLK_P>,
 532                                  <&cpg_clocks R8A7778_CLK_S>;
 533                         #clock-cells = <1>;
 534                         clock-indices = <
 535                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 536                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 537                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 538                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 539                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 540                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 541                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 542                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 543                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 544                                 R8A7778_CLK_HSPI
 545                         >;
 546                         clock-output-names =
 547                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 548                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 549                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 550                                 "ssi2", "ssi3", "sru", "hspi";
 551                 };
 552                 mstp1_clks: mstp1_clks@ffc80034 {
 553                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 554                         reg = <0xffc80034 4>, <0xffc80044 4>;
 555                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 556                                  <&cpg_clocks R8A7778_CLK_S>,
 557                                  <&cpg_clocks R8A7778_CLK_S>,
 558                                  <&cpg_clocks R8A7778_CLK_P>;
 559                         #clock-cells = <1>;
 560                         clock-indices = <
 561                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 562                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 563                         >;
 564                         clock-output-names =
 565                                 "ether", "vin0", "vin1", "usb";
 566                 };
 567                 mstp3_clks: mstp3_clks@ffc8003c {
 568                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 569                         reg = <0xffc8003c 4>;
 570                         clocks = <&s4_clk>,
 571                                  <&cpg_clocks R8A7778_CLK_P>,
 572                                  <&cpg_clocks R8A7778_CLK_P>,
 573                                  <&cpg_clocks R8A7778_CLK_P>,
 574                                  <&cpg_clocks R8A7778_CLK_P>,
 575                                  <&cpg_clocks R8A7778_CLK_P>,
 576                                  <&cpg_clocks R8A7778_CLK_P>,
 577                                  <&cpg_clocks R8A7778_CLK_P>,
 578                                  <&cpg_clocks R8A7778_CLK_P>;
 579                         #clock-cells = <1>;
 580                         clock-indices = <
 581                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 582                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 583                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 584                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 585                                 R8A7778_CLK_SSI8
 586                         >;
 587                         clock-output-names =
 588                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 589                                 "ssi5", "ssi6", "ssi7", "ssi8";
 590                 };
 591                 mstp5_clks: mstp5_clks@ffc80054 {
 592                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 593                         reg = <0xffc80054 4>;
 594                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 595                                  <&cpg_clocks R8A7778_CLK_P>,
 596                                  <&cpg_clocks R8A7778_CLK_P>,
 597                                  <&cpg_clocks R8A7778_CLK_P>,
 598                                  <&cpg_clocks R8A7778_CLK_P>,
 599                                  <&cpg_clocks R8A7778_CLK_P>,
 600                                  <&cpg_clocks R8A7778_CLK_P>,
 601                                  <&cpg_clocks R8A7778_CLK_P>,
 602                                  <&cpg_clocks R8A7778_CLK_P>;
 603                         #clock-cells = <1>;
 604                         clock-indices = <
 605                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 606                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 607                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 608                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 609                                 R8A7778_CLK_SRU_SRC8
 610                         >;
 611                         clock-output-names =
 612                                 "sru-src0", "sru-src1", "sru-src2",
 613                                 "sru-src3", "sru-src4", "sru-src5",
 614                                 "sru-src6", "sru-src7", "sru-src8";
 615                 };
 616         };
 617 };