arch/arm/boot/dts/r8a7778.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car M1A (R8A77781) SoC
   4  *
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   7  *
   8  * based on r8a7779
   9  *
  10  * Copyright (C) 2013 Renesas Solutions Corp.
  11  * Copyright (C) 2013 Simon Horman
  12  */
  13
  14 #include <dt-bindings/clock/r8a7778-clock.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "renesas,r8a7778";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <0>;
  32                         clock-frequency = <800000000>;
  33                         clocks = <&z_clk>;
  34                 };
  35         };
  36
  37         aliases {
  38                 spi0 = &hspi0;
  39                 spi1 = &hspi1;
  40                 spi2 = &hspi2;
  41         };
  42
  43         bsc: bus@1c000000 {
  44                 compatible = "simple-bus";
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges = <0 0 0x1c000000>;
  48         };
  49
  50         ether: ethernet@fde00000 {
  51                 compatible = "renesas,ether-r8a7778",
  52                              "renesas,rcar-gen1-ether";
  53                 reg = <0xfde00000 0x400>;
  54                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  56                 power-domains = <&cpg_clocks>;
  57                 phy-mode = "rmii";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 status = "disabled";
  61         };
  62
  63         gic: interrupt-controller@fe438000 {
  64                 compatible = "arm,pl390";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xfe438000 0x1000>,
  68                       <0xfe430000 0x100>;
  69         };
  70
  71         /* irqpin: IRQ0 - IRQ3 */
  72         irqpin: interrupt-controller@fe78001c {
  73                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  74                 #interrupt-cells = <2>;
  75                 interrupt-controller;
  76                 status = "disabled"; /* default off */
  77                 reg =   <0xfe78001c 4>,
  78                         <0xfe780010 4>,
  79                         <0xfe780024 4>,
  80                         <0xfe780044 4>,
  81                         <0xfe780064 4>;
  82                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  86                 sense-bitfield-width = <2>;
  87         };
  88
  89         gpio0: gpio@ffc40000 {
  90                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
  91                 reg = <0xffc40000 0x2c>;
  92                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  93                 #gpio-cells = <2>;
  94                 gpio-controller;
  95                 gpio-ranges = <&pfc 0 0 32>;
  96                 #interrupt-cells = <2>;
  97                 interrupt-controller;
  98         };
  99
 100         gpio1: gpio@ffc41000 {
 101                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 102                 reg = <0xffc41000 0x2c>;
 103                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 104                 #gpio-cells = <2>;
 105                 gpio-controller;
 106                 gpio-ranges = <&pfc 0 32 32>;
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109         };
 110
 111         gpio2: gpio@ffc42000 {
 112                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 113                 reg = <0xffc42000 0x2c>;
 114                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 64 32>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120         };
 121
 122         gpio3: gpio@ffc43000 {
 123                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 124                 reg = <0xffc43000 0x2c>;
 125                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 96 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131         };
 132
 133         gpio4: gpio@ffc44000 {
 134                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 135                 reg = <0xffc44000 0x2c>;
 136                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 gpio-ranges = <&pfc 0 128 27>;
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142         };
 143
 144         pfc: pin-controller@fffc0000 {
 145                 compatible = "renesas,pfc-r8a7778";
 146                 reg = <0xfffc0000 0x118>;
 147         };
 148
 149         i2c0: i2c@ffc70000 {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 153                 reg = <0xffc70000 0x1000>;
 154                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 155                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 156                 power-domains = <&cpg_clocks>;
 157                 status = "disabled";
 158         };
 159
 160         i2c1: i2c@ffc71000 {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 164                 reg = <0xffc71000 0x1000>;
 165                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 167                 power-domains = <&cpg_clocks>;
 168                 status = "disabled";
 169         };
 170
 171         i2c2: i2c@ffc72000 {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 175                 reg = <0xffc72000 0x1000>;
 176                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 178                 power-domains = <&cpg_clocks>;
 179                 status = "disabled";
 180         };
 181
 182         i2c3: i2c@ffc73000 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 186                 reg = <0xffc73000 0x1000>;
 187                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 189                 power-domains = <&cpg_clocks>;
 190                 status = "disabled";
 191         };
 192
 193         tmu0: timer@ffd80000 {
 194                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 195                 reg = <0xffd80000 0x30>;
 196                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 200                 clock-names = "fck";
 201                 power-domains = <&cpg_clocks>;
 202
 203                 #renesas,channels = <3>;
 204
 205                 status = "disabled";
 206         };
 207
 208         tmu1: timer@ffd81000 {
 209                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 210                 reg = <0xffd81000 0x30>;
 211                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 215                 clock-names = "fck";
 216                 power-domains = <&cpg_clocks>;
 217
 218                 #renesas,channels = <3>;
 219
 220                 status = "disabled";
 221         };
 222
 223         tmu2: timer@ffd82000 {
 224                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 225                 reg = <0xffd82000 0x30>;
 226                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 230                 clock-names = "fck";
 231                 power-domains = <&cpg_clocks>;
 232
 233                 #renesas,channels = <3>;
 234
 235                 status = "disabled";
 236         };
 237
 238         rcar_sound: sound@ffd90000 {
 239                 /*
 240                  * #sound-dai-cells is required
 241                  *
 242                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 243                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 244                  */
 245                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 246                 reg =   <0xffd90000 0x1000>,    /* SRU */
 247                         <0xffd91000 0x240>,     /* SSI */
 248                         <0xfffe0000 0x24>;      /* ADG */
 249                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 250                         <&mstp3_clks R8A7778_CLK_SSI7>,
 251                         <&mstp3_clks R8A7778_CLK_SSI6>,
 252                         <&mstp3_clks R8A7778_CLK_SSI5>,
 253                         <&mstp3_clks R8A7778_CLK_SSI4>,
 254                         <&mstp0_clks R8A7778_CLK_SSI3>,
 255                         <&mstp0_clks R8A7778_CLK_SSI2>,
 256                         <&mstp0_clks R8A7778_CLK_SSI1>,
 257                         <&mstp0_clks R8A7778_CLK_SSI0>,
 258                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 259                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 260                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 261                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 267                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 268                         <&cpg_clocks R8A7778_CLK_S1>;
 269                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 270                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 271                         "src.8", "src.7", "src.6", "src.5", "src.4",
 272                         "src.3", "src.2", "src.1", "src.0",
 273                         "clk_a", "clk_b", "clk_c", "clk_i";
 274
 275                 status = "disabled";
 276
 277                 rcar_sound,src {
 278                         src3: src-3 { };
 279                         src4: src-4 { };
 280                         src5: src-5 { };
 281                         src6: src-6 { };
 282                         src7: src-7 { };
 283                         src8: src-8 { };
 284                         src9: src-9 { };
 285                 };
 286
 287                 rcar_sound,ssi {
 288                         ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 289                         ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 290                         ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 291                         ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 292                         ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                 };
 296         };
 297
 298         scif0: serial@ffe40000 {
 299                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 300                              "renesas,scif";
 301                 reg = <0xffe40000 0x100>;
 302                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
 304                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 305                 clock-names = "fck", "brg_int", "scif_clk";
 306                 power-domains = <&cpg_clocks>;
 307                 status = "disabled";
 308         };
 309
 310         scif1: serial@ffe41000 {
 311                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 312                              "renesas,scif";
 313                 reg = <0xffe41000 0x100>;
 314                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
 316                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 317                 clock-names = "fck", "brg_int", "scif_clk";
 318                 power-domains = <&cpg_clocks>;
 319                 status = "disabled";
 320         };
 321
 322         scif2: serial@ffe42000 {
 323                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 324                              "renesas,scif";
 325                 reg = <0xffe42000 0x100>;
 326                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
 328                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 329                 clock-names = "fck", "brg_int", "scif_clk";
 330                 power-domains = <&cpg_clocks>;
 331                 status = "disabled";
 332         };
 333
 334         scif3: serial@ffe43000 {
 335                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 336                              "renesas,scif";
 337                 reg = <0xffe43000 0x100>;
 338                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
 340                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 341                 clock-names = "fck", "brg_int", "scif_clk";
 342                 power-domains = <&cpg_clocks>;
 343                 status = "disabled";
 344         };
 345
 346         scif4: serial@ffe44000 {
 347                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 348                              "renesas,scif";
 349                 reg = <0xffe44000 0x100>;
 350                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
 352                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 353                 clock-names = "fck", "brg_int", "scif_clk";
 354                 power-domains = <&cpg_clocks>;
 355                 status = "disabled";
 356         };
 357
 358         scif5: serial@ffe45000 {
 359                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 360                              "renesas,scif";
 361                 reg = <0xffe45000 0x100>;
 362                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
 364                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 365                 clock-names = "fck", "brg_int", "scif_clk";
 366                 power-domains = <&cpg_clocks>;
 367                 status = "disabled";
 368         };
 369
 370         hscif0: serial@ffe48000 {
 371                 compatible = "renesas,hscif-r8a7778",
 372                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 373                 reg = <0xffe48000 96>;
 374                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
 376                          <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
 377                 clock-names = "fck", "brg_int", "scif_clk";
 378                 power-domains = <&cpg_clocks>;
 379                 status = "disabled";
 380         };
 381
 382         hscif1: serial@ffe49000 {
 383                 compatible = "renesas,hscif-r8a7778",
 384                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 385                 reg = <0xffe49000 96>;
 386                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
 388                          <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
 389                 clock-names = "fck", "brg_int", "scif_clk";
 390                 power-domains = <&cpg_clocks>;
 391                 status = "disabled";
 392         };
 393
 394         mmcif: mmc@ffe4e000 {
 395                 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
 396                 reg = <0xffe4e000 0x100>;
 397                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 399                 power-domains = <&cpg_clocks>;
 400                 status = "disabled";
 401         };
 402
 403         sdhi0: sd@ffe4c000 {
 404                 compatible = "renesas,sdhi-r8a7778",
 405                              "renesas,rcar-gen1-sdhi";
 406                 reg = <0xffe4c000 0x100>;
 407                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 409                 power-domains = <&cpg_clocks>;
 410                 status = "disabled";
 411         };
 412
 413         sdhi1: sd@ffe4d000 {
 414                 compatible = "renesas,sdhi-r8a7778",
 415                              "renesas,rcar-gen1-sdhi";
 416                 reg = <0xffe4d000 0x100>;
 417                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 419                 power-domains = <&cpg_clocks>;
 420                 status = "disabled";
 421         };
 422
 423         sdhi2: sd@ffe4f000 {
 424                 compatible = "renesas,sdhi-r8a7778",
 425                              "renesas,rcar-gen1-sdhi";
 426                 reg = <0xffe4f000 0x100>;
 427                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 429                 power-domains = <&cpg_clocks>;
 430                 status = "disabled";
 431         };
 432
 433         hspi0: spi@fffc7000 {
 434                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 435                 reg = <0xfffc7000 0x18>;
 436                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 438                 power-domains = <&cpg_clocks>;
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 status = "disabled";
 442         };
 443
 444         hspi1: spi@fffc8000 {
 445                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 446                 reg = <0xfffc8000 0x18>;
 447                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 449                 power-domains = <&cpg_clocks>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 status = "disabled";
 453         };
 454
 455         hspi2: spi@fffc6000 {
 456                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 457                 reg = <0xfffc6000 0x18>;
 458                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 460                 power-domains = <&cpg_clocks>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 status = "disabled";
 464         };
 465
 466         clocks {
 467                 #address-cells = <1>;
 468                 #size-cells = <1>;
 469                 ranges;
 470
 471                 /* External input clock */
 472                 extal_clk: extal {
 473                         compatible = "fixed-clock";
 474                         #clock-cells = <0>;
 475                         clock-frequency = <0>;
 476                 };
 477
 478                 /* External SCIF clock */
 479                 scif_clk: scif {
 480                         compatible = "fixed-clock";
 481                         #clock-cells = <0>;
 482                         /* This value must be overridden by the board. */
 483                         clock-frequency = <0>;
 484                 };
 485
 486                 /* Special CPG clocks */
 487                 cpg_clocks: cpg_clocks@ffc80000 {
 488                         compatible = "renesas,r8a7778-cpg-clocks";
 489                         reg = <0xffc80000 0x80>;
 490                         #clock-cells = <1>;
 491                         clocks = <&extal_clk>;
 492                         clock-output-names = "plla", "pllb", "b",
 493                                              "out", "p", "s", "s1";
 494                         #power-domain-cells = <0>;
 495                 };
 496
 497                 /* Audio clocks; frequencies are set by boards if applicable. */
 498                 audio_clk_a: audio_clk_a {
 499                         compatible = "fixed-clock";
 500                         #clock-cells = <0>;
 501                         clock-frequency = <0>;
 502                 };
 503                 audio_clk_b: audio_clk_b {
 504                         compatible = "fixed-clock";
 505                         #clock-cells = <0>;
 506                         clock-frequency = <0>;
 507                 };
 508                 audio_clk_c: audio_clk_c {
 509                         compatible = "fixed-clock";
 510                         #clock-cells = <0>;
 511                         clock-frequency = <0>;
 512                 };
 513
 514                 /* Fixed ratio clocks */
 515                 g_clk: g {
 516                         compatible = "fixed-factor-clock";
 517                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 518                         #clock-cells = <0>;
 519                         clock-div = <12>;
 520                         clock-mult = <1>;
 521                 };
 522                 i_clk: i {
 523                         compatible = "fixed-factor-clock";
 524                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 525                         #clock-cells = <0>;
 526                         clock-div = <1>;
 527                         clock-mult = <1>;
 528                 };
 529                 s3_clk: s3 {
 530                         compatible = "fixed-factor-clock";
 531                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 532                         #clock-cells = <0>;
 533                         clock-div = <4>;
 534                         clock-mult = <1>;
 535                 };
 536                 s4_clk: s4 {
 537                         compatible = "fixed-factor-clock";
 538                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 539                         #clock-cells = <0>;
 540                         clock-div = <8>;
 541                         clock-mult = <1>;
 542                 };
 543                 z_clk: z {
 544                         compatible = "fixed-factor-clock";
 545                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 546                         #clock-cells = <0>;
 547                         clock-div = <1>;
 548                         clock-mult = <1>;
 549                 };
 550
 551                 /* Gate clocks */
 552                 mstp0_clks: mstp0_clks@ffc80030 {
 553                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 554                         reg = <0xffc80030 4>;
 555                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 556                                  <&cpg_clocks R8A7778_CLK_P>,
 557                                  <&cpg_clocks R8A7778_CLK_P>,
 558                                  <&cpg_clocks R8A7778_CLK_P>,
 559                                  <&cpg_clocks R8A7778_CLK_P>,
 560                                  <&cpg_clocks R8A7778_CLK_P>,
 561                                  <&cpg_clocks R8A7778_CLK_P>,
 562                                  <&cpg_clocks R8A7778_CLK_P>,
 563                                  <&cpg_clocks R8A7778_CLK_P>,
 564                                  <&cpg_clocks R8A7778_CLK_P>,
 565                                  <&cpg_clocks R8A7778_CLK_S>,
 566                                  <&cpg_clocks R8A7778_CLK_S>,
 567                                  <&cpg_clocks R8A7778_CLK_P>,
 568                                  <&cpg_clocks R8A7778_CLK_P>,
 569                                  <&cpg_clocks R8A7778_CLK_P>,
 570                                  <&cpg_clocks R8A7778_CLK_P>,
 571                                  <&cpg_clocks R8A7778_CLK_P>,
 572                                  <&cpg_clocks R8A7778_CLK_P>,
 573                                  <&cpg_clocks R8A7778_CLK_P>,
 574                                  <&cpg_clocks R8A7778_CLK_P>,
 575                                  <&cpg_clocks R8A7778_CLK_S>;
 576                         #clock-cells = <1>;
 577                         clock-indices = <
 578                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 579                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 580                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 581                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 582                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 583                                 R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
 584                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 585                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 586                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 587                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 588                                 R8A7778_CLK_HSPI
 589                         >;
 590                         clock-output-names =
 591                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 592                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 593                                 "hscif0", "hscif1",
 594                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 595                                 "ssi2", "ssi3", "sru", "hspi";
 596                 };
 597                 mstp1_clks: mstp1_clks@ffc80034 {
 598                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 599                         reg = <0xffc80034 4>, <0xffc80044 4>;
 600                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 601                                  <&cpg_clocks R8A7778_CLK_S>,
 602                                  <&cpg_clocks R8A7778_CLK_S>,
 603                                  <&cpg_clocks R8A7778_CLK_P>;
 604                         #clock-cells = <1>;
 605                         clock-indices = <
 606                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 607                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 608                         >;
 609                         clock-output-names =
 610                                 "ether", "vin0", "vin1", "usb";
 611                 };
 612                 mstp3_clks: mstp3_clks@ffc8003c {
 613                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 614                         reg = <0xffc8003c 4>;
 615                         clocks = <&s4_clk>,
 616                                  <&cpg_clocks R8A7778_CLK_P>,
 617                                  <&cpg_clocks R8A7778_CLK_P>,
 618                                  <&cpg_clocks R8A7778_CLK_P>,
 619                                  <&cpg_clocks R8A7778_CLK_P>,
 620                                  <&cpg_clocks R8A7778_CLK_P>,
 621                                  <&cpg_clocks R8A7778_CLK_P>,
 622                                  <&cpg_clocks R8A7778_CLK_P>,
 623                                  <&cpg_clocks R8A7778_CLK_P>;
 624                         #clock-cells = <1>;
 625                         clock-indices = <
 626                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 627                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 628                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 629                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 630                                 R8A7778_CLK_SSI8
 631                         >;
 632                         clock-output-names =
 633                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 634                                 "ssi5", "ssi6", "ssi7", "ssi8";
 635                 };
 636                 mstp5_clks: mstp5_clks@ffc80054 {
 637                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 638                         reg = <0xffc80054 4>;
 639                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 640                                  <&cpg_clocks R8A7778_CLK_P>,
 641                                  <&cpg_clocks R8A7778_CLK_P>,
 642                                  <&cpg_clocks R8A7778_CLK_P>,
 643                                  <&cpg_clocks R8A7778_CLK_P>,
 644                                  <&cpg_clocks R8A7778_CLK_P>,
 645                                  <&cpg_clocks R8A7778_CLK_P>,
 646                                  <&cpg_clocks R8A7778_CLK_P>,
 647                                  <&cpg_clocks R8A7778_CLK_P>;
 648                         #clock-cells = <1>;
 649                         clock-indices = <
 650                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 651                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 652                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 653                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 654                                 R8A7778_CLK_SRU_SRC8
 655                         >;
 656                         clock-output-names =
 657                                 "sru-src0", "sru-src1", "sru-src2",
 658                                 "sru-src3", "sru-src4", "sru-src5",
 659                                 "sru-src6", "sru-src7", "sru-src8";
 660                 };
 661         };
 662
 663         rst: reset-controller@ffcc0000 {
 664                 compatible = "renesas,r8a7778-reset-wdt";
 665                 reg = <0xffcc0000 0x40>;
 666         };
 667 };