arch/arm/boot/dts/r8a7778.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7778
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2013 Renesas Solutions Corp.
  10  * Copyright (C) 2013 Simon Horman
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2.  This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 #include <dt-bindings/clock/r8a7778-clock.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         compatible = "renesas,r8a7778";
  23         interrupt-parent = <&gic>;
  24         #address-cells = <1>;
  25         #size-cells = <1>;
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <0>;
  35                         clock-frequency = <800000000>;
  36                         clocks = <&z_clk>;
  37                 };
  38         };
  39
  40         aliases {
  41                 spi0 = &hspi0;
  42                 spi1 = &hspi1;
  43                 spi2 = &hspi2;
  44         };
  45
  46         bsc: bus@1c000000 {
  47                 compatible = "simple-bus";
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0 0 0x1c000000>;
  51         };
  52
  53         ether: ethernet@fde00000 {
  54                 compatible = "renesas,ether-r8a7778",
  55                              "renesas,rcar-gen1-ether";
  56                 reg = <0xfde00000 0x400>;
  57                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  59                 power-domains = <&cpg_clocks>;
  60                 phy-mode = "rmii";
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 status = "disabled";
  64         };
  65
  66         gic: interrupt-controller@fe438000 {
  67                 compatible = "arm,pl390";
  68                 #interrupt-cells = <3>;
  69                 interrupt-controller;
  70                 reg = <0xfe438000 0x1000>,
  71                       <0xfe430000 0x100>;
  72         };
  73
  74         /* irqpin: IRQ0 - IRQ3 */
  75         irqpin: interrupt-controller@fe78001c {
  76                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  77                 #interrupt-cells = <2>;
  78                 interrupt-controller;
  79                 status = "disabled"; /* default off */
  80                 reg =   <0xfe78001c 4>,
  81                         <0xfe780010 4>,
  82                         <0xfe780024 4>,
  83                         <0xfe780044 4>,
  84                         <0xfe780064 4>;
  85                 interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
  86                                 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
  87                                 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
  88                                 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  89                 sense-bitfield-width = <2>;
  90         };
  91
  92         gpio0: gpio@ffc40000 {
  93                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
  94                 reg = <0xffc40000 0x2c>;
  95                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 0 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio1: gpio@ffc41000 {
 104                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 105                 reg = <0xffc41000 0x2c>;
 106                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 32 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio2: gpio@ffc42000 {
 115                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 116                 reg = <0xffc42000 0x2c>;
 117                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 64 32>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         gpio3: gpio@ffc43000 {
 126                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 127                 reg = <0xffc43000 0x2c>;
 128                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 96 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134         };
 135
 136         gpio4: gpio@ffc44000 {
 137                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 138                 reg = <0xffc44000 0x2c>;
 139                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 140                 #gpio-cells = <2>;
 141                 gpio-controller;
 142                 gpio-ranges = <&pfc 0 128 27>;
 143                 #interrupt-cells = <2>;
 144                 interrupt-controller;
 145         };
 146
 147         pfc: pin-controller@fffc0000 {
 148                 compatible = "renesas,pfc-r8a7778";
 149                 reg = <0xfffc0000 0x118>;
 150         };
 151
 152         i2c0: i2c@ffc70000 {
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 156                 reg = <0xffc70000 0x1000>;
 157                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 159                 power-domains = <&cpg_clocks>;
 160                 status = "disabled";
 161         };
 162
 163         i2c1: i2c@ffc71000 {
 164                 #address-cells = <1>;
 165                 #size-cells = <0>;
 166                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 167                 reg = <0xffc71000 0x1000>;
 168                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 170                 power-domains = <&cpg_clocks>;
 171                 status = "disabled";
 172         };
 173
 174         i2c2: i2c@ffc72000 {
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 178                 reg = <0xffc72000 0x1000>;
 179                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 180                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 181                 power-domains = <&cpg_clocks>;
 182                 status = "disabled";
 183         };
 184
 185         i2c3: i2c@ffc73000 {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 189                 reg = <0xffc73000 0x1000>;
 190                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 191                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 192                 power-domains = <&cpg_clocks>;
 193                 status = "disabled";
 194         };
 195
 196         tmu0: timer@ffd80000 {
 197                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 198                 reg = <0xffd80000 0x30>;
 199                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 203                 clock-names = "fck";
 204                 power-domains = <&cpg_clocks>;
 205
 206                 #renesas,channels = <3>;
 207
 208                 status = "disabled";
 209         };
 210
 211         tmu1: timer@ffd81000 {
 212                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 213                 reg = <0xffd81000 0x30>;
 214                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 218                 clock-names = "fck";
 219                 power-domains = <&cpg_clocks>;
 220
 221                 #renesas,channels = <3>;
 222
 223                 status = "disabled";
 224         };
 225
 226         tmu2: timer@ffd82000 {
 227                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 228                 reg = <0xffd82000 0x30>;
 229                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 233                 clock-names = "fck";
 234                 power-domains = <&cpg_clocks>;
 235
 236                 #renesas,channels = <3>;
 237
 238                 status = "disabled";
 239         };
 240
 241         rcar_sound: sound@ffd90000 {
 242                 /*
 243                  * #sound-dai-cells is required
 244                  *
 245                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 246                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 247                  */
 248                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 249                 reg =   <0xffd90000 0x1000>,    /* SRU */
 250                         <0xffd91000 0x240>,     /* SSI */
 251                         <0xfffe0000 0x24>;      /* ADG */
 252                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 253                         <&mstp3_clks R8A7778_CLK_SSI7>,
 254                         <&mstp3_clks R8A7778_CLK_SSI6>,
 255                         <&mstp3_clks R8A7778_CLK_SSI5>,
 256                         <&mstp3_clks R8A7778_CLK_SSI4>,
 257                         <&mstp0_clks R8A7778_CLK_SSI3>,
 258                         <&mstp0_clks R8A7778_CLK_SSI2>,
 259                         <&mstp0_clks R8A7778_CLK_SSI1>,
 260                         <&mstp0_clks R8A7778_CLK_SSI0>,
 261                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 267                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 268                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 269                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 270                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 271                         <&cpg_clocks R8A7778_CLK_S1>;
 272                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 273                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 274                         "src.8", "src.7", "src.6", "src.5", "src.4",
 275                         "src.3", "src.2", "src.1", "src.0",
 276                         "clk_a", "clk_b", "clk_c", "clk_i";
 277
 278                 status = "disabled";
 279
 280                 rcar_sound,src {
 281                         src3: src-3 { };
 282                         src4: src-4 { };
 283                         src5: src-5 { };
 284                         src6: src-6 { };
 285                         src7: src-7 { };
 286                         src8: src-8 { };
 287                         src9: src-9 { };
 288                 };
 289
 290                 rcar_sound,ssi {
 291                         ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 292                         ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                         ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 296                         ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 297                         ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 298                 };
 299         };
 300
 301         scif0: serial@ffe40000 {
 302                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 303                              "renesas,scif";
 304                 reg = <0xffe40000 0x100>;
 305                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
 307                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 308                 clock-names = "fck", "brg_int", "scif_clk";
 309                 power-domains = <&cpg_clocks>;
 310                 status = "disabled";
 311         };
 312
 313         scif1: serial@ffe41000 {
 314                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 315                              "renesas,scif";
 316                 reg = <0xffe41000 0x100>;
 317                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
 319                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 320                 clock-names = "fck", "brg_int", "scif_clk";
 321                 power-domains = <&cpg_clocks>;
 322                 status = "disabled";
 323         };
 324
 325         scif2: serial@ffe42000 {
 326                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 327                              "renesas,scif";
 328                 reg = <0xffe42000 0x100>;
 329                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
 331                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 332                 clock-names = "fck", "brg_int", "scif_clk";
 333                 power-domains = <&cpg_clocks>;
 334                 status = "disabled";
 335         };
 336
 337         scif3: serial@ffe43000 {
 338                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 339                              "renesas,scif";
 340                 reg = <0xffe43000 0x100>;
 341                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
 343                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 344                 clock-names = "fck", "brg_int", "scif_clk";
 345                 power-domains = <&cpg_clocks>;
 346                 status = "disabled";
 347         };
 348
 349         scif4: serial@ffe44000 {
 350                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 351                              "renesas,scif";
 352                 reg = <0xffe44000 0x100>;
 353                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
 355                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 356                 clock-names = "fck", "brg_int", "scif_clk";
 357                 power-domains = <&cpg_clocks>;
 358                 status = "disabled";
 359         };
 360
 361         scif5: serial@ffe45000 {
 362                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 363                              "renesas,scif";
 364                 reg = <0xffe45000 0x100>;
 365                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
 367                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 368                 clock-names = "fck", "brg_int", "scif_clk";
 369                 power-domains = <&cpg_clocks>;
 370                 status = "disabled";
 371         };
 372
 373         mmcif: mmc@ffe4e000 {
 374                 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
 375                 reg = <0xffe4e000 0x100>;
 376                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 378                 power-domains = <&cpg_clocks>;
 379                 status = "disabled";
 380         };
 381
 382         sdhi0: sd@ffe4c000 {
 383                 compatible = "renesas,sdhi-r8a7778",
 384                              "renesas,rcar-gen1-sdhi";
 385                 reg = <0xffe4c000 0x100>;
 386                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 388                 power-domains = <&cpg_clocks>;
 389                 status = "disabled";
 390         };
 391
 392         sdhi1: sd@ffe4d000 {
 393                 compatible = "renesas,sdhi-r8a7778",
 394                              "renesas,rcar-gen1-sdhi";
 395                 reg = <0xffe4d000 0x100>;
 396                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 398                 power-domains = <&cpg_clocks>;
 399                 status = "disabled";
 400         };
 401
 402         sdhi2: sd@ffe4f000 {
 403                 compatible = "renesas,sdhi-r8a7778",
 404                              "renesas,rcar-gen1-sdhi";
 405                 reg = <0xffe4f000 0x100>;
 406                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 408                 power-domains = <&cpg_clocks>;
 409                 status = "disabled";
 410         };
 411
 412         hspi0: spi@fffc7000 {
 413                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 414                 reg = <0xfffc7000 0x18>;
 415                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 417                 power-domains = <&cpg_clocks>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 status = "disabled";
 421         };
 422
 423         hspi1: spi@fffc8000 {
 424                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 425                 reg = <0xfffc8000 0x18>;
 426                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 428                 power-domains = <&cpg_clocks>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 status = "disabled";
 432         };
 433
 434         hspi2: spi@fffc6000 {
 435                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 436                 reg = <0xfffc6000 0x18>;
 437                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 438                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 439                 power-domains = <&cpg_clocks>;
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 status = "disabled";
 443         };
 444
 445         clocks {
 446                 #address-cells = <1>;
 447                 #size-cells = <1>;
 448                 ranges;
 449
 450                 /* External input clock */
 451                 extal_clk: extal {
 452                         compatible = "fixed-clock";
 453                         #clock-cells = <0>;
 454                         clock-frequency = <0>;
 455                 };
 456
 457                 /* External SCIF clock */
 458                 scif_clk: scif {
 459                         compatible = "fixed-clock";
 460                         #clock-cells = <0>;
 461                         /* This value must be overridden by the board. */
 462                         clock-frequency = <0>;
 463                 };
 464
 465                 /* Special CPG clocks */
 466                 cpg_clocks: cpg_clocks@ffc80000 {
 467                         compatible = "renesas,r8a7778-cpg-clocks";
 468                         reg = <0xffc80000 0x80>;
 469                         #clock-cells = <1>;
 470                         clocks = <&extal_clk>;
 471                         clock-output-names = "plla", "pllb", "b",
 472                                              "out", "p", "s", "s1";
 473                         #power-domain-cells = <0>;
 474                 };
 475
 476                 /* Audio clocks; frequencies are set by boards if applicable. */
 477                 audio_clk_a: audio_clk_a {
 478                         compatible = "fixed-clock";
 479                         #clock-cells = <0>;
 480                 };
 481                 audio_clk_b: audio_clk_b {
 482                         compatible = "fixed-clock";
 483                         #clock-cells = <0>;
 484                 };
 485                 audio_clk_c: audio_clk_c {
 486                         compatible = "fixed-clock";
 487                         #clock-cells = <0>;
 488                 };
 489
 490                 /* Fixed ratio clocks */
 491                 g_clk: g {
 492                         compatible = "fixed-factor-clock";
 493                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 494                         #clock-cells = <0>;
 495                         clock-div = <12>;
 496                         clock-mult = <1>;
 497                 };
 498                 i_clk: i {
 499                         compatible = "fixed-factor-clock";
 500                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 501                         #clock-cells = <0>;
 502                         clock-div = <1>;
 503                         clock-mult = <1>;
 504                 };
 505                 s3_clk: s3 {
 506                         compatible = "fixed-factor-clock";
 507                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 508                         #clock-cells = <0>;
 509                         clock-div = <4>;
 510                         clock-mult = <1>;
 511                 };
 512                 s4_clk: s4 {
 513                         compatible = "fixed-factor-clock";
 514                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 515                         #clock-cells = <0>;
 516                         clock-div = <8>;
 517                         clock-mult = <1>;
 518                 };
 519                 z_clk: z {
 520                         compatible = "fixed-factor-clock";
 521                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 522                         #clock-cells = <0>;
 523                         clock-div = <1>;
 524                         clock-mult = <1>;
 525                 };
 526
 527                 /* Gate clocks */
 528                 mstp0_clks: mstp0_clks@ffc80030 {
 529                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 530                         reg = <0xffc80030 4>;
 531                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 532                                  <&cpg_clocks R8A7778_CLK_P>,
 533                                  <&cpg_clocks R8A7778_CLK_P>,
 534                                  <&cpg_clocks R8A7778_CLK_P>,
 535                                  <&cpg_clocks R8A7778_CLK_P>,
 536                                  <&cpg_clocks R8A7778_CLK_P>,
 537                                  <&cpg_clocks R8A7778_CLK_P>,
 538                                  <&cpg_clocks R8A7778_CLK_P>,
 539                                  <&cpg_clocks R8A7778_CLK_P>,
 540                                  <&cpg_clocks R8A7778_CLK_P>,
 541                                  <&cpg_clocks R8A7778_CLK_P>,
 542                                  <&cpg_clocks R8A7778_CLK_P>,
 543                                  <&cpg_clocks R8A7778_CLK_P>,
 544                                  <&cpg_clocks R8A7778_CLK_P>,
 545                                  <&cpg_clocks R8A7778_CLK_P>,
 546                                  <&cpg_clocks R8A7778_CLK_P>,
 547                                  <&cpg_clocks R8A7778_CLK_P>,
 548                                  <&cpg_clocks R8A7778_CLK_P>,
 549                                  <&cpg_clocks R8A7778_CLK_S>;
 550                         #clock-cells = <1>;
 551                         clock-indices = <
 552                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 553                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 554                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 555                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 556                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 557                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 558                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 559                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 560                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 561                                 R8A7778_CLK_HSPI
 562                         >;
 563                         clock-output-names =
 564                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 565                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 566                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 567                                 "ssi2", "ssi3", "sru", "hspi";
 568                 };
 569                 mstp1_clks: mstp1_clks@ffc80034 {
 570                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 571                         reg = <0xffc80034 4>, <0xffc80044 4>;
 572                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 573                                  <&cpg_clocks R8A7778_CLK_S>,
 574                                  <&cpg_clocks R8A7778_CLK_S>,
 575                                  <&cpg_clocks R8A7778_CLK_P>;
 576                         #clock-cells = <1>;
 577                         clock-indices = <
 578                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 579                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 580                         >;
 581                         clock-output-names =
 582                                 "ether", "vin0", "vin1", "usb";
 583                 };
 584                 mstp3_clks: mstp3_clks@ffc8003c {
 585                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 586                         reg = <0xffc8003c 4>;
 587                         clocks = <&s4_clk>,
 588                                  <&cpg_clocks R8A7778_CLK_P>,
 589                                  <&cpg_clocks R8A7778_CLK_P>,
 590                                  <&cpg_clocks R8A7778_CLK_P>,
 591                                  <&cpg_clocks R8A7778_CLK_P>,
 592                                  <&cpg_clocks R8A7778_CLK_P>,
 593                                  <&cpg_clocks R8A7778_CLK_P>,
 594                                  <&cpg_clocks R8A7778_CLK_P>,
 595                                  <&cpg_clocks R8A7778_CLK_P>;
 596                         #clock-cells = <1>;
 597                         clock-indices = <
 598                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 599                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 600                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 601                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 602                                 R8A7778_CLK_SSI8
 603                         >;
 604                         clock-output-names =
 605                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 606                                 "ssi5", "ssi6", "ssi7", "ssi8";
 607                 };
 608                 mstp5_clks: mstp5_clks@ffc80054 {
 609                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 610                         reg = <0xffc80054 4>;
 611                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 612                                  <&cpg_clocks R8A7778_CLK_P>,
 613                                  <&cpg_clocks R8A7778_CLK_P>,
 614                                  <&cpg_clocks R8A7778_CLK_P>,
 615                                  <&cpg_clocks R8A7778_CLK_P>,
 616                                  <&cpg_clocks R8A7778_CLK_P>,
 617                                  <&cpg_clocks R8A7778_CLK_P>,
 618                                  <&cpg_clocks R8A7778_CLK_P>,
 619                                  <&cpg_clocks R8A7778_CLK_P>;
 620                         #clock-cells = <1>;
 621                         clock-indices = <
 622                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 623                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 624                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 625                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 626                                 R8A7778_CLK_SRU_SRC8
 627                         >;
 628                         clock-output-names =
 629                                 "sru-src0", "sru-src1", "sru-src2",
 630                                 "sru-src3", "sru-src4", "sru-src5",
 631                                 "sru-src6", "sru-src7", "sru-src8";
 632                 };
 633         };
 634
 635         rst: reset-controller@ffcc0000 {
 636                 compatible = "renesas,r8a7778-reset-wdt";
 637                 reg = <0xffcc0000 0x40>;
 638         };
 639 };