arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts

   1 /*
   2  * Device Tree Source for the iWave-RZG1E SODIMM carrier board
   3  *
   4  * Copyright (C) 2017 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 #include "r8a7745-iwg22m.dtsi"
  13
  14 / {
  15         model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
  16         compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
  17
  18         aliases {
  19                 serial0 = &scif4;
  20                 ethernet0 = &avb;
  21         };
  22
  23         chosen {
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         vccq_sdhi0: regulator-vccq-sdhi0 {
  29                 compatible = "regulator-gpio";
  30
  31                 regulator-name = "SDHI0 VccQ";
  32                 regulator-min-microvolt = <1800000>;
  33                 regulator-max-microvolt = <3300000>;
  34
  35                 gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  36                 gpios-states = <1>;
  37                 states = <3300000 1
  38                           1800000 0>;
  39         };
  40 };
  41
  42 &pfc {
  43         scif4_pins: scif4 {
  44                 groups = "scif4_data_b";
  45                 function = "scif4";
  46         };
  47
  48         avb_pins: avb {
  49                 groups = "avb_mdio", "avb_gmii";
  50                 function = "avb";
  51         };
  52
  53         sdhi0_pins: sd0 {
  54                 groups = "sdhi0_data4", "sdhi0_ctrl";
  55                 function = "sdhi0";
  56                 power-source = <3300>;
  57         };
  58
  59         usb1_pins: usb1 {
  60                 groups = "usb1";
  61                 function = "usb1";
  62         };
  63 };
  64
  65 &scif4 {
  66         pinctrl-0 = <&scif4_pins>;
  67         pinctrl-names = "default";
  68
  69         status = "okay";
  70 };
  71
  72 &avb {
  73         pinctrl-0 = <&avb_pins>;
  74         pinctrl-names = "default";
  75
  76         phy-handle = <&phy3>;
  77         phy-mode = "gmii";
  78         renesas,no-ether-link;
  79         status = "okay";
  80
  81         phy3: ethernet-phy@3 {
  82         /*
  83          * On some older versions of the platform (before R4.0) the phy address
  84          * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
  85          */
  86                 reg = <3>;
  87                 micrel,led-mode = <1>;
  88         };
  89 };
  90
  91 &sdhi0 {
  92         pinctrl-0 = <&sdhi0_pins>;
  93         pinctrl-names = "default";
  94
  95         vmmc-supply = <&reg_3p3v>;
  96         vqmmc-supply = <&vccq_sdhi0>;
  97         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
  98         status = "okay";
  99 };
 100
 101 &pci1 {
 102         status = "okay";
 103         pinctrl-0 = <&usb1_pins>;
 104         pinctrl-names = "default";
 105 };
 106
 107 &usbphy {
 108         status = "okay";
 109 };