arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15                 interrupts = <1 9 0xf04>;
  16
  17                 cpu@0 {
  18                         compatible = "qcom,krait";
  19                         enable-method = "qcom,kpss-acc-v2";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                         qcom,acc = <&acc0>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "qcom,krait";
  28                         enable-method = "qcom,kpss-acc-v2";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         next-level-cache = <&L2>;
  32                         qcom,acc = <&acc1>;
  33                 };
  34
  35                 cpu@2 {
  36                         compatible = "qcom,krait";
  37                         enable-method = "qcom,kpss-acc-v2";
  38                         device_type = "cpu";
  39                         reg = <2>;
  40                         next-level-cache = <&L2>;
  41                         qcom,acc = <&acc2>;
  42                 };
  43
  44                 cpu@3 {
  45                         compatible = "qcom,krait";
  46                         enable-method = "qcom,kpss-acc-v2";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         next-level-cache = <&L2>;
  50                         qcom,acc = <&acc3>;
  51                 };
  52
  53                 L2: l2-cache {
  54                         compatible = "cache";
  55                         cache-level = <2>;
  56                         qcom,saw = <&saw_l2>;
  57                 };
  58         };
  59
  60         cpu-pmu {
  61                 compatible = "qcom,krait-pmu";
  62                 interrupts = <1 7 0xf04>;
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv7-timer";
  67                 interrupts = <1 2 0xf08>,
  68                              <1 3 0xf08>,
  69                              <1 4 0xf08>,
  70                              <1 1 0xf08>;
  71                 clock-frequency = <19200000>;
  72         };
  73
  74         soc: soc {
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 ranges;
  78                 compatible = "simple-bus";
  79
  80                 intc: interrupt-controller@f9000000 {
  81                         compatible = "qcom,msm-qgic2";
  82                         interrupt-controller;
  83                         #interrupt-cells = <3>;
  84                         reg = <0xf9000000 0x1000>,
  85                               <0xf9002000 0x1000>;
  86                 };
  87
  88                 timer@f9020000 {
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         ranges;
  92                         compatible = "arm,armv7-timer-mem";
  93                         reg = <0xf9020000 0x1000>;
  94                         clock-frequency = <19200000>;
  95
  96                         frame@f9021000 {
  97                                 frame-number = <0>;
  98                                 interrupts = <0 8 0x4>,
  99                                              <0 7 0x4>;
 100                                 reg = <0xf9021000 0x1000>,
 101                                       <0xf9022000 0x1000>;
 102                         };
 103
 104                         frame@f9023000 {
 105                                 frame-number = <1>;
 106                                 interrupts = <0 9 0x4>;
 107                                 reg = <0xf9023000 0x1000>;
 108                                 status = "disabled";
 109                         };
 110
 111                         frame@f9024000 {
 112                                 frame-number = <2>;
 113                                 interrupts = <0 10 0x4>;
 114                                 reg = <0xf9024000 0x1000>;
 115                                 status = "disabled";
 116                         };
 117
 118                         frame@f9025000 {
 119                                 frame-number = <3>;
 120                                 interrupts = <0 11 0x4>;
 121                                 reg = <0xf9025000 0x1000>;
 122                                 status = "disabled";
 123                         };
 124
 125                         frame@f9026000 {
 126                                 frame-number = <4>;
 127                                 interrupts = <0 12 0x4>;
 128                                 reg = <0xf9026000 0x1000>;
 129                                 status = "disabled";
 130                         };
 131
 132                         frame@f9027000 {
 133                                 frame-number = <5>;
 134                                 interrupts = <0 13 0x4>;
 135                                 reg = <0xf9027000 0x1000>;
 136                                 status = "disabled";
 137                         };
 138
 139                         frame@f9028000 {
 140                                 frame-number = <6>;
 141                                 interrupts = <0 14 0x4>;
 142                                 reg = <0xf9028000 0x1000>;
 143                                 status = "disabled";
 144                         };
 145                 };
 146
 147                 saw_l2: regulator@f9012000 {
 148                         compatible = "qcom,saw2";
 149                         reg = <0xf9012000 0x1000>;
 150                         regulator;
 151                 };
 152
 153                 acc0: clock-controller@f9088000 {
 154                         compatible = "qcom,kpss-acc-v2";
 155                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 156                 };
 157
 158                 acc1: clock-controller@f9098000 {
 159                         compatible = "qcom,kpss-acc-v2";
 160                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 161                 };
 162
 163                 acc2: clock-controller@f90a8000 {
 164                         compatible = "qcom,kpss-acc-v2";
 165                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 166                 };
 167
 168                 acc3: clock-controller@f90b8000 {
 169                         compatible = "qcom,kpss-acc-v2";
 170                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 171                 };
 172
 173                 restart@fc4ab000 {
 174                         compatible = "qcom,pshold";
 175                         reg = <0xfc4ab000 0x4>;
 176                 };
 177
 178                 gcc: clock-controller@fc400000 {
 179                         compatible = "qcom,gcc-msm8974";
 180                         #clock-cells = <1>;
 181                         #reset-cells = <1>;
 182                         reg = <0xfc400000 0x4000>;
 183                 };
 184
 185                 mmcc: clock-controller@fd8c0000 {
 186                         compatible = "qcom,mmcc-msm8974";
 187                         #clock-cells = <1>;
 188                         #reset-cells = <1>;
 189                         reg = <0xfd8c0000 0x6000>;
 190                 };
 191
 192                 serial@f991e000 {
 193                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 194                         reg = <0xf991e000 0x1000>;
 195                         interrupts = <0 108 0x0>;
 196                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 197                         clock-names = "core", "iface";
 198                         status = "disabled";
 199                 };
 200
 201                 sdhci@f9824900 {
 202                         compatible = "qcom,sdhci-msm-v4";
 203                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 204                         reg-names = "hc_mem", "core_mem";
 205                         interrupts = <0 123 0>, <0 138 0>;
 206                         interrupt-names = "hc_irq", "pwr_irq";
 207                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 208                         clock-names = "core", "iface";
 209                         status = "disabled";
 210                 };
 211
 212                 sdhci@f98a4900 {
 213                         compatible = "qcom,sdhci-msm-v4";
 214                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 215                         reg-names = "hc_mem", "core_mem";
 216                         interrupts = <0 125 0>, <0 221 0>;
 217                         interrupt-names = "hc_irq", "pwr_irq";
 218                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 219                         clock-names = "core", "iface";
 220                         status = "disabled";
 221                 };
 222
 223                 rng@f9bff000 {
 224                         compatible = "qcom,prng";
 225                         reg = <0xf9bff000 0x200>;
 226                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 227                         clock-names = "core";
 228                 };
 229
 230                 msmgpio: pinctrl@fd510000 {
 231                         compatible = "qcom,msm8974-pinctrl";
 232                         reg = <0xfd510000 0x4000>;
 233                         gpio-controller;
 234                         #gpio-cells = <2>;
 235                         interrupt-controller;
 236                         #interrupt-cells = <2>;
 237                         interrupts = <0 208 0>;
 238                 };
 239
 240                 blsp_i2c11: i2c@f9967000 {
 241                         status = "disable";
 242                         compatible = "qcom,i2c-qup-v2.1.1";
 243                         reg = <0xf9967000 0x1000>;
 244                         interrupts = <0 105 IRQ_TYPE_NONE>;
 245                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 246                         clock-names = "core", "iface";
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                 };
 250         };
 251 };