arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         model = "Qualcomm MSM8974";
  11         compatible = "qcom,msm8974";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 mpss@08000000 {
  20                         reg = <0x08000000 0x5100000>;
  21                         no-map;
  22                 };
  23
  24                 mba@00d100000 {
  25                         reg = <0x0d100000 0x100000>;
  26                         no-map;
  27                 };
  28
  29                 reserved@0d200000 {
  30                         reg = <0x0d200000 0xa00000>;
  31                         no-map;
  32                 };
  33
  34                 adsp_region: adsp@0dc00000 {
  35                         reg = <0x0dc00000 0x1900000>;
  36                         no-map;
  37                 };
  38
  39                 venus@0f500000 {
  40                         reg = <0x0f500000 0x500000>;
  41                         no-map;
  42                 };
  43
  44                 smem_region: smem@fa00000 {
  45                         reg = <0xfa00000 0x200000>;
  46                         no-map;
  47                 };
  48
  49                 tz@0fc00000 {
  50                         reg = <0x0fc00000 0x160000>;
  51                         no-map;
  52                 };
  53
  54                 rfsa@0fd60000 {
  55                         reg = <0x0fd60000 0x20000>;
  56                         no-map;
  57                 };
  58
  59                 rmtfs@0fd80000 {
  60                         reg = <0x0fd80000 0x180000>;
  61                         no-map;
  62                 };
  63         };
  64
  65         cpus {
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68                 interrupts = <1 9 0xf04>;
  69
  70                 cpu@0 {
  71                         compatible = "qcom,krait";
  72                         enable-method = "qcom,kpss-acc-v2";
  73                         device_type = "cpu";
  74                         reg = <0>;
  75                         next-level-cache = <&L2>;
  76                         qcom,acc = <&acc0>;
  77                         qcom,saw = <&saw0>;
  78                         cpu-idle-states = <&CPU_SPC>;
  79                 };
  80
  81                 cpu@1 {
  82                         compatible = "qcom,krait";
  83                         enable-method = "qcom,kpss-acc-v2";
  84                         device_type = "cpu";
  85                         reg = <1>;
  86                         next-level-cache = <&L2>;
  87                         qcom,acc = <&acc1>;
  88                         qcom,saw = <&saw1>;
  89                         cpu-idle-states = <&CPU_SPC>;
  90                 };
  91
  92                 cpu@2 {
  93                         compatible = "qcom,krait";
  94                         enable-method = "qcom,kpss-acc-v2";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                         next-level-cache = <&L2>;
  98                         qcom,acc = <&acc2>;
  99                         qcom,saw = <&saw2>;
 100                         cpu-idle-states = <&CPU_SPC>;
 101                 };
 102
 103                 cpu@3 {
 104                         compatible = "qcom,krait";
 105                         enable-method = "qcom,kpss-acc-v2";
 106                         device_type = "cpu";
 107                         reg = <3>;
 108                         next-level-cache = <&L2>;
 109                         qcom,acc = <&acc3>;
 110                         qcom,saw = <&saw3>;
 111                         cpu-idle-states = <&CPU_SPC>;
 112                 };
 113
 114                 L2: l2-cache {
 115                         compatible = "cache";
 116                         cache-level = <2>;
 117                         qcom,saw = <&saw_l2>;
 118                 };
 119
 120                 idle-states {
 121                         CPU_SPC: spc {
 122                                 compatible = "qcom,idle-state-spc",
 123                                                 "arm,idle-state";
 124                                 entry-latency-us = <150>;
 125                                 exit-latency-us = <200>;
 126                                 min-residency-us = <2000>;
 127                         };
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 cpu-thermal0 {
 133                         polling-delay-passive = <250>;
 134                         polling-delay = <1000>;
 135
 136                         thermal-sensors = <&tsens 5>;
 137
 138                         trips {
 139                                 cpu_alert0: trip0 {
 140                                         temperature = <75000>;
 141                                         hysteresis = <2000>;
 142                                         type = "passive";
 143                                 };
 144                                 cpu_crit0: trip1 {
 145                                         temperature = <110000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150                 };
 151
 152                 cpu-thermal1 {
 153                         polling-delay-passive = <250>;
 154                         polling-delay = <1000>;
 155
 156                         thermal-sensors = <&tsens 6>;
 157
 158                         trips {
 159                                 cpu_alert1: trip0 {
 160                                         temperature = <75000>;
 161                                         hysteresis = <2000>;
 162                                         type = "passive";
 163                                 };
 164                                 cpu_crit1: trip1 {
 165                                         temperature = <110000>;
 166                                         hysteresis = <2000>;
 167                                         type = "critical";
 168                                 };
 169                         };
 170                 };
 171
 172                 cpu-thermal2 {
 173                         polling-delay-passive = <250>;
 174                         polling-delay = <1000>;
 175
 176                         thermal-sensors = <&tsens 7>;
 177
 178                         trips {
 179                                 cpu_alert2: trip0 {
 180                                         temperature = <75000>;
 181                                         hysteresis = <2000>;
 182                                         type = "passive";
 183                                 };
 184                                 cpu_crit2: trip1 {
 185                                         temperature = <110000>;
 186                                         hysteresis = <2000>;
 187                                         type = "critical";
 188                                 };
 189                         };
 190                 };
 191
 192                 cpu-thermal3 {
 193                         polling-delay-passive = <250>;
 194                         polling-delay = <1000>;
 195
 196                         thermal-sensors = <&tsens 8>;
 197
 198                         trips {
 199                                 cpu_alert3: trip0 {
 200                                         temperature = <75000>;
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                                 cpu_crit3: trip1 {
 205                                         temperature = <110000>;
 206                                         hysteresis = <2000>;
 207                                         type = "critical";
 208                                 };
 209                         };
 210                 };
 211         };
 212
 213         cpu-pmu {
 214                 compatible = "qcom,krait-pmu";
 215                 interrupts = <1 7 0xf04>;
 216         };
 217
 218         clocks {
 219                 xo_board: xo_board {
 220                         compatible = "fixed-clock";
 221                         #clock-cells = <0>;
 222                         clock-frequency = <19200000>;
 223                 };
 224
 225                 sleep_clk: sleep_clk {
 226                         compatible = "fixed-clock";
 227                         #clock-cells = <0>;
 228                         clock-frequency = <32768>;
 229                 };
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv7-timer";
 234                 interrupts = <1 2 0xf08>,
 235                              <1 3 0xf08>,
 236                              <1 4 0xf08>,
 237                              <1 1 0xf08>;
 238                 clock-frequency = <19200000>;
 239         };
 240
 241         adsp-pil {
 242                 compatible = "qcom,msm8974-adsp-pil";
 243
 244                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
 245                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 246                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 247                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 248                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 249                 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 250
 251                 cx-supply = <&pm8841_s2>;
 252
 253                 memory-region = <&adsp_region>;
 254
 255                 qcom,smem-states = <&adsp_smp2p_out 0>;
 256                 qcom,smem-state-names = "stop";
 257         };
 258
 259         smem {
 260                 compatible = "qcom,smem";
 261
 262                 memory-region = <&smem_region>;
 263                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 264
 265                 hwlocks = <&tcsr_mutex 3>;
 266         };
 267
 268         smp2p-adsp {
 269                 compatible = "qcom,smp2p";
 270                 qcom,smem = <443>, <429>;
 271
 272                 interrupt-parent = <&intc>;
 273                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 274
 275                 qcom,ipc = <&apcs 8 10>;
 276
 277                 qcom,local-pid = <0>;
 278                 qcom,remote-pid = <2>;
 279
 280                 adsp_smp2p_out: master-kernel {
 281                         qcom,entry-name = "master-kernel";
 282                         #qcom,smem-state-cells = <1>;
 283                 };
 284
 285                 adsp_smp2p_in: slave-kernel {
 286                         qcom,entry-name = "slave-kernel";
 287
 288                         interrupt-controller;
 289                         #interrupt-cells = <2>;
 290                 };
 291         };
 292
 293         smp2p-modem {
 294                 compatible = "qcom,smp2p";
 295                 qcom,smem = <435>, <428>;
 296
 297                 interrupt-parent = <&intc>;
 298                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 299
 300                 qcom,ipc = <&apcs 8 14>;
 301
 302                 qcom,local-pid = <0>;
 303                 qcom,remote-pid = <1>;
 304
 305                 modem_smp2p_out: master-kernel {
 306                         qcom,entry-name = "master-kernel";
 307                         #qcom,smem-state-cells = <1>;
 308                 };
 309
 310                 modem_smp2p_in: slave-kernel {
 311                         qcom,entry-name = "slave-kernel";
 312
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                 };
 316         };
 317
 318         smp2p-wcnss {
 319                 compatible = "qcom,smp2p";
 320                 qcom,smem = <451>, <431>;
 321
 322                 interrupt-parent = <&intc>;
 323                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 324
 325                 qcom,ipc = <&apcs 8 18>;
 326
 327                 qcom,local-pid = <0>;
 328                 qcom,remote-pid = <4>;
 329
 330                 wcnss_smp2p_out: master-kernel {
 331                         qcom,entry-name = "master-kernel";
 332
 333                         #qcom,smem-state-cells = <1>;
 334                 };
 335
 336                 wcnss_smp2p_in: slave-kernel {
 337                         qcom,entry-name = "slave-kernel";
 338
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                 };
 342         };
 343
 344         smsm {
 345                 compatible = "qcom,smsm";
 346
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349
 350                 qcom,ipc-1 = <&apcs 8 13>;
 351                 qcom,ipc-2 = <&apcs 8 9>;
 352                 qcom,ipc-3 = <&apcs 8 19>;
 353
 354                 apps_smsm: apps@0 {
 355                         reg = <0>;
 356
 357                         #qcom,smem-state-cells = <1>;
 358                 };
 359
 360                 modem_smsm: modem@1 {
 361                         reg = <1>;
 362                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 363
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                 };
 367
 368                 adsp_smsm: adsp@2 {
 369                         reg = <2>;
 370                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 371
 372                         interrupt-controller;
 373                         #interrupt-cells = <2>;
 374                 };
 375
 376                 wcnss_smsm: wcnss@7 {
 377                         reg = <7>;
 378                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 379
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                 };
 383         };
 384
 385         firmware {
 386                 scm {
 387                         compatible = "qcom,scm";
 388                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 389                         clock-names = "core", "bus", "iface";
 390                 };
 391         };
 392
 393         soc: soc {
 394                 #address-cells = <1>;
 395                 #size-cells = <1>;
 396                 ranges;
 397                 compatible = "simple-bus";
 398
 399                 intc: interrupt-controller@f9000000 {
 400                         compatible = "qcom,msm-qgic2";
 401                         interrupt-controller;
 402                         #interrupt-cells = <3>;
 403                         reg = <0xf9000000 0x1000>,
 404                               <0xf9002000 0x1000>;
 405                 };
 406
 407                 apcs: syscon@f9011000 {
 408                         compatible = "syscon";
 409                         reg = <0xf9011000 0x1000>;
 410                 };
 411
 412                 qfprom: qfprom@fc4bc000 {
 413                         #address-cells = <1>;
 414                         #size-cells = <1>;
 415                         compatible = "qcom,qfprom";
 416                         reg = <0xfc4bc000 0x1000>;
 417                         tsens_calib: calib@d0 {
 418                                 reg = <0xd0 0x18>;
 419                         };
 420                         tsens_backup: backup@440 {
 421                                 reg = <0x440 0x10>;
 422                         };
 423                 };
 424
 425                 tsens: thermal-sensor@fc4a8000 {
 426                         compatible = "qcom,msm8974-tsens";
 427                         reg = <0xfc4a8000 0x2000>;
 428                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 429                         nvmem-cell-names = "calib", "calib_backup";
 430                         #thermal-sensor-cells = <1>;
 431                 };
 432
 433                 timer@f9020000 {
 434                         #address-cells = <1>;
 435                         #size-cells = <1>;
 436                         ranges;
 437                         compatible = "arm,armv7-timer-mem";
 438                         reg = <0xf9020000 0x1000>;
 439                         clock-frequency = <19200000>;
 440
 441                         frame@f9021000 {
 442                                 frame-number = <0>;
 443                                 interrupts = <0 8 0x4>,
 444                                              <0 7 0x4>;
 445                                 reg = <0xf9021000 0x1000>,
 446                                       <0xf9022000 0x1000>;
 447                         };
 448
 449                         frame@f9023000 {
 450                                 frame-number = <1>;
 451                                 interrupts = <0 9 0x4>;
 452                                 reg = <0xf9023000 0x1000>;
 453                                 status = "disabled";
 454                         };
 455
 456                         frame@f9024000 {
 457                                 frame-number = <2>;
 458                                 interrupts = <0 10 0x4>;
 459                                 reg = <0xf9024000 0x1000>;
 460                                 status = "disabled";
 461                         };
 462
 463                         frame@f9025000 {
 464                                 frame-number = <3>;
 465                                 interrupts = <0 11 0x4>;
 466                                 reg = <0xf9025000 0x1000>;
 467                                 status = "disabled";
 468                         };
 469
 470                         frame@f9026000 {
 471                                 frame-number = <4>;
 472                                 interrupts = <0 12 0x4>;
 473                                 reg = <0xf9026000 0x1000>;
 474                                 status = "disabled";
 475                         };
 476
 477                         frame@f9027000 {
 478                                 frame-number = <5>;
 479                                 interrupts = <0 13 0x4>;
 480                                 reg = <0xf9027000 0x1000>;
 481                                 status = "disabled";
 482                         };
 483
 484                         frame@f9028000 {
 485                                 frame-number = <6>;
 486                                 interrupts = <0 14 0x4>;
 487                                 reg = <0xf9028000 0x1000>;
 488                                 status = "disabled";
 489                         };
 490                 };
 491
 492                 saw0: power-controller@f9089000 {
 493                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 494                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 495                 };
 496
 497                 saw1: power-controller@f9099000 {
 498                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 499                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 500                 };
 501
 502                 saw2: power-controller@f90a9000 {
 503                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 504                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 505                 };
 506
 507                 saw3: power-controller@f90b9000 {
 508                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 509                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 510                 };
 511
 512                 saw_l2: power-controller@f9012000 {
 513                         compatible = "qcom,saw2";
 514                         reg = <0xf9012000 0x1000>;
 515                         regulator;
 516                 };
 517
 518                 acc0: clock-controller@f9088000 {
 519                         compatible = "qcom,kpss-acc-v2";
 520                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 521                 };
 522
 523                 acc1: clock-controller@f9098000 {
 524                         compatible = "qcom,kpss-acc-v2";
 525                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 526                 };
 527
 528                 acc2: clock-controller@f90a8000 {
 529                         compatible = "qcom,kpss-acc-v2";
 530                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 531                 };
 532
 533                 acc3: clock-controller@f90b8000 {
 534                         compatible = "qcom,kpss-acc-v2";
 535                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 536                 };
 537
 538                 restart@fc4ab000 {
 539                         compatible = "qcom,pshold";
 540                         reg = <0xfc4ab000 0x4>;
 541                 };
 542
 543                 gcc: clock-controller@fc400000 {
 544                         compatible = "qcom,gcc-msm8974";
 545                         #clock-cells = <1>;
 546                         #reset-cells = <1>;
 547                         #power-domain-cells = <1>;
 548                         reg = <0xfc400000 0x4000>;
 549                 };
 550
 551                 tcsr_mutex_block: syscon@fd484000 {
 552                         compatible = "syscon";
 553                         reg = <0xfd484000 0x2000>;
 554                 };
 555
 556                 mmcc: clock-controller@fd8c0000 {
 557                         compatible = "qcom,mmcc-msm8974";
 558                         #clock-cells = <1>;
 559                         #reset-cells = <1>;
 560                         #power-domain-cells = <1>;
 561                         reg = <0xfd8c0000 0x6000>;
 562                 };
 563
 564                 tcsr_mutex: tcsr-mutex {
 565                         compatible = "qcom,tcsr-mutex";
 566                         syscon = <&tcsr_mutex_block 0 0x80>;
 567
 568                         #hwlock-cells = <1>;
 569                 };
 570
 571                 rpm_msg_ram: memory@fc428000 {
 572                         compatible = "qcom,rpm-msg-ram";
 573                         reg = <0xfc428000 0x4000>;
 574                 };
 575
 576                 blsp1_uart1: serial@f991d000 {
 577                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 578                         reg = <0xf991d000 0x1000>;
 579                         interrupts = <0 107 0x0>;
 580                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 581                         clock-names = "core", "iface";
 582                         status = "disabled";
 583                 };
 584
 585                 blsp1_uart2: serial@f991e000 {
 586                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 587                         reg = <0xf991e000 0x1000>;
 588                         interrupts = <0 108 0x0>;
 589                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 590                         clock-names = "core", "iface";
 591                         status = "disabled";
 592                 };
 593
 594                 sdhci@f9824900 {
 595                         compatible = "qcom,sdhci-msm-v4";
 596                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 597                         reg-names = "hc_mem", "core_mem";
 598                         interrupts = <0 123 0>, <0 138 0>;
 599                         interrupt-names = "hc_irq", "pwr_irq";
 600                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 601                                  <&gcc GCC_SDCC1_AHB_CLK>,
 602                                  <&xo_board>;
 603                         clock-names = "core", "iface", "xo";
 604                         status = "disabled";
 605                 };
 606
 607                 sdhci@f98a4900 {
 608                         compatible = "qcom,sdhci-msm-v4";
 609                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 610                         reg-names = "hc_mem", "core_mem";
 611                         interrupts = <0 125 0>, <0 221 0>;
 612                         interrupt-names = "hc_irq", "pwr_irq";
 613                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 614                                  <&gcc GCC_SDCC2_AHB_CLK>,
 615                                  <&xo_board>;
 616                         clock-names = "core", "iface", "xo";
 617                         status = "disabled";
 618                 };
 619
 620                 rng@f9bff000 {
 621                         compatible = "qcom,prng";
 622                         reg = <0xf9bff000 0x200>;
 623                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 624                         clock-names = "core";
 625                 };
 626
 627                 msmgpio: pinctrl@fd510000 {
 628                         compatible = "qcom,msm8974-pinctrl";
 629                         reg = <0xfd510000 0x4000>;
 630                         gpio-controller;
 631                         #gpio-cells = <2>;
 632                         interrupt-controller;
 633                         #interrupt-cells = <2>;
 634                         interrupts = <0 208 0>;
 635                 };
 636
 637                 i2c@f9924000 {
 638                         status = "disabled";
 639                         compatible = "qcom,i2c-qup-v2.1.1";
 640                         reg = <0xf9924000 0x1000>;
 641                         interrupts = <0 96 IRQ_TYPE_NONE>;
 642                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 643                         clock-names = "core", "iface";
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                 };
 647
 648                 blsp_i2c8: i2c@f9964000 {
 649                         status = "disabled";
 650                         compatible = "qcom,i2c-qup-v2.1.1";
 651                         reg = <0xf9964000 0x1000>;
 652                         interrupts = <0 102 IRQ_TYPE_NONE>;
 653                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 654                         clock-names = "core", "iface";
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                 };
 658
 659                 blsp_i2c11: i2c@f9967000 {
 660                         status = "disabled";
 661                         compatible = "qcom,i2c-qup-v2.1.1";
 662                         reg = <0xf9967000 0x1000>;
 663                         interrupts = <0 105 IRQ_TYPE_NONE>;
 664                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 665                         clock-names = "core", "iface";
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 669                         dma-names = "tx", "rx";
 670                 };
 671
 672                 spmi_bus: spmi@fc4cf000 {
 673                         compatible = "qcom,spmi-pmic-arb";
 674                         reg-names = "core", "intr", "cnfg";
 675                         reg = <0xfc4cf000 0x1000>,
 676                               <0xfc4cb000 0x1000>,
 677                               <0xfc4ca000 0x1000>;
 678                         interrupt-names = "periph_irq";
 679                         interrupts = <0 190 0>;
 680                         qcom,ee = <0>;
 681                         qcom,channel = <0>;
 682                         #address-cells = <2>;
 683                         #size-cells = <0>;
 684                         interrupt-controller;
 685                         #interrupt-cells = <4>;
 686                 };
 687
 688                 blsp2_dma: dma-controller@f9944000 {
 689                         compatible = "qcom,bam-v1.4.0";
 690                         reg = <0xf9944000 0x19000>;
 691                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 693                         clock-names = "bam_clk";
 694                         #dma-cells = <1>;
 695                         qcom,ee = <0>;
 696                 };
 697
 698                 usb1_phy: usb-phy@f9a55000 {
 699                         compatible = "qcom,usb-otg-snps";
 700
 701                         reg = <0xf9a55000 0x400>;
 702                         interrupts-extended = <&intc 0 134 0>, <&intc 0 140 0>,
 703                                 <&spmi_bus 0 0x9 0 0>;
 704                         interrupt-names = "core_irq", "async_irq", "pmic_id_irq";
 705
 706                         vddcx-supply = <&pm8841_s2>;
 707                         v3p3-supply = <&pm8941_l24>;
 708                         v1p8-supply = <&pm8941_l6>;
 709
 710                         dr_mode = "otg";
 711                         qcom,phy-init-sequence = <0x63 0x81 0xfffffff>;
 712                         qcom,otg-control = <1>;
 713                         qcom,phy-num = <0>;
 714
 715                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
 716                         reset-names = "phy", "link";
 717
 718                         clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
 719                                 <&gcc GCC_USB_HS_AHB_CLK>;
 720                         clock-names = "phy", "core", "iface";
 721
 722                         status = "disabled";
 723                 };
 724
 725                 usb@f9a55000 {
 726                         compatible = "qcom,ci-hdrc";
 727                         reg = <0xf9a55000 0x400>;
 728                         dr_mode = "otg";
 729                         interrupts = <0 134 0>, <0 140 0>;
 730                         interrupt-names = "core_irq", "async_irq";
 731                         usb-phy = <&usb1_phy>;
 732
 733                         status = "disabled";
 734                 };
 735         };
 736
 737         smd {
 738                 compatible = "qcom,smd";
 739
 740                 adsp {
 741                         interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
 742
 743                         qcom,ipc = <&apcs 8 8>;
 744                         qcom,smd-edge = <1>;
 745                 };
 746
 747                 modem {
 748                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 749
 750                         qcom,ipc = <&apcs 8 12>;
 751                         qcom,smd-edge = <0>;
 752                 };
 753
 754                 rpm {
 755                         interrupts = <0 168 1>;
 756                         qcom,ipc = <&apcs 8 0>;
 757                         qcom,smd-edge = <15>;
 758
 759                         rpm_requests {
 760                                 compatible = "qcom,rpm-msm8974";
 761                                 qcom,smd-channels = "rpm_requests";
 762
 763                                 pm8841-regulators {
 764                                         compatible = "qcom,rpm-pm8841-regulators";
 765
 766                                         pm8841_s1: s1 {};
 767                                         pm8841_s2: s2 {};
 768                                         pm8841_s3: s3 {};
 769                                         pm8841_s4: s4 {};
 770                                         pm8841_s5: s5 {};
 771                                         pm8841_s6: s6 {};
 772                                         pm8841_s7: s7 {};
 773                                         pm8841_s8: s8 {};
 774                                 };
 775
 776                                 pm8941-regulators {
 777                                         compatible = "qcom,rpm-pm8941-regulators";
 778
 779                                         pm8941_s1: s1 {};
 780                                         pm8941_s2: s2 {};
 781                                         pm8941_s3: s3 {};
 782                                         pm8941_5v: s4 {};
 783
 784                                         pm8941_l1: l1 {};
 785                                         pm8941_l2: l2 {};
 786                                         pm8941_l3: l3 {};
 787                                         pm8941_l4: l4 {};
 788                                         pm8941_l5: l5 {};
 789                                         pm8941_l6: l6 {};
 790                                         pm8941_l7: l7 {};
 791                                         pm8941_l8: l8 {};
 792                                         pm8941_l9: l9 {};
 793                                         pm8941_l10: l10 {};
 794                                         pm8941_l11: l11 {};
 795                                         pm8941_l12: l12 {};
 796                                         pm8941_l13: l13 {};
 797                                         pm8941_l14: l14 {};
 798                                         pm8941_l15: l15 {};
 799                                         pm8941_l16: l16 {};
 800                                         pm8941_l17: l17 {};
 801                                         pm8941_l18: l18 {};
 802                                         pm8941_l19: l19 {};
 803                                         pm8941_l20: l20 {};
 804                                         pm8941_l21: l21 {};
 805                                         pm8941_l22: l22 {};
 806                                         pm8941_l23: l23 {};
 807                                         pm8941_l24: l24 {};
 808
 809                                         pm8941_lvs1: lvs1 {};
 810                                         pm8941_lvs2: lvs2 {};
 811                                         pm8941_lvs3: lvs3 {};
 812
 813                                         pm8941_5vs1: 5vs1 {};
 814                                         pm8941_5vs2: 5vs2 {};
 815                                 };
 816                         };
 817                 };
 818         };
 819
 820         vreg_boost: vreg-boost {
 821                 compatible = "regulator-fixed";
 822
 823                 regulator-name = "vreg-boost";
 824                 regulator-min-microvolt = <3150000>;
 825                 regulator-max-microvolt = <3150000>;
 826
 827                 regulator-always-on;
 828                 regulator-boot-on;
 829
 830                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
 831                 enable-active-high;
 832
 833                 pinctrl-names = "default";
 834                 pinctrl-0 = <&boost_bypass_n_pin>;
 835         };
 836         vreg_vph_pwr: vreg-vph-pwr {
 837                 compatible = "regulator-fixed";
 838                 regulator-name = "vph-pwr";
 839
 840                 regulator-min-microvolt = <3600000>;
 841                 regulator-max-microvolt = <3600000>;
 842
 843                 regulator-always-on;
 844         };
 845 };