arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include <dt-bindings/clock/qcom,rpmcc.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         model = "Qualcomm MSM8974";
  12         compatible = "qcom,msm8974";
  13         interrupt-parent = <&intc>;
  14
  15         reserved-memory {
  16                 #address-cells = <1>;
  17                 #size-cells = <1>;
  18                 ranges;
  19
  20                 mpss@08000000 {
  21                         reg = <0x08000000 0x5100000>;
  22                         no-map;
  23                 };
  24
  25                 mba@00d100000 {
  26                         reg = <0x0d100000 0x100000>;
  27                         no-map;
  28                 };
  29
  30                 reserved@0d200000 {
  31                         reg = <0x0d200000 0xa00000>;
  32                         no-map;
  33                 };
  34
  35                 adsp_region: adsp@0dc00000 {
  36                         reg = <0x0dc00000 0x1900000>;
  37                         no-map;
  38                 };
  39
  40                 venus@0f500000 {
  41                         reg = <0x0f500000 0x500000>;
  42                         no-map;
  43                 };
  44
  45                 smem_region: smem@fa00000 {
  46                         reg = <0xfa00000 0x200000>;
  47                         no-map;
  48                 };
  49
  50                 tz@0fc00000 {
  51                         reg = <0x0fc00000 0x160000>;
  52                         no-map;
  53                 };
  54
  55                 rfsa@0fd60000 {
  56                         reg = <0x0fd60000 0x20000>;
  57                         no-map;
  58                 };
  59
  60                 rmtfs@0fd80000 {
  61                         reg = <0x0fd80000 0x180000>;
  62                         no-map;
  63                 };
  64         };
  65
  66         cpus {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 interrupts = <1 9 0xf04>;
  70
  71                 CPU0: cpu@0 {
  72                         compatible = "qcom,krait";
  73                         enable-method = "qcom,kpss-acc-v2";
  74                         device_type = "cpu";
  75                         reg = <0>;
  76                         next-level-cache = <&L2>;
  77                         qcom,acc = <&acc0>;
  78                         qcom,saw = <&saw0>;
  79                         cpu-idle-states = <&CPU_SPC>;
  80                 };
  81
  82                 CPU1: cpu@1 {
  83                         compatible = "qcom,krait";
  84                         enable-method = "qcom,kpss-acc-v2";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                         next-level-cache = <&L2>;
  88                         qcom,acc = <&acc1>;
  89                         qcom,saw = <&saw1>;
  90                         cpu-idle-states = <&CPU_SPC>;
  91                 };
  92
  93                 CPU2: cpu@2 {
  94                         compatible = "qcom,krait";
  95                         enable-method = "qcom,kpss-acc-v2";
  96                         device_type = "cpu";
  97                         reg = <2>;
  98                         next-level-cache = <&L2>;
  99                         qcom,acc = <&acc2>;
 100                         qcom,saw = <&saw2>;
 101                         cpu-idle-states = <&CPU_SPC>;
 102                 };
 103
 104                 CPU3: cpu@3 {
 105                         compatible = "qcom,krait";
 106                         enable-method = "qcom,kpss-acc-v2";
 107                         device_type = "cpu";
 108                         reg = <3>;
 109                         next-level-cache = <&L2>;
 110                         qcom,acc = <&acc3>;
 111                         qcom,saw = <&saw3>;
 112                         cpu-idle-states = <&CPU_SPC>;
 113                 };
 114
 115                 L2: l2-cache {
 116                         compatible = "cache";
 117                         cache-level = <2>;
 118                         qcom,saw = <&saw_l2>;
 119                 };
 120
 121                 idle-states {
 122                         CPU_SPC: spc {
 123                                 compatible = "qcom,idle-state-spc",
 124                                                 "arm,idle-state";
 125                                 entry-latency-us = <150>;
 126                                 exit-latency-us = <200>;
 127                                 min-residency-us = <2000>;
 128                         };
 129                 };
 130         };
 131
 132         thermal-zones {
 133                 cpu-thermal0 {
 134                         polling-delay-passive = <250>;
 135                         polling-delay = <1000>;
 136
 137                         thermal-sensors = <&tsens 5>;
 138
 139                         trips {
 140                                 cpu_alert0: trip0 {
 141                                         temperature = <75000>;
 142                                         hysteresis = <2000>;
 143                                         type = "passive";
 144                                 };
 145                                 cpu_crit0: trip1 {
 146                                         temperature = <110000>;
 147                                         hysteresis = <2000>;
 148                                         type = "critical";
 149                                 };
 150                         };
 151                 };
 152
 153                 cpu-thermal1 {
 154                         polling-delay-passive = <250>;
 155                         polling-delay = <1000>;
 156
 157                         thermal-sensors = <&tsens 6>;
 158
 159                         trips {
 160                                 cpu_alert1: trip0 {
 161                                         temperature = <75000>;
 162                                         hysteresis = <2000>;
 163                                         type = "passive";
 164                                 };
 165                                 cpu_crit1: trip1 {
 166                                         temperature = <110000>;
 167                                         hysteresis = <2000>;
 168                                         type = "critical";
 169                                 };
 170                         };
 171                 };
 172
 173                 cpu-thermal2 {
 174                         polling-delay-passive = <250>;
 175                         polling-delay = <1000>;
 176
 177                         thermal-sensors = <&tsens 7>;
 178
 179                         trips {
 180                                 cpu_alert2: trip0 {
 181                                         temperature = <75000>;
 182                                         hysteresis = <2000>;
 183                                         type = "passive";
 184                                 };
 185                                 cpu_crit2: trip1 {
 186                                         temperature = <110000>;
 187                                         hysteresis = <2000>;
 188                                         type = "critical";
 189                                 };
 190                         };
 191                 };
 192
 193                 cpu-thermal3 {
 194                         polling-delay-passive = <250>;
 195                         polling-delay = <1000>;
 196
 197                         thermal-sensors = <&tsens 8>;
 198
 199                         trips {
 200                                 cpu_alert3: trip0 {
 201                                         temperature = <75000>;
 202                                         hysteresis = <2000>;
 203                                         type = "passive";
 204                                 };
 205                                 cpu_crit3: trip1 {
 206                                         temperature = <110000>;
 207                                         hysteresis = <2000>;
 208                                         type = "critical";
 209                                 };
 210                         };
 211                 };
 212         };
 213
 214         cpu-pmu {
 215                 compatible = "qcom,krait-pmu";
 216                 interrupts = <1 7 0xf04>;
 217         };
 218
 219         clocks {
 220                 xo_board: xo_board {
 221                         compatible = "fixed-clock";
 222                         #clock-cells = <0>;
 223                         clock-frequency = <19200000>;
 224                 };
 225
 226                 sleep_clk: sleep_clk {
 227                         compatible = "fixed-clock";
 228                         #clock-cells = <0>;
 229                         clock-frequency = <32768>;
 230                 };
 231         };
 232
 233         timer {
 234                 compatible = "arm,armv7-timer";
 235                 interrupts = <1 2 0xf08>,
 236                              <1 3 0xf08>,
 237                              <1 4 0xf08>,
 238                              <1 1 0xf08>;
 239                 clock-frequency = <19200000>;
 240         };
 241
 242         adsp-pil {
 243                 compatible = "qcom,msm8974-adsp-pil";
 244
 245                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
 246                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 247                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 248                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 249                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 250                 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 251
 252                 cx-supply = <&pm8841_s2>;
 253
 254                 clocks = <&xo_board>;
 255                 clock-names = "xo";
 256
 257                 memory-region = <&adsp_region>;
 258
 259                 qcom,smem-states = <&adsp_smp2p_out 0>;
 260                 qcom,smem-state-names = "stop";
 261         };
 262
 263         smem {
 264                 compatible = "qcom,smem";
 265
 266                 memory-region = <&smem_region>;
 267                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 268
 269                 hwlocks = <&tcsr_mutex 3>;
 270         };
 271
 272         smp2p-adsp {
 273                 compatible = "qcom,smp2p";
 274                 qcom,smem = <443>, <429>;
 275
 276                 interrupt-parent = <&intc>;
 277                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 278
 279                 qcom,ipc = <&apcs 8 10>;
 280
 281                 qcom,local-pid = <0>;
 282                 qcom,remote-pid = <2>;
 283
 284                 adsp_smp2p_out: master-kernel {
 285                         qcom,entry-name = "master-kernel";
 286                         #qcom,smem-state-cells = <1>;
 287                 };
 288
 289                 adsp_smp2p_in: slave-kernel {
 290                         qcom,entry-name = "slave-kernel";
 291
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295         };
 296
 297         smp2p-modem {
 298                 compatible = "qcom,smp2p";
 299                 qcom,smem = <435>, <428>;
 300
 301                 interrupt-parent = <&intc>;
 302                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 303
 304                 qcom,ipc = <&apcs 8 14>;
 305
 306                 qcom,local-pid = <0>;
 307                 qcom,remote-pid = <1>;
 308
 309                 modem_smp2p_out: master-kernel {
 310                         qcom,entry-name = "master-kernel";
 311                         #qcom,smem-state-cells = <1>;
 312                 };
 313
 314                 modem_smp2p_in: slave-kernel {
 315                         qcom,entry-name = "slave-kernel";
 316
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320         };
 321
 322         smp2p-wcnss {
 323                 compatible = "qcom,smp2p";
 324                 qcom,smem = <451>, <431>;
 325
 326                 interrupt-parent = <&intc>;
 327                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 328
 329                 qcom,ipc = <&apcs 8 18>;
 330
 331                 qcom,local-pid = <0>;
 332                 qcom,remote-pid = <4>;
 333
 334                 wcnss_smp2p_out: master-kernel {
 335                         qcom,entry-name = "master-kernel";
 336
 337                         #qcom,smem-state-cells = <1>;
 338                 };
 339
 340                 wcnss_smp2p_in: slave-kernel {
 341                         qcom,entry-name = "slave-kernel";
 342
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                 };
 346         };
 347
 348         smsm {
 349                 compatible = "qcom,smsm";
 350
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353
 354                 qcom,ipc-1 = <&apcs 8 13>;
 355                 qcom,ipc-2 = <&apcs 8 9>;
 356                 qcom,ipc-3 = <&apcs 8 19>;
 357
 358                 apps_smsm: apps@0 {
 359                         reg = <0>;
 360
 361                         #qcom,smem-state-cells = <1>;
 362                 };
 363
 364                 modem_smsm: modem@1 {
 365                         reg = <1>;
 366                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 367
 368                         interrupt-controller;
 369                         #interrupt-cells = <2>;
 370                 };
 371
 372                 adsp_smsm: adsp@2 {
 373                         reg = <2>;
 374                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 375
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                 };
 379
 380                 wcnss_smsm: wcnss@7 {
 381                         reg = <7>;
 382                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 383
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                 };
 387         };
 388
 389         firmware {
 390                 scm {
 391                         compatible = "qcom,scm";
 392                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 393                         clock-names = "core", "bus", "iface";
 394                 };
 395         };
 396
 397         soc: soc {
 398                 #address-cells = <1>;
 399                 #size-cells = <1>;
 400                 ranges;
 401                 compatible = "simple-bus";
 402
 403                 intc: interrupt-controller@f9000000 {
 404                         compatible = "qcom,msm-qgic2";
 405                         interrupt-controller;
 406                         #interrupt-cells = <3>;
 407                         reg = <0xf9000000 0x1000>,
 408                               <0xf9002000 0x1000>;
 409                 };
 410
 411                 apcs: syscon@f9011000 {
 412                         compatible = "syscon";
 413                         reg = <0xf9011000 0x1000>;
 414                 };
 415
 416                 qfprom: qfprom@fc4bc000 {
 417                         #address-cells = <1>;
 418                         #size-cells = <1>;
 419                         compatible = "qcom,qfprom";
 420                         reg = <0xfc4bc000 0x1000>;
 421                         tsens_calib: calib@d0 {
 422                                 reg = <0xd0 0x18>;
 423                         };
 424                         tsens_backup: backup@440 {
 425                                 reg = <0x440 0x10>;
 426                         };
 427                 };
 428
 429                 tsens: thermal-sensor@fc4a8000 {
 430                         compatible = "qcom,msm8974-tsens";
 431                         reg = <0xfc4a8000 0x2000>;
 432                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 433                         nvmem-cell-names = "calib", "calib_backup";
 434                         #thermal-sensor-cells = <1>;
 435                 };
 436
 437                 timer@f9020000 {
 438                         #address-cells = <1>;
 439                         #size-cells = <1>;
 440                         ranges;
 441                         compatible = "arm,armv7-timer-mem";
 442                         reg = <0xf9020000 0x1000>;
 443                         clock-frequency = <19200000>;
 444
 445                         frame@f9021000 {
 446                                 frame-number = <0>;
 447                                 interrupts = <0 8 0x4>,
 448                                              <0 7 0x4>;
 449                                 reg = <0xf9021000 0x1000>,
 450                                       <0xf9022000 0x1000>;
 451                         };
 452
 453                         frame@f9023000 {
 454                                 frame-number = <1>;
 455                                 interrupts = <0 9 0x4>;
 456                                 reg = <0xf9023000 0x1000>;
 457                                 status = "disabled";
 458                         };
 459
 460                         frame@f9024000 {
 461                                 frame-number = <2>;
 462                                 interrupts = <0 10 0x4>;
 463                                 reg = <0xf9024000 0x1000>;
 464                                 status = "disabled";
 465                         };
 466
 467                         frame@f9025000 {
 468                                 frame-number = <3>;
 469                                 interrupts = <0 11 0x4>;
 470                                 reg = <0xf9025000 0x1000>;
 471                                 status = "disabled";
 472                         };
 473
 474                         frame@f9026000 {
 475                                 frame-number = <4>;
 476                                 interrupts = <0 12 0x4>;
 477                                 reg = <0xf9026000 0x1000>;
 478                                 status = "disabled";
 479                         };
 480
 481                         frame@f9027000 {
 482                                 frame-number = <5>;
 483                                 interrupts = <0 13 0x4>;
 484                                 reg = <0xf9027000 0x1000>;
 485                                 status = "disabled";
 486                         };
 487
 488                         frame@f9028000 {
 489                                 frame-number = <6>;
 490                                 interrupts = <0 14 0x4>;
 491                                 reg = <0xf9028000 0x1000>;
 492                                 status = "disabled";
 493                         };
 494                 };
 495
 496                 saw0: power-controller@f9089000 {
 497                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 498                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 499                 };
 500
 501                 saw1: power-controller@f9099000 {
 502                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 503                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 504                 };
 505
 506                 saw2: power-controller@f90a9000 {
 507                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 508                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 509                 };
 510
 511                 saw3: power-controller@f90b9000 {
 512                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 513                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 514                 };
 515
 516                 saw_l2: power-controller@f9012000 {
 517                         compatible = "qcom,saw2";
 518                         reg = <0xf9012000 0x1000>;
 519                         regulator;
 520                 };
 521
 522                 acc0: clock-controller@f9088000 {
 523                         compatible = "qcom,kpss-acc-v2";
 524                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 525                 };
 526
 527                 acc1: clock-controller@f9098000 {
 528                         compatible = "qcom,kpss-acc-v2";
 529                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 530                 };
 531
 532                 acc2: clock-controller@f90a8000 {
 533                         compatible = "qcom,kpss-acc-v2";
 534                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 535                 };
 536
 537                 acc3: clock-controller@f90b8000 {
 538                         compatible = "qcom,kpss-acc-v2";
 539                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 540                 };
 541
 542                 restart@fc4ab000 {
 543                         compatible = "qcom,pshold";
 544                         reg = <0xfc4ab000 0x4>;
 545                 };
 546
 547                 gcc: clock-controller@fc400000 {
 548                         compatible = "qcom,gcc-msm8974";
 549                         #clock-cells = <1>;
 550                         #reset-cells = <1>;
 551                         #power-domain-cells = <1>;
 552                         reg = <0xfc400000 0x4000>;
 553                 };
 554
 555                 tcsr: syscon@fd4a0000 {
 556                         compatible = "syscon";
 557                         reg = <0xfd4a0000 0x10000>;
 558                 };
 559
 560                 tcsr_mutex_block: syscon@fd484000 {
 561                         compatible = "syscon";
 562                         reg = <0xfd484000 0x2000>;
 563                 };
 564
 565                 mmcc: clock-controller@fd8c0000 {
 566                         compatible = "qcom,mmcc-msm8974";
 567                         #clock-cells = <1>;
 568                         #reset-cells = <1>;
 569                         #power-domain-cells = <1>;
 570                         reg = <0xfd8c0000 0x6000>;
 571                 };
 572
 573                 tcsr_mutex: tcsr-mutex {
 574                         compatible = "qcom,tcsr-mutex";
 575                         syscon = <&tcsr_mutex_block 0 0x80>;
 576
 577                         #hwlock-cells = <1>;
 578                 };
 579
 580                 rpm_msg_ram: memory@fc428000 {
 581                         compatible = "qcom,rpm-msg-ram";
 582                         reg = <0xfc428000 0x4000>;
 583                 };
 584
 585                 blsp1_uart1: serial@f991d000 {
 586                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 587                         reg = <0xf991d000 0x1000>;
 588                         interrupts = <0 107 0x0>;
 589                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 590                         clock-names = "core", "iface";
 591                         status = "disabled";
 592                 };
 593
 594                 blsp1_uart2: serial@f991e000 {
 595                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 596                         reg = <0xf991e000 0x1000>;
 597                         interrupts = <0 108 0x0>;
 598                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 599                         clock-names = "core", "iface";
 600                         status = "disabled";
 601                 };
 602
 603                 sdhci@f9824900 {
 604                         compatible = "qcom,sdhci-msm-v4";
 605                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 606                         reg-names = "hc_mem", "core_mem";
 607                         interrupts = <0 123 0>, <0 138 0>;
 608                         interrupt-names = "hc_irq", "pwr_irq";
 609                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 610                                  <&gcc GCC_SDCC1_AHB_CLK>,
 611                                  <&xo_board>;
 612                         clock-names = "core", "iface", "xo";
 613                         status = "disabled";
 614                 };
 615
 616                 sdhci@f98a4900 {
 617                         compatible = "qcom,sdhci-msm-v4";
 618                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 619                         reg-names = "hc_mem", "core_mem";
 620                         interrupts = <0 125 0>, <0 221 0>;
 621                         interrupt-names = "hc_irq", "pwr_irq";
 622                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 623                                  <&gcc GCC_SDCC2_AHB_CLK>,
 624                                  <&xo_board>;
 625                         clock-names = "core", "iface", "xo";
 626                         status = "disabled";
 627                 };
 628
 629                 otg: usb@f9a55000 {
 630                         compatible = "qcom,ci-hdrc";
 631                         reg = <0xf9a55000 0x200>,
 632                               <0xf9a55200 0x200>;
 633                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 635                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 636                         clock-names = "iface", "core";
 637                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 638                         assigned-clock-rates = <75000000>;
 639                         resets = <&gcc GCC_USB_HS_BCR>;
 640                         reset-names = "core";
 641                         phy_type = "ulpi";
 642                         dr_mode = "otg";
 643                         ahb-burst-config = <0>;
 644                         phy-names = "usb-phy";
 645                         status = "disabled";
 646                         #reset-cells = <1>;
 647
 648                         ulpi {
 649                                 usb_hs1_phy: phy@a {
 650                                         compatible = "qcom,usb-hs-phy-msm8974",
 651                                                      "qcom,usb-hs-phy";
 652                                         #phy-cells = <0>;
 653                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 654                                         clock-names = "ref", "sleep";
 655                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 656                                         reset-names = "phy", "por";
 657                                         status = "disabled";
 658                                 };
 659
 660                                 usb_hs2_phy: phy@b {
 661                                         compatible = "qcom,usb-hs-phy-msm8974",
 662                                                      "qcom,usb-hs-phy";
 663                                         #phy-cells = <0>;
 664                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
 665                                         clock-names = "ref", "sleep";
 666                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
 667                                         reset-names = "phy", "por";
 668                                         status = "disabled";
 669                                 };
 670                         };
 671                 };
 672
 673                 rng@f9bff000 {
 674                         compatible = "qcom,prng";
 675                         reg = <0xf9bff000 0x200>;
 676                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 677                         clock-names = "core";
 678                 };
 679
 680                 msmgpio: pinctrl@fd510000 {
 681                         compatible = "qcom,msm8974-pinctrl";
 682                         reg = <0xfd510000 0x4000>;
 683                         gpio-controller;
 684                         #gpio-cells = <2>;
 685                         interrupt-controller;
 686                         #interrupt-cells = <2>;
 687                         interrupts = <0 208 0>;
 688                 };
 689
 690                 i2c@f9924000 {
 691                         status = "disabled";
 692                         compatible = "qcom,i2c-qup-v2.1.1";
 693                         reg = <0xf9924000 0x1000>;
 694                         interrupts = <0 96 IRQ_TYPE_NONE>;
 695                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 696                         clock-names = "core", "iface";
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699                 };
 700
 701                 blsp_i2c8: i2c@f9964000 {
 702                         status = "disabled";
 703                         compatible = "qcom,i2c-qup-v2.1.1";
 704                         reg = <0xf9964000 0x1000>;
 705                         interrupts = <0 102 IRQ_TYPE_NONE>;
 706                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 707                         clock-names = "core", "iface";
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                 };
 711
 712                 blsp_i2c11: i2c@f9967000 {
 713                         status = "disabled";
 714                         compatible = "qcom,i2c-qup-v2.1.1";
 715                         reg = <0xf9967000 0x1000>;
 716                         interrupts = <0 105 IRQ_TYPE_NONE>;
 717                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 718                         clock-names = "core", "iface";
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 722                         dma-names = "tx", "rx";
 723                 };
 724
 725                 spmi_bus: spmi@fc4cf000 {
 726                         compatible = "qcom,spmi-pmic-arb";
 727                         reg-names = "core", "intr", "cnfg";
 728                         reg = <0xfc4cf000 0x1000>,
 729                               <0xfc4cb000 0x1000>,
 730                               <0xfc4ca000 0x1000>;
 731                         interrupt-names = "periph_irq";
 732                         interrupts = <0 190 0>;
 733                         qcom,ee = <0>;
 734                         qcom,channel = <0>;
 735                         #address-cells = <2>;
 736                         #size-cells = <0>;
 737                         interrupt-controller;
 738                         #interrupt-cells = <4>;
 739                 };
 740
 741                 blsp2_dma: dma-controller@f9944000 {
 742                         compatible = "qcom,bam-v1.4.0";
 743                         reg = <0xf9944000 0x19000>;
 744                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 745                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 746                         clock-names = "bam_clk";
 747                         #dma-cells = <1>;
 748                         qcom,ee = <0>;
 749                 };
 750
 751                 etr@fc322000 {
 752                         compatible = "arm,coresight-tmc", "arm,primecell";
 753                         reg = <0xfc322000 0x1000>;
 754
 755                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 756                         clock-names = "apb_pclk", "atclk";
 757
 758                         port {
 759                                 etr_in: endpoint {
 760                                         slave-mode;
 761                                         remote-endpoint = <&replicator_out0>;
 762                                 };
 763                         };
 764                 };
 765
 766                 tpiu@fc318000 {
 767                         compatible = "arm,coresight-tpiu", "arm,primecell";
 768                         reg = <0xfc318000 0x1000>;
 769
 770                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 771                         clock-names = "apb_pclk", "atclk";
 772
 773                         port {
 774                                 tpiu_in: endpoint {
 775                                          slave-mode;
 776                                          remote-endpoint = <&replicator_out1>;
 777                                  };
 778                         };
 779                 };
 780
 781                 replicator@fc31c000 {
 782                         compatible = "qcom,coresight-replicator1x", "arm,primecell";
 783                         reg = <0xfc31c000 0x1000>;
 784
 785                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 786                         clock-names = "apb_pclk", "atclk";
 787
 788                         ports {
 789                                 #address-cells = <1>;
 790                                 #size-cells = <0>;
 791
 792                                 port@0 {
 793                                         reg = <0>;
 794                                         replicator_out0: endpoint {
 795                                                 remote-endpoint = <&etr_in>;
 796                                         };
 797                                 };
 798                                 port@1 {
 799                                         reg = <1>;
 800                                         replicator_out1: endpoint {
 801                                                 remote-endpoint = <&tpiu_in>;
 802                                         };
 803                                 };
 804                                 port@2 {
 805                                         reg = <0>;
 806                                         replicator_in: endpoint {
 807                                                 slave-mode;
 808                                                 remote-endpoint = <&etf_out>;
 809                                         };
 810                                 };
 811                         };
 812                 };
 813
 814                 etf@fc307000 {
 815                         compatible = "arm,coresight-tmc", "arm,primecell";
 816                         reg = <0xfc307000 0x1000>;
 817
 818                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 819                         clock-names = "apb_pclk", "atclk";
 820
 821                         ports {
 822                                 #address-cells = <1>;
 823                                 #size-cells = <0>;
 824
 825                                 port@0 {
 826                                         reg = <0>;
 827                                         etf_out: endpoint {
 828                                                 remote-endpoint = <&replicator_in>;
 829                                         };
 830                                 };
 831                                 port@1 {
 832                                         reg = <0>;
 833                                         etf_in: endpoint {
 834                                                 slave-mode;
 835                                                 remote-endpoint = <&merger_out>;
 836                                         };
 837                                 };
 838                         };
 839                 };
 840
 841                 funnel@fc31b000 {
 842                         compatible = "arm,coresight-funnel", "arm,primecell";
 843                         reg = <0xfc31b000 0x1000>;
 844
 845                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 846                         clock-names = "apb_pclk", "atclk";
 847
 848                         ports {
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851
 852                                 /*
 853                                  * Not described input ports:
 854                                  * 0 - connected trought funnel to Audio, Modem and
 855                                  *     Resource and Power Manager CPU's
 856                                  * 2...7 - not-connected
 857                                  */
 858                                 port@1 {
 859                                         reg = <1>;
 860                                         merger_in1: endpoint {
 861                                                 slave-mode;
 862                                                 remote-endpoint = <&funnel1_out>;
 863                                         };
 864                                 };
 865                                 port@8 {
 866                                         reg = <0>;
 867                                         merger_out: endpoint {
 868                                                 remote-endpoint = <&etf_in>;
 869                                         };
 870                                 };
 871                         };
 872                 };
 873
 874                 funnel@fc31a000 {
 875                         compatible = "arm,coresight-funnel", "arm,primecell";
 876                         reg = <0xfc31a000 0x1000>;
 877
 878                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 879                         clock-names = "apb_pclk", "atclk";
 880
 881                         ports {
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884
 885                                 /*
 886                                  * Not described input ports:
 887                                  * 0 - not-connected
 888                                  * 1 - connected trought funnel to Multimedia CPU
 889                                  * 2 - connected to Wireless CPU
 890                                  * 3 - not-connected
 891                                  * 4 - not-connected
 892                                  * 6 - not-connected
 893                                  * 7 - connected to STM
 894                                  */
 895                                 port@5 {
 896                                         reg = <5>;
 897                                         funnel1_in5: endpoint {
 898                                                 slave-mode;
 899                                                 remote-endpoint = <&kpss_out>;
 900                                         };
 901                                 };
 902                                 port@8 {
 903                                         reg = <0>;
 904                                         funnel1_out: endpoint {
 905                                                 remote-endpoint = <&merger_in1>;
 906                                         };
 907                                 };
 908                         };
 909                 };
 910
 911                 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
 912                         compatible = "arm,coresight-funnel", "arm,primecell";
 913                         reg = <0xfc345000 0x1000>;
 914
 915                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 916                         clock-names = "apb_pclk", "atclk";
 917
 918                         ports {
 919                                 #address-cells = <1>;
 920                                 #size-cells = <0>;
 921
 922                                 port@0 {
 923                                         reg = <0>;
 924                                         kpss_in0: endpoint {
 925                                                 slave-mode;
 926                                                 remote-endpoint = <&etm0_out>;
 927                                         };
 928                                 };
 929                                 port@1 {
 930                                         reg = <1>;
 931                                         kpss_in1: endpoint {
 932                                                 slave-mode;
 933                                                 remote-endpoint = <&etm1_out>;
 934                                         };
 935                                 };
 936                                 port@2 {
 937                                         reg = <2>;
 938                                         kpss_in2: endpoint {
 939                                                 slave-mode;
 940                                                 remote-endpoint = <&etm2_out>;
 941                                         };
 942                                 };
 943                                 port@3 {
 944                                         reg = <3>;
 945                                         kpss_in3: endpoint {
 946                                                 slave-mode;
 947                                                 remote-endpoint = <&etm3_out>;
 948                                         };
 949                                 };
 950                                 port@8 {
 951                                         reg = <0>;
 952                                         kpss_out: endpoint {
 953                                                 remote-endpoint = <&funnel1_in5>;
 954                                         };
 955                                 };
 956                         };
 957                 };
 958
 959                 etm@fc33c000 {
 960                         compatible = "arm,coresight-etm4x", "arm,primecell";
 961                         reg = <0xfc33c000 0x1000>;
 962
 963                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 964                         clock-names = "apb_pclk", "atclk";
 965
 966                         cpu = <&CPU0>;
 967
 968                         port {
 969                                 etm0_out: endpoint {
 970                                         remote-endpoint = <&kpss_in0>;
 971                                 };
 972                         };
 973                 };
 974
 975                 etm@fc33d000 {
 976                         compatible = "arm,coresight-etm4x", "arm,primecell";
 977                         reg = <0xfc33d000 0x1000>;
 978
 979                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 980                         clock-names = "apb_pclk", "atclk";
 981
 982                         cpu = <&CPU1>;
 983
 984                         port {
 985                                 etm1_out: endpoint {
 986                                         remote-endpoint = <&kpss_in1>;
 987                                 };
 988                         };
 989                 };
 990
 991                 etm@fc33e000 {
 992                         compatible = "arm,coresight-etm4x", "arm,primecell";
 993                         reg = <0xfc33e000 0x1000>;
 994
 995                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 996                         clock-names = "apb_pclk", "atclk";
 997
 998                         cpu = <&CPU2>;
 999
1000                         port {
1001                                 etm2_out: endpoint {
1002                                         remote-endpoint = <&kpss_in2>;
1003                                 };
1004                         };
1005                 };
1006
1007                 etm@fc33f000 {
1008                         compatible = "arm,coresight-etm4x", "arm,primecell";
1009                         reg = <0xfc33f000 0x1000>;
1010
1011                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1012                         clock-names = "apb_pclk", "atclk";
1013
1014                         cpu = <&CPU3>;
1015
1016                         port {
1017                                 etm3_out: endpoint {
1018                                         remote-endpoint = <&kpss_in3>;
1019                                 };
1020                         };
1021                 };
1022         };
1023
1024         smd {
1025                 compatible = "qcom,smd";
1026
1027                 adsp {
1028                         interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
1029
1030                         qcom,ipc = <&apcs 8 8>;
1031                         qcom,smd-edge = <1>;
1032                 };
1033
1034                 modem {
1035                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1036
1037                         qcom,ipc = <&apcs 8 12>;
1038                         qcom,smd-edge = <0>;
1039                 };
1040
1041                 rpm {
1042                         interrupts = <0 168 1>;
1043                         qcom,ipc = <&apcs 8 0>;
1044                         qcom,smd-edge = <15>;
1045
1046                         rpm_requests {
1047                                 compatible = "qcom,rpm-msm8974";
1048                                 qcom,smd-channels = "rpm_requests";
1049
1050                                 rpmcc: clock-controller {
1051                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1052                                         #clock-cells = <1>;
1053                                 };
1054
1055                                 pm8841-regulators {
1056                                         compatible = "qcom,rpm-pm8841-regulators";
1057
1058                                         pm8841_s1: s1 {};
1059                                         pm8841_s2: s2 {};
1060                                         pm8841_s3: s3 {};
1061                                         pm8841_s4: s4 {};
1062                                         pm8841_s5: s5 {};
1063                                         pm8841_s6: s6 {};
1064                                         pm8841_s7: s7 {};
1065                                         pm8841_s8: s8 {};
1066                                 };
1067
1068                                 pm8941-regulators {
1069                                         compatible = "qcom,rpm-pm8941-regulators";
1070
1071                                         pm8941_s1: s1 {};
1072                                         pm8941_s2: s2 {};
1073                                         pm8941_s3: s3 {};
1074
1075                                         pm8941_l1: l1 {};
1076                                         pm8941_l2: l2 {};
1077                                         pm8941_l3: l3 {};
1078                                         pm8941_l4: l4 {};
1079                                         pm8941_l5: l5 {};
1080                                         pm8941_l6: l6 {};
1081                                         pm8941_l7: l7 {};
1082                                         pm8941_l8: l8 {};
1083                                         pm8941_l9: l9 {};
1084                                         pm8941_l10: l10 {};
1085                                         pm8941_l11: l11 {};
1086                                         pm8941_l12: l12 {};
1087                                         pm8941_l13: l13 {};
1088                                         pm8941_l14: l14 {};
1089                                         pm8941_l15: l15 {};
1090                                         pm8941_l16: l16 {};
1091                                         pm8941_l17: l17 {};
1092                                         pm8941_l18: l18 {};
1093                                         pm8941_l19: l19 {};
1094                                         pm8941_l20: l20 {};
1095                                         pm8941_l21: l21 {};
1096                                         pm8941_l22: l22 {};
1097                                         pm8941_l23: l23 {};
1098                                         pm8941_l24: l24 {};
1099
1100                                         pm8941_lvs1: lvs1 {};
1101                                         pm8941_lvs2: lvs2 {};
1102                                         pm8941_lvs3: lvs3 {};
1103                                 };
1104                         };
1105                 };
1106         };
1107
1108         vreg_boost: vreg-boost {
1109                 compatible = "regulator-fixed";
1110
1111                 regulator-name = "vreg-boost";
1112                 regulator-min-microvolt = <3150000>;
1113                 regulator-max-microvolt = <3150000>;
1114
1115                 regulator-always-on;
1116                 regulator-boot-on;
1117
1118                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1119                 enable-active-high;
1120
1121                 pinctrl-names = "default";
1122                 pinctrl-0 = <&boost_bypass_n_pin>;
1123         };
1124         vreg_vph_pwr: vreg-vph-pwr {
1125                 compatible = "regulator-fixed";
1126                 regulator-name = "vph-pwr";
1127
1128                 regulator-min-microvolt = <3600000>;
1129                 regulator-max-microvolt = <3600000>;
1130
1131                 regulator-always-on;
1132         };
1133 };