arch/arm/boot/dts/qcom-msm8974.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         model = "Qualcomm MSM8974";
  15         compatible = "qcom,msm8974";
  16         interrupt-parent = <&intc>;
  17
  18         reserved-memory {
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges;
  22
  23                 mpss@8000000 {
  24                         reg = <0x08000000 0x5100000>;
  25                         no-map;
  26                 };
  27
  28                 mba@d100000 {
  29                         reg = <0x0d100000 0x100000>;
  30                         no-map;
  31                 };
  32
  33                 reserved@d200000 {
  34                         reg = <0x0d200000 0xa00000>;
  35                         no-map;
  36                 };
  37
  38                 adsp_region: adsp@dc00000 {
  39                         reg = <0x0dc00000 0x1900000>;
  40                         no-map;
  41                 };
  42
  43                 venus@f500000 {
  44                         reg = <0x0f500000 0x500000>;
  45                         no-map;
  46                 };
  47
  48                 smem_region: smem@fa00000 {
  49                         reg = <0xfa00000 0x200000>;
  50                         no-map;
  51                 };
  52
  53                 tz@fc00000 {
  54                         reg = <0x0fc00000 0x160000>;
  55                         no-map;
  56                 };
  57
  58                 rfsa@fd60000 {
  59                         reg = <0x0fd60000 0x20000>;
  60                         no-map;
  61                 };
  62
  63                 rmtfs@fd80000 {
  64                         reg = <0x0fd80000 0x180000>;
  65                         no-map;
  66                 };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72                 interrupts = <GIC_PPI 9 0xf04>;
  73
  74                 CPU0: cpu@0 {
  75                         compatible = "qcom,krait";
  76                         enable-method = "qcom,kpss-acc-v2";
  77                         device_type = "cpu";
  78                         reg = <0>;
  79                         next-level-cache = <&L2>;
  80                         qcom,acc = <&acc0>;
  81                         qcom,saw = <&saw0>;
  82                         cpu-idle-states = <&CPU_SPC>;
  83                 };
  84
  85                 CPU1: cpu@1 {
  86                         compatible = "qcom,krait";
  87                         enable-method = "qcom,kpss-acc-v2";
  88                         device_type = "cpu";
  89                         reg = <1>;
  90                         next-level-cache = <&L2>;
  91                         qcom,acc = <&acc1>;
  92                         qcom,saw = <&saw1>;
  93                         cpu-idle-states = <&CPU_SPC>;
  94                 };
  95
  96                 CPU2: cpu@2 {
  97                         compatible = "qcom,krait";
  98                         enable-method = "qcom,kpss-acc-v2";
  99                         device_type = "cpu";
 100                         reg = <2>;
 101                         next-level-cache = <&L2>;
 102                         qcom,acc = <&acc2>;
 103                         qcom,saw = <&saw2>;
 104                         cpu-idle-states = <&CPU_SPC>;
 105                 };
 106
 107                 CPU3: cpu@3 {
 108                         compatible = "qcom,krait";
 109                         enable-method = "qcom,kpss-acc-v2";
 110                         device_type = "cpu";
 111                         reg = <3>;
 112                         next-level-cache = <&L2>;
 113                         qcom,acc = <&acc3>;
 114                         qcom,saw = <&saw3>;
 115                         cpu-idle-states = <&CPU_SPC>;
 116                 };
 117
 118                 L2: l2-cache {
 119                         compatible = "cache";
 120                         cache-level = <2>;
 121                         qcom,saw = <&saw_l2>;
 122                 };
 123
 124                 idle-states {
 125                         CPU_SPC: spc {
 126                                 compatible = "qcom,idle-state-spc",
 127                                                 "arm,idle-state";
 128                                 entry-latency-us = <150>;
 129                                 exit-latency-us = <200>;
 130                                 min-residency-us = <2000>;
 131                         };
 132                 };
 133         };
 134
 135         memory {
 136                 device_type = "memory";
 137                 reg = <0x0 0x0>;
 138         };
 139
 140         thermal-zones {
 141                 cpu-thermal0 {
 142                         polling-delay-passive = <250>;
 143                         polling-delay = <1000>;
 144
 145                         thermal-sensors = <&tsens 5>;
 146
 147                         trips {
 148                                 cpu_alert0: trip0 {
 149                                         temperature = <75000>;
 150                                         hysteresis = <2000>;
 151                                         type = "passive";
 152                                 };
 153                                 cpu_crit0: trip1 {
 154                                         temperature = <110000>;
 155                                         hysteresis = <2000>;
 156                                         type = "critical";
 157                                 };
 158                         };
 159                 };
 160
 161                 cpu-thermal1 {
 162                         polling-delay-passive = <250>;
 163                         polling-delay = <1000>;
 164
 165                         thermal-sensors = <&tsens 6>;
 166
 167                         trips {
 168                                 cpu_alert1: trip0 {
 169                                         temperature = <75000>;
 170                                         hysteresis = <2000>;
 171                                         type = "passive";
 172                                 };
 173                                 cpu_crit1: trip1 {
 174                                         temperature = <110000>;
 175                                         hysteresis = <2000>;
 176                                         type = "critical";
 177                                 };
 178                         };
 179                 };
 180
 181                 cpu-thermal2 {
 182                         polling-delay-passive = <250>;
 183                         polling-delay = <1000>;
 184
 185                         thermal-sensors = <&tsens 7>;
 186
 187                         trips {
 188                                 cpu_alert2: trip0 {
 189                                         temperature = <75000>;
 190                                         hysteresis = <2000>;
 191                                         type = "passive";
 192                                 };
 193                                 cpu_crit2: trip1 {
 194                                         temperature = <110000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200
 201                 cpu-thermal3 {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <1000>;
 204
 205                         thermal-sensors = <&tsens 8>;
 206
 207                         trips {
 208                                 cpu_alert3: trip0 {
 209                                         temperature = <75000>;
 210                                         hysteresis = <2000>;
 211                                         type = "passive";
 212                                 };
 213                                 cpu_crit3: trip1 {
 214                                         temperature = <110000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219                 };
 220
 221                 q6-dsp-thermal {
 222                         polling-delay-passive = <250>;
 223                         polling-delay = <1000>;
 224
 225                         thermal-sensors = <&tsens 1>;
 226
 227                         trips {
 228                                 q6_dsp_alert0: trip-point0 {
 229                                         temperature = <90000>;
 230                                         hysteresis = <2000>;
 231                                         type = "hot";
 232                                 };
 233                         };
 234                 };
 235
 236                 modemtx-thermal {
 237                         polling-delay-passive = <250>;
 238                         polling-delay = <1000>;
 239
 240                         thermal-sensors = <&tsens 2>;
 241
 242                         trips {
 243                                 modemtx_alert0: trip-point0 {
 244                                         temperature = <90000>;
 245                                         hysteresis = <2000>;
 246                                         type = "hot";
 247                                 };
 248                         };
 249                 };
 250
 251                 video-thermal {
 252                         polling-delay-passive = <250>;
 253                         polling-delay = <1000>;
 254
 255                         thermal-sensors = <&tsens 3>;
 256
 257                         trips {
 258                                 video_alert0: trip-point0 {
 259                                         temperature = <95000>;
 260                                         hysteresis = <2000>;
 261                                         type = "hot";
 262                                 };
 263                         };
 264                 };
 265
 266                 wlan-thermal {
 267                         polling-delay-passive = <250>;
 268                         polling-delay = <1000>;
 269
 270                         thermal-sensors = <&tsens 4>;
 271
 272                         trips {
 273                                 wlan_alert0: trip-point0 {
 274                                         temperature = <105000>;
 275                                         hysteresis = <2000>;
 276                                         type = "hot";
 277                                 };
 278                         };
 279                 };
 280
 281                 gpu-thermal-top {
 282                         polling-delay-passive = <250>;
 283                         polling-delay = <1000>;
 284
 285                         thermal-sensors = <&tsens 9>;
 286
 287                         trips {
 288                                 gpu1_alert0: trip-point0 {
 289                                         temperature = <90000>;
 290                                         hysteresis = <2000>;
 291                                         type = "hot";
 292                                 };
 293                         };
 294                 };
 295
 296                 gpu-thermal-bottom {
 297                         polling-delay-passive = <250>;
 298                         polling-delay = <1000>;
 299
 300                         thermal-sensors = <&tsens 10>;
 301
 302                         trips {
 303                                 gpu2_alert0: trip-point0 {
 304                                         temperature = <90000>;
 305                                         hysteresis = <2000>;
 306                                         type = "hot";
 307                                 };
 308                         };
 309                 };
 310         };
 311
 312         cpu-pmu {
 313                 compatible = "qcom,krait-pmu";
 314                 interrupts = <GIC_PPI 7 0xf04>;
 315         };
 316
 317         clocks {
 318                 xo_board: xo_board {
 319                         compatible = "fixed-clock";
 320                         #clock-cells = <0>;
 321                         clock-frequency = <19200000>;
 322                 };
 323
 324                 sleep_clk: sleep_clk {
 325                         compatible = "fixed-clock";
 326                         #clock-cells = <0>;
 327                         clock-frequency = <32768>;
 328                 };
 329         };
 330
 331         timer {
 332                 compatible = "arm,armv7-timer";
 333                 interrupts = <GIC_PPI 2 0xf08>,
 334                              <GIC_PPI 3 0xf08>,
 335                              <GIC_PPI 4 0xf08>,
 336                              <GIC_PPI 1 0xf08>;
 337                 clock-frequency = <19200000>;
 338         };
 339
 340         adsp-pil {
 341                 compatible = "qcom,msm8974-adsp-pil";
 342
 343                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 344                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 345                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 346                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 347                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 348                 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 349
 350                 cx-supply = <&pm8841_s2>;
 351
 352                 clocks = <&xo_board>;
 353                 clock-names = "xo";
 354
 355                 memory-region = <&adsp_region>;
 356
 357                 qcom,smem-states = <&adsp_smp2p_out 0>;
 358                 qcom,smem-state-names = "stop";
 359         };
 360
 361         smem {
 362                 compatible = "qcom,smem";
 363
 364                 memory-region = <&smem_region>;
 365                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 366
 367                 hwlocks = <&tcsr_mutex 3>;
 368         };
 369
 370         smp2p-adsp {
 371                 compatible = "qcom,smp2p";
 372                 qcom,smem = <443>, <429>;
 373
 374                 interrupt-parent = <&intc>;
 375                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 376
 377                 qcom,ipc = <&apcs 8 10>;
 378
 379                 qcom,local-pid = <0>;
 380                 qcom,remote-pid = <2>;
 381
 382                 adsp_smp2p_out: master-kernel {
 383                         qcom,entry-name = "master-kernel";
 384                         #qcom,smem-state-cells = <1>;
 385                 };
 386
 387                 adsp_smp2p_in: slave-kernel {
 388                         qcom,entry-name = "slave-kernel";
 389
 390                         interrupt-controller;
 391                         #interrupt-cells = <2>;
 392                 };
 393         };
 394
 395         smp2p-modem {
 396                 compatible = "qcom,smp2p";
 397                 qcom,smem = <435>, <428>;
 398
 399                 interrupt-parent = <&intc>;
 400                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 401
 402                 qcom,ipc = <&apcs 8 14>;
 403
 404                 qcom,local-pid = <0>;
 405                 qcom,remote-pid = <1>;
 406
 407                 modem_smp2p_out: master-kernel {
 408                         qcom,entry-name = "master-kernel";
 409                         #qcom,smem-state-cells = <1>;
 410                 };
 411
 412                 modem_smp2p_in: slave-kernel {
 413                         qcom,entry-name = "slave-kernel";
 414
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418         };
 419
 420         smp2p-wcnss {
 421                 compatible = "qcom,smp2p";
 422                 qcom,smem = <451>, <431>;
 423
 424                 interrupt-parent = <&intc>;
 425                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 426
 427                 qcom,ipc = <&apcs 8 18>;
 428
 429                 qcom,local-pid = <0>;
 430                 qcom,remote-pid = <4>;
 431
 432                 wcnss_smp2p_out: master-kernel {
 433                         qcom,entry-name = "master-kernel";
 434
 435                         #qcom,smem-state-cells = <1>;
 436                 };
 437
 438                 wcnss_smp2p_in: slave-kernel {
 439                         qcom,entry-name = "slave-kernel";
 440
 441                         interrupt-controller;
 442                         #interrupt-cells = <2>;
 443                 };
 444         };
 445
 446         smsm {
 447                 compatible = "qcom,smsm";
 448
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451
 452                 qcom,ipc-1 = <&apcs 8 13>;
 453                 qcom,ipc-2 = <&apcs 8 9>;
 454                 qcom,ipc-3 = <&apcs 8 19>;
 455
 456                 apps_smsm: apps@0 {
 457                         reg = <0>;
 458
 459                         #qcom,smem-state-cells = <1>;
 460                 };
 461
 462                 modem_smsm: modem@1 {
 463                         reg = <1>;
 464                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 465
 466                         interrupt-controller;
 467                         #interrupt-cells = <2>;
 468                 };
 469
 470                 adsp_smsm: adsp@2 {
 471                         reg = <2>;
 472                         interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 473
 474                         interrupt-controller;
 475                         #interrupt-cells = <2>;
 476                 };
 477
 478                 wcnss_smsm: wcnss@7 {
 479                         reg = <7>;
 480                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 481
 482                         interrupt-controller;
 483                         #interrupt-cells = <2>;
 484                 };
 485         };
 486
 487         firmware {
 488                 scm {
 489                         compatible = "qcom,scm";
 490                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 491                         clock-names = "core", "bus", "iface";
 492                 };
 493         };
 494
 495         soc: soc {
 496                 #address-cells = <1>;
 497                 #size-cells = <1>;
 498                 ranges;
 499                 compatible = "simple-bus";
 500
 501                 intc: interrupt-controller@f9000000 {
 502                         compatible = "qcom,msm-qgic2";
 503                         interrupt-controller;
 504                         #interrupt-cells = <3>;
 505                         reg = <0xf9000000 0x1000>,
 506                               <0xf9002000 0x1000>;
 507                 };
 508
 509                 apcs: syscon@f9011000 {
 510                         compatible = "syscon";
 511                         reg = <0xf9011000 0x1000>;
 512                 };
 513
 514                 qfprom: qfprom@fc4bc000 {
 515                         #address-cells = <1>;
 516                         #size-cells = <1>;
 517                         compatible = "qcom,qfprom";
 518                         reg = <0xfc4bc000 0x1000>;
 519                         tsens_calib: calib@d0 {
 520                                 reg = <0xd0 0x18>;
 521                         };
 522                         tsens_backup: backup@440 {
 523                                 reg = <0x440 0x10>;
 524                         };
 525                 };
 526
 527                 tsens: thermal-sensor@fc4a9000 {
 528                         compatible = "qcom,msm8974-tsens";
 529                         reg = <0xfc4a9000 0x1000>, /* TM */
 530                               <0xfc4a8000 0x1000>; /* SROT */
 531                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 532                         nvmem-cell-names = "calib", "calib_backup";
 533                         #qcom,sensors = <11>;
 534                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 535                         interrupt-names = "uplow";
 536                         #thermal-sensor-cells = <1>;
 537                 };
 538
 539                 timer@f9020000 {
 540                         #address-cells = <1>;
 541                         #size-cells = <1>;
 542                         ranges;
 543                         compatible = "arm,armv7-timer-mem";
 544                         reg = <0xf9020000 0x1000>;
 545                         clock-frequency = <19200000>;
 546
 547                         frame@f9021000 {
 548                                 frame-number = <0>;
 549                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 550                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 551                                 reg = <0xf9021000 0x1000>,
 552                                       <0xf9022000 0x1000>;
 553                         };
 554
 555                         frame@f9023000 {
 556                                 frame-number = <1>;
 557                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 558                                 reg = <0xf9023000 0x1000>;
 559                                 status = "disabled";
 560                         };
 561
 562                         frame@f9024000 {
 563                                 frame-number = <2>;
 564                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 565                                 reg = <0xf9024000 0x1000>;
 566                                 status = "disabled";
 567                         };
 568
 569                         frame@f9025000 {
 570                                 frame-number = <3>;
 571                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 572                                 reg = <0xf9025000 0x1000>;
 573                                 status = "disabled";
 574                         };
 575
 576                         frame@f9026000 {
 577                                 frame-number = <4>;
 578                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 579                                 reg = <0xf9026000 0x1000>;
 580                                 status = "disabled";
 581                         };
 582
 583                         frame@f9027000 {
 584                                 frame-number = <5>;
 585                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 586                                 reg = <0xf9027000 0x1000>;
 587                                 status = "disabled";
 588                         };
 589
 590                         frame@f9028000 {
 591                                 frame-number = <6>;
 592                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 593                                 reg = <0xf9028000 0x1000>;
 594                                 status = "disabled";
 595                         };
 596                 };
 597
 598                 saw0: power-controller@f9089000 {
 599                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 600                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 601                 };
 602
 603                 saw1: power-controller@f9099000 {
 604                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 605                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 606                 };
 607
 608                 saw2: power-controller@f90a9000 {
 609                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 610                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 611                 };
 612
 613                 saw3: power-controller@f90b9000 {
 614                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 615                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 616                 };
 617
 618                 saw_l2: power-controller@f9012000 {
 619                         compatible = "qcom,saw2";
 620                         reg = <0xf9012000 0x1000>;
 621                         regulator;
 622                 };
 623
 624                 acc0: clock-controller@f9088000 {
 625                         compatible = "qcom,kpss-acc-v2";
 626                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 627                 };
 628
 629                 acc1: clock-controller@f9098000 {
 630                         compatible = "qcom,kpss-acc-v2";
 631                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 632                 };
 633
 634                 acc2: clock-controller@f90a8000 {
 635                         compatible = "qcom,kpss-acc-v2";
 636                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 637                 };
 638
 639                 acc3: clock-controller@f90b8000 {
 640                         compatible = "qcom,kpss-acc-v2";
 641                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 642                 };
 643
 644                 restart@fc4ab000 {
 645                         compatible = "qcom,pshold";
 646                         reg = <0xfc4ab000 0x4>;
 647                 };
 648
 649                 gcc: clock-controller@fc400000 {
 650                         compatible = "qcom,gcc-msm8974";
 651                         #clock-cells = <1>;
 652                         #reset-cells = <1>;
 653                         #power-domain-cells = <1>;
 654                         reg = <0xfc400000 0x4000>;
 655                 };
 656
 657                 tcsr: syscon@fd4a0000 {
 658                         compatible = "syscon";
 659                         reg = <0xfd4a0000 0x10000>;
 660                 };
 661
 662                 tcsr_mutex_block: syscon@fd484000 {
 663                         compatible = "syscon";
 664                         reg = <0xfd484000 0x2000>;
 665                 };
 666
 667                 mmcc: clock-controller@fd8c0000 {
 668                         compatible = "qcom,mmcc-msm8974";
 669                         #clock-cells = <1>;
 670                         #reset-cells = <1>;
 671                         #power-domain-cells = <1>;
 672                         reg = <0xfd8c0000 0x6000>;
 673                 };
 674
 675                 tcsr_mutex: tcsr-mutex {
 676                         compatible = "qcom,tcsr-mutex";
 677                         syscon = <&tcsr_mutex_block 0 0x80>;
 678
 679                         #hwlock-cells = <1>;
 680                 };
 681
 682                 rpm_msg_ram: memory@fc428000 {
 683                         compatible = "qcom,rpm-msg-ram";
 684                         reg = <0xfc428000 0x4000>;
 685                 };
 686
 687                 blsp1_uart1: serial@f991d000 {
 688                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 689                         reg = <0xf991d000 0x1000>;
 690                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 692                         clock-names = "core", "iface";
 693                         status = "disabled";
 694                 };
 695
 696                 blsp1_uart2: serial@f991e000 {
 697                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 698                         reg = <0xf991e000 0x1000>;
 699                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 700                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 701                         clock-names = "core", "iface";
 702                         status = "disabled";
 703                 };
 704
 705                 sdhci@f9824900 {
 706                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 707                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 708                         reg-names = "hc_mem", "core_mem";
 709                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 711                         interrupt-names = "hc_irq", "pwr_irq";
 712                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 713                                  <&gcc GCC_SDCC1_AHB_CLK>,
 714                                  <&xo_board>;
 715                         clock-names = "core", "iface", "xo";
 716                         status = "disabled";
 717                 };
 718
 719                 sdhci@f9864900 {
 720                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 721                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 722                         reg-names = "hc_mem", "core_mem";
 723                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 725                         interrupt-names = "hc_irq", "pwr_irq";
 726                         clocks = <&gcc GCC_SDCC3_APPS_CLK>,
 727                                  <&gcc GCC_SDCC3_AHB_CLK>,
 728                                  <&xo_board>;
 729                         clock-names = "core", "iface", "xo";
 730                         status = "disabled";
 731                 };
 732
 733                 sdhci@f98a4900 {
 734                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 735                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 736                         reg-names = "hc_mem", "core_mem";
 737                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 739                         interrupt-names = "hc_irq", "pwr_irq";
 740                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 741                                  <&gcc GCC_SDCC2_AHB_CLK>,
 742                                  <&xo_board>;
 743                         clock-names = "core", "iface", "xo";
 744                         status = "disabled";
 745                 };
 746
 747                 otg: usb@f9a55000 {
 748                         compatible = "qcom,ci-hdrc";
 749                         reg = <0xf9a55000 0x200>,
 750                               <0xf9a55200 0x200>;
 751                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 753                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 754                         clock-names = "iface", "core";
 755                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 756                         assigned-clock-rates = <75000000>;
 757                         resets = <&gcc GCC_USB_HS_BCR>;
 758                         reset-names = "core";
 759                         phy_type = "ulpi";
 760                         dr_mode = "otg";
 761                         ahb-burst-config = <0>;
 762                         phy-names = "usb-phy";
 763                         status = "disabled";
 764                         #reset-cells = <1>;
 765
 766                         ulpi {
 767                                 usb_hs1_phy: phy@a {
 768                                         compatible = "qcom,usb-hs-phy-msm8974",
 769                                                      "qcom,usb-hs-phy";
 770                                         #phy-cells = <0>;
 771                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 772                                         clock-names = "ref", "sleep";
 773                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 774                                         reset-names = "phy", "por";
 775                                         status = "disabled";
 776                                 };
 777
 778                                 usb_hs2_phy: phy@b {
 779                                         compatible = "qcom,usb-hs-phy-msm8974",
 780                                                      "qcom,usb-hs-phy";
 781                                         #phy-cells = <0>;
 782                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
 783                                         clock-names = "ref", "sleep";
 784                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
 785                                         reset-names = "phy", "por";
 786                                         status = "disabled";
 787                                 };
 788                         };
 789                 };
 790
 791                 rng@f9bff000 {
 792                         compatible = "qcom,prng";
 793                         reg = <0xf9bff000 0x200>;
 794                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 795                         clock-names = "core";
 796                 };
 797
 798                 msmgpio: pinctrl@fd510000 {
 799                         compatible = "qcom,msm8974-pinctrl";
 800                         reg = <0xfd510000 0x4000>;
 801                         gpio-controller;
 802                         #gpio-cells = <2>;
 803                         interrupt-controller;
 804                         #interrupt-cells = <2>;
 805                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 806                 };
 807
 808                 i2c@f9923000 {
 809                         status = "disabled";
 810                         compatible = "qcom,i2c-qup-v2.1.1";
 811                         reg = <0xf9923000 0x1000>;
 812                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 813                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 814                         clock-names = "core", "iface";
 815                         #address-cells = <1>;
 816                         #size-cells = <0>;
 817                 };
 818
 819                 i2c@f9924000 {
 820                         status = "disabled";
 821                         compatible = "qcom,i2c-qup-v2.1.1";
 822                         reg = <0xf9924000 0x1000>;
 823                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 825                         clock-names = "core", "iface";
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                 };
 829
 830                 blsp_i2c3: i2c@f9925000 {
 831                         status = "disabled";
 832                         compatible = "qcom,i2c-qup-v2.1.1";
 833                         reg = <0xf9925000 0x1000>;
 834                         interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 835                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 836                         clock-names = "core", "iface";
 837                         #address-cells = <1>;
 838                         #size-cells = <0>;
 839                 };
 840
 841                 blsp_i2c8: i2c@f9964000 {
 842                         status = "disabled";
 843                         compatible = "qcom,i2c-qup-v2.1.1";
 844                         reg = <0xf9964000 0x1000>;
 845                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 846                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 847                         clock-names = "core", "iface";
 848                         #address-cells = <1>;
 849                         #size-cells = <0>;
 850                 };
 851
 852                 blsp_i2c11: i2c@f9967000 {
 853                         status = "disabled";
 854                         compatible = "qcom,i2c-qup-v2.1.1";
 855                         reg = <0xf9967000 0x1000>;
 856                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 857                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 858                         clock-names = "core", "iface";
 859                         #address-cells = <1>;
 860                         #size-cells = <0>;
 861                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 862                         dma-names = "tx", "rx";
 863                 };
 864
 865                 blsp_i2c12: i2c@f9968000 {
 866                         status = "disabled";
 867                         compatible = "qcom,i2c-qup-v2.1.1";
 868                         reg = <0xf9968000 0x1000>;
 869                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 870                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 871                         clock-names = "core", "iface";
 872                         #address-cells = <1>;
 873                         #size-cells = <0>;
 874                 };
 875
 876                 spmi_bus: spmi@fc4cf000 {
 877                         compatible = "qcom,spmi-pmic-arb";
 878                         reg-names = "core", "intr", "cnfg";
 879                         reg = <0xfc4cf000 0x1000>,
 880                               <0xfc4cb000 0x1000>,
 881                               <0xfc4ca000 0x1000>;
 882                         interrupt-names = "periph_irq";
 883                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 884                         qcom,ee = <0>;
 885                         qcom,channel = <0>;
 886                         #address-cells = <2>;
 887                         #size-cells = <0>;
 888                         interrupt-controller;
 889                         #interrupt-cells = <4>;
 890                 };
 891
 892                 blsp2_dma: dma-controller@f9944000 {
 893                         compatible = "qcom,bam-v1.4.0";
 894                         reg = <0xf9944000 0x19000>;
 895                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 897                         clock-names = "bam_clk";
 898                         #dma-cells = <1>;
 899                         qcom,ee = <0>;
 900                 };
 901
 902                 etr@fc322000 {
 903                         compatible = "arm,coresight-tmc", "arm,primecell";
 904                         reg = <0xfc322000 0x1000>;
 905
 906                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 907                         clock-names = "apb_pclk", "atclk";
 908
 909                         in-ports {
 910                                 port {
 911                                         etr_in: endpoint {
 912                                                 remote-endpoint = <&replicator_out0>;
 913                                         };
 914                                 };
 915                         };
 916                 };
 917
 918                 tpiu@fc318000 {
 919                         compatible = "arm,coresight-tpiu", "arm,primecell";
 920                         reg = <0xfc318000 0x1000>;
 921
 922                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 923                         clock-names = "apb_pclk", "atclk";
 924
 925                         in-ports {
 926                                 port {
 927                                         tpiu_in: endpoint {
 928                                                 remote-endpoint = <&replicator_out1>;
 929                                         };
 930                                  };
 931                         };
 932                 };
 933
 934                 replicator@fc31c000 {
 935                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 936                         reg = <0xfc31c000 0x1000>;
 937
 938                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 939                         clock-names = "apb_pclk", "atclk";
 940
 941                         out-ports {
 942                                 #address-cells = <1>;
 943                                 #size-cells = <0>;
 944
 945                                 port@0 {
 946                                         reg = <0>;
 947                                         replicator_out0: endpoint {
 948                                                 remote-endpoint = <&etr_in>;
 949                                         };
 950                                 };
 951                                 port@1 {
 952                                         reg = <1>;
 953                                         replicator_out1: endpoint {
 954                                                 remote-endpoint = <&tpiu_in>;
 955                                         };
 956                                 };
 957                         };
 958
 959                         in-ports {
 960                                 port {
 961                                         replicator_in: endpoint {
 962                                                 remote-endpoint = <&etf_out>;
 963                                         };
 964                                 };
 965                         };
 966                 };
 967
 968                 etf@fc307000 {
 969                         compatible = "arm,coresight-tmc", "arm,primecell";
 970                         reg = <0xfc307000 0x1000>;
 971
 972                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 973                         clock-names = "apb_pclk", "atclk";
 974
 975                         out-ports {
 976                                 port {
 977                                         etf_out: endpoint {
 978                                                 remote-endpoint = <&replicator_in>;
 979                                         };
 980                                 };
 981                         };
 982
 983                         in-ports {
 984                                 port {
 985                                         etf_in: endpoint {
 986                                                 remote-endpoint = <&merger_out>;
 987                                         };
 988                                 };
 989                         };
 990                 };
 991
 992                 funnel@fc31b000 {
 993                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 994                         reg = <0xfc31b000 0x1000>;
 995
 996                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 997                         clock-names = "apb_pclk", "atclk";
 998
 999                         in-ports {
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002
1003                                 /*
1004                                  * Not described input ports:
1005                                  * 0 - connected trought funnel to Audio, Modem and
1006                                  *     Resource and Power Manager CPU's
1007                                  * 2...7 - not-connected
1008                                  */
1009                                 port@1 {
1010                                         reg = <1>;
1011                                         merger_in1: endpoint {
1012                                                 remote-endpoint = <&funnel1_out>;
1013                                         };
1014                                 };
1015                         };
1016
1017                         out-ports {
1018                                 port {
1019                                         merger_out: endpoint {
1020                                                 remote-endpoint = <&etf_in>;
1021                                         };
1022                                 };
1023                         };
1024                 };
1025
1026                 funnel@fc31a000 {
1027                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1028                         reg = <0xfc31a000 0x1000>;
1029
1030                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1031                         clock-names = "apb_pclk", "atclk";
1032
1033                         in-ports {
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036
1037                                 /*
1038                                  * Not described input ports:
1039                                  * 0 - not-connected
1040                                  * 1 - connected trought funnel to Multimedia CPU
1041                                  * 2 - connected to Wireless CPU
1042                                  * 3 - not-connected
1043                                  * 4 - not-connected
1044                                  * 6 - not-connected
1045                                  * 7 - connected to STM
1046                                  */
1047                                 port@5 {
1048                                         reg = <5>;
1049                                         funnel1_in5: endpoint {
1050                                                 remote-endpoint = <&kpss_out>;
1051                                         };
1052                                 };
1053                         };
1054
1055                         out-ports {
1056                                 port {
1057                                         funnel1_out: endpoint {
1058                                                 remote-endpoint = <&merger_in1>;
1059                                         };
1060                                 };
1061                         };
1062                 };
1063
1064                 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
1065                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1066                         reg = <0xfc345000 0x1000>;
1067
1068                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1069                         clock-names = "apb_pclk", "atclk";
1070
1071                         in-ports {
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074
1075                                 port@0 {
1076                                         reg = <0>;
1077                                         kpss_in0: endpoint {
1078                                                 remote-endpoint = <&etm0_out>;
1079                                         };
1080                                 };
1081                                 port@1 {
1082                                         reg = <1>;
1083                                         kpss_in1: endpoint {
1084                                                 remote-endpoint = <&etm1_out>;
1085                                         };
1086                                 };
1087                                 port@2 {
1088                                         reg = <2>;
1089                                         kpss_in2: endpoint {
1090                                                 remote-endpoint = <&etm2_out>;
1091                                         };
1092                                 };
1093                                 port@3 {
1094                                         reg = <3>;
1095                                         kpss_in3: endpoint {
1096                                                 remote-endpoint = <&etm3_out>;
1097                                         };
1098                                 };
1099                         };
1100
1101                         out-ports {
1102                                 port {
1103                                         kpss_out: endpoint {
1104                                                 remote-endpoint = <&funnel1_in5>;
1105                                         };
1106                                 };
1107                         };
1108                 };
1109
1110                 etm@fc33c000 {
1111                         compatible = "arm,coresight-etm4x", "arm,primecell";
1112                         reg = <0xfc33c000 0x1000>;
1113
1114                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1115                         clock-names = "apb_pclk", "atclk";
1116
1117                         cpu = <&CPU0>;
1118
1119                         out-ports {
1120                                 port {
1121                                         etm0_out: endpoint {
1122                                                 remote-endpoint = <&kpss_in0>;
1123                                         };
1124                                 };
1125                         };
1126                 };
1127
1128                 etm@fc33d000 {
1129                         compatible = "arm,coresight-etm4x", "arm,primecell";
1130                         reg = <0xfc33d000 0x1000>;
1131
1132                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1133                         clock-names = "apb_pclk", "atclk";
1134
1135                         cpu = <&CPU1>;
1136
1137                         out-ports {
1138                                 port {
1139                                         etm1_out: endpoint {
1140                                                 remote-endpoint = <&kpss_in1>;
1141                                         };
1142                                 };
1143                         };
1144                 };
1145
1146                 etm@fc33e000 {
1147                         compatible = "arm,coresight-etm4x", "arm,primecell";
1148                         reg = <0xfc33e000 0x1000>;
1149
1150                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1151                         clock-names = "apb_pclk", "atclk";
1152
1153                         cpu = <&CPU2>;
1154
1155                         out-ports {
1156                                 port {
1157                                         etm2_out: endpoint {
1158                                                 remote-endpoint = <&kpss_in2>;
1159                                         };
1160                                 };
1161                         };
1162                 };
1163
1164                 etm@fc33f000 {
1165                         compatible = "arm,coresight-etm4x", "arm,primecell";
1166                         reg = <0xfc33f000 0x1000>;
1167
1168                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1169                         clock-names = "apb_pclk", "atclk";
1170
1171                         cpu = <&CPU3>;
1172
1173                         out-ports {
1174                                 port {
1175                                         etm3_out: endpoint {
1176                                                 remote-endpoint = <&kpss_in3>;
1177                                         };
1178                                 };
1179                         };
1180                 };
1181
1182                 mdss: mdss@fd900000 {
1183                         status = "disabled";
1184
1185                         compatible = "qcom,mdss";
1186                         reg = <0xfd900000 0x100>,
1187                               <0xfd924000 0x1000>;
1188                         reg-names = "mdss_phys",
1189                                     "vbif_phys";
1190
1191                         power-domains = <&mmcc MDSS_GDSC>;
1192
1193                         clocks = <&mmcc MDSS_AHB_CLK>,
1194                                  <&mmcc MDSS_AXI_CLK>,
1195                                  <&mmcc MDSS_VSYNC_CLK>;
1196                         clock-names = "iface",
1197                                       "bus",
1198                                       "vsync";
1199
1200                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1201
1202                         interrupt-controller;
1203                         #interrupt-cells = <1>;
1204
1205                         #address-cells = <1>;
1206                         #size-cells = <1>;
1207                         ranges;
1208
1209                         mdp: mdp@fd900000 {
1210                                 status = "disabled";
1211
1212                                 compatible = "qcom,mdp5";
1213                                 reg = <0xfd900100 0x22000>;
1214                                 reg-names = "mdp_phys";
1215
1216                                 interrupt-parent = <&mdss>;
1217                                 interrupts = <0 0>;
1218
1219                                 clocks = <&mmcc MDSS_AHB_CLK>,
1220                                          <&mmcc MDSS_AXI_CLK>,
1221                                          <&mmcc MDSS_MDP_CLK>,
1222                                          <&mmcc MDSS_VSYNC_CLK>;
1223                                 clock-names = "iface",
1224                                               "bus",
1225                                               "core",
1226                                               "vsync";
1227
1228                                 ports {
1229                                         #address-cells = <1>;
1230                                         #size-cells = <0>;
1231
1232                                         port@0 {
1233                                                 reg = <0>;
1234                                                 mdp5_intf1_out: endpoint {
1235                                                         remote-endpoint = <&dsi0_in>;
1236                                                 };
1237                                         };
1238                                 };
1239                         };
1240
1241                         dsi0: dsi@fd922800 {
1242                                 status = "disabled";
1243
1244                                 compatible = "qcom,mdss-dsi-ctrl";
1245                                 reg = <0xfd922800 0x1f8>;
1246                                 reg-names = "dsi_ctrl";
1247
1248                                 interrupt-parent = <&mdss>;
1249                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1250
1251                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1252                                                   <&mmcc PCLK0_CLK_SRC>;
1253                                 assigned-clock-parents = <&dsi_phy0 0>,
1254                                                          <&dsi_phy0 1>;
1255
1256                                 clocks = <&mmcc MDSS_MDP_CLK>,
1257                                          <&mmcc MDSS_AHB_CLK>,
1258                                          <&mmcc MDSS_AXI_CLK>,
1259                                          <&mmcc MDSS_BYTE0_CLK>,
1260                                          <&mmcc MDSS_PCLK0_CLK>,
1261                                          <&mmcc MDSS_ESC0_CLK>,
1262                                          <&mmcc MMSS_MISC_AHB_CLK>;
1263                                 clock-names = "mdp_core",
1264                                               "iface",
1265                                               "bus",
1266                                               "byte",
1267                                               "pixel",
1268                                               "core",
1269                                               "core_mmss";
1270
1271                                 phys = <&dsi_phy0>;
1272                                 phy-names = "dsi-phy";
1273
1274                                 ports {
1275                                         #address-cells = <1>;
1276                                         #size-cells = <0>;
1277
1278                                         port@0 {
1279                                                 reg = <0>;
1280                                                 dsi0_in: endpoint {
1281                                                         remote-endpoint = <&mdp5_intf1_out>;
1282                                                 };
1283                                         };
1284
1285                                         port@1 {
1286                                                 reg = <1>;
1287                                                 dsi0_out: endpoint {
1288                                                 };
1289                                         };
1290                                 };
1291                         };
1292
1293                         dsi_phy0: dsi-phy@fd922a00 {
1294                                 status = "disabled";
1295
1296                                 compatible = "qcom,dsi-phy-28nm-hpm";
1297                                 reg = <0xfd922a00 0xd4>,
1298                                       <0xfd922b00 0x280>,
1299                                       <0xfd922d80 0x30>;
1300                                 reg-names = "dsi_pll",
1301                                             "dsi_phy",
1302                                             "dsi_phy_regulator";
1303
1304                                 #clock-cells = <1>;
1305                                 #phy-cells = <0>;
1306                                 qcom,dsi-phy-index = <0>;
1307
1308                                 clocks = <&mmcc MDSS_AHB_CLK>;
1309                                 clock-names = "iface";
1310                         };
1311                 };
1312
1313                 imem@fe805000 {
1314                         status = "disabled";
1315                         compatible = "syscon", "simple-mfd";
1316                         reg = <0xfe805000 0x1000>;
1317
1318                         reboot-mode {
1319                                 compatible = "syscon-reboot-mode";
1320                                 offset = <0x65c>;
1321                         };
1322                 };
1323         };
1324
1325         smd {
1326                 compatible = "qcom,smd";
1327
1328                 adsp {
1329                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1330
1331                         qcom,ipc = <&apcs 8 8>;
1332                         qcom,smd-edge = <1>;
1333                 };
1334
1335                 modem {
1336                         interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1337
1338                         qcom,ipc = <&apcs 8 12>;
1339                         qcom,smd-edge = <0>;
1340                 };
1341
1342                 rpm {
1343                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1344                         qcom,ipc = <&apcs 8 0>;
1345                         qcom,smd-edge = <15>;
1346
1347                         rpm_requests {
1348                                 compatible = "qcom,rpm-msm8974";
1349                                 qcom,smd-channels = "rpm_requests";
1350
1351                                 rpmcc: clock-controller {
1352                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1353                                         #clock-cells = <1>;
1354                                 };
1355
1356                                 pm8841-regulators {
1357                                         compatible = "qcom,rpm-pm8841-regulators";
1358
1359                                         pm8841_s1: s1 {};
1360                                         pm8841_s2: s2 {};
1361                                         pm8841_s3: s3 {};
1362                                         pm8841_s4: s4 {};
1363                                         pm8841_s5: s5 {};
1364                                         pm8841_s6: s6 {};
1365                                         pm8841_s7: s7 {};
1366                                         pm8841_s8: s8 {};
1367                                 };
1368
1369                                 pm8941-regulators {
1370                                         compatible = "qcom,rpm-pm8941-regulators";
1371
1372                                         pm8941_s1: s1 {};
1373                                         pm8941_s2: s2 {};
1374                                         pm8941_s3: s3 {};
1375
1376                                         pm8941_l1: l1 {};
1377                                         pm8941_l2: l2 {};
1378                                         pm8941_l3: l3 {};
1379                                         pm8941_l4: l4 {};
1380                                         pm8941_l5: l5 {};
1381                                         pm8941_l6: l6 {};
1382                                         pm8941_l7: l7 {};
1383                                         pm8941_l8: l8 {};
1384                                         pm8941_l9: l9 {};
1385                                         pm8941_l10: l10 {};
1386                                         pm8941_l11: l11 {};
1387                                         pm8941_l12: l12 {};
1388                                         pm8941_l13: l13 {};
1389                                         pm8941_l14: l14 {};
1390                                         pm8941_l15: l15 {};
1391                                         pm8941_l16: l16 {};
1392                                         pm8941_l17: l17 {};
1393                                         pm8941_l18: l18 {};
1394                                         pm8941_l19: l19 {};
1395                                         pm8941_l20: l20 {};
1396                                         pm8941_l21: l21 {};
1397                                         pm8941_l22: l22 {};
1398                                         pm8941_l23: l23 {};
1399                                         pm8941_l24: l24 {};
1400
1401                                         pm8941_lvs1: lvs1 {};
1402                                         pm8941_lvs2: lvs2 {};
1403                                         pm8941_lvs3: lvs3 {};
1404                                 };
1405                         };
1406                 };
1407         };
1408
1409         vreg_boost: vreg-boost {
1410                 compatible = "regulator-fixed";
1411
1412                 regulator-name = "vreg-boost";
1413                 regulator-min-microvolt = <3150000>;
1414                 regulator-max-microvolt = <3150000>;
1415
1416                 regulator-always-on;
1417                 regulator-boot-on;
1418
1419                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1420                 enable-active-high;
1421
1422                 pinctrl-names = "default";
1423                 pinctrl-0 = <&boost_bypass_n_pin>;
1424         };
1425         vreg_vph_pwr: vreg-vph-pwr {
1426                 compatible = "regulator-fixed";
1427                 regulator-name = "vph-pwr";
1428
1429                 regulator-min-microvolt = <3600000>;
1430                 regulator-max-microvolt = <3600000>;
1431
1432                 regulator-always-on;
1433         };
1434 };