1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
15 model = "Qualcomm MSM8974";
16 compatible = "qcom,msm8974";
17 interrupt-parent = <&intc>;
24 mpss_region: mpss@8000000 {
25 reg = <0x08000000 0x5100000>;
29 mba_region: mba@d100000 {
30 reg = <0x0d100000 0x100000>;
34 wcnss_region: wcnss@d200000 {
35 reg = <0x0d200000 0xa00000>;
39 adsp_region: adsp@dc00000 {
40 reg = <0x0dc00000 0x1900000>;
45 reg = <0x0f500000 0x500000>;
49 smem_region: smem@fa00000 {
50 reg = <0xfa00000 0x200000>;
55 reg = <0x0fc00000 0x160000>;
60 reg = <0x0fd60000 0x20000>;
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0fd80000 0x180000>;
76 interrupts = <GIC_PPI 9 0xf04>;
79 compatible = "qcom,krait";
80 enable-method = "qcom,kpss-acc-v2";
83 next-level-cache = <&L2>;
86 cpu-idle-states = <&CPU_SPC>;
90 compatible = "qcom,krait";
91 enable-method = "qcom,kpss-acc-v2";
94 next-level-cache = <&L2>;
97 cpu-idle-states = <&CPU_SPC>;
101 compatible = "qcom,krait";
102 enable-method = "qcom,kpss-acc-v2";
105 next-level-cache = <&L2>;
108 cpu-idle-states = <&CPU_SPC>;
112 compatible = "qcom,krait";
113 enable-method = "qcom,kpss-acc-v2";
116 next-level-cache = <&L2>;
119 cpu-idle-states = <&CPU_SPC>;
123 compatible = "cache";
125 qcom,saw = <&saw_l2>;
130 compatible = "qcom,idle-state-spc",
132 entry-latency-us = <150>;
133 exit-latency-us = <200>;
134 min-residency-us = <2000>;
140 device_type = "memory";
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
149 thermal-sensors = <&tsens 5>;
153 temperature = <75000>;
158 temperature = <110000>;
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
169 thermal-sensors = <&tsens 6>;
173 temperature = <75000>;
178 temperature = <110000>;
186 polling-delay-passive = <250>;
187 polling-delay = <1000>;
189 thermal-sensors = <&tsens 7>;
193 temperature = <75000>;
198 temperature = <110000>;
206 polling-delay-passive = <250>;
207 polling-delay = <1000>;
209 thermal-sensors = <&tsens 8>;
213 temperature = <75000>;
218 temperature = <110000>;
226 polling-delay-passive = <250>;
227 polling-delay = <1000>;
229 thermal-sensors = <&tsens 1>;
232 q6_dsp_alert0: trip-point0 {
233 temperature = <90000>;
241 polling-delay-passive = <250>;
242 polling-delay = <1000>;
244 thermal-sensors = <&tsens 2>;
247 modemtx_alert0: trip-point0 {
248 temperature = <90000>;
256 polling-delay-passive = <250>;
257 polling-delay = <1000>;
259 thermal-sensors = <&tsens 3>;
262 video_alert0: trip-point0 {
263 temperature = <95000>;
271 polling-delay-passive = <250>;
272 polling-delay = <1000>;
274 thermal-sensors = <&tsens 4>;
277 wlan_alert0: trip-point0 {
278 temperature = <105000>;
286 polling-delay-passive = <250>;
287 polling-delay = <1000>;
289 thermal-sensors = <&tsens 9>;
292 gpu1_alert0: trip-point0 {
293 temperature = <90000>;
301 polling-delay-passive = <250>;
302 polling-delay = <1000>;
304 thermal-sensors = <&tsens 10>;
307 gpu2_alert0: trip-point0 {
308 temperature = <90000>;
317 compatible = "qcom,krait-pmu";
318 interrupts = <GIC_PPI 7 0xf04>;
323 compatible = "fixed-clock";
325 clock-frequency = <19200000>;
328 sleep_clk: sleep_clk {
329 compatible = "fixed-clock";
331 clock-frequency = <32768>;
336 compatible = "arm,armv7-timer";
337 interrupts = <GIC_PPI 2 0xf08>,
341 clock-frequency = <19200000>;
345 compatible = "qcom,msm8974-adsp-pil";
347 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
348 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
349 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
350 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
351 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
352 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
354 cx-supply = <&pm8841_s2>;
356 clocks = <&xo_board>;
359 memory-region = <&adsp_region>;
361 qcom,smem-states = <&adsp_smp2p_out 0>;
362 qcom,smem-state-names = "stop";
365 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
367 qcom,ipc = <&apcs 8 8>;
375 compatible = "qcom,smem";
377 memory-region = <&smem_region>;
378 qcom,rpm-msg-ram = <&rpm_msg_ram>;
380 hwlocks = <&tcsr_mutex 3>;
384 compatible = "qcom,smp2p";
385 qcom,smem = <443>, <429>;
387 interrupt-parent = <&intc>;
388 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
390 qcom,ipc = <&apcs 8 10>;
392 qcom,local-pid = <0>;
393 qcom,remote-pid = <2>;
395 adsp_smp2p_out: master-kernel {
396 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
400 adsp_smp2p_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
409 compatible = "qcom,smp2p";
410 qcom,smem = <435>, <428>;
412 interrupt-parent = <&intc>;
413 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
415 qcom,ipc = <&apcs 8 14>;
417 qcom,local-pid = <0>;
418 qcom,remote-pid = <1>;
420 modem_smp2p_out: master-kernel {
421 qcom,entry-name = "master-kernel";
422 #qcom,smem-state-cells = <1>;
425 modem_smp2p_in: slave-kernel {
426 qcom,entry-name = "slave-kernel";
428 interrupt-controller;
429 #interrupt-cells = <2>;
434 compatible = "qcom,smp2p";
435 qcom,smem = <451>, <431>;
437 interrupt-parent = <&intc>;
438 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
440 qcom,ipc = <&apcs 8 18>;
442 qcom,local-pid = <0>;
443 qcom,remote-pid = <4>;
445 wcnss_smp2p_out: master-kernel {
446 qcom,entry-name = "master-kernel";
448 #qcom,smem-state-cells = <1>;
451 wcnss_smp2p_in: slave-kernel {
452 qcom,entry-name = "slave-kernel";
454 interrupt-controller;
455 #interrupt-cells = <2>;
460 compatible = "qcom,smsm";
462 #address-cells = <1>;
465 qcom,ipc-1 = <&apcs 8 13>;
466 qcom,ipc-2 = <&apcs 8 9>;
467 qcom,ipc-3 = <&apcs 8 19>;
472 #qcom,smem-state-cells = <1>;
475 modem_smsm: modem@1 {
477 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
485 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
491 wcnss_smsm: wcnss@7 {
493 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
502 compatible = "qcom,scm";
503 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
504 clock-names = "core", "bus", "iface";
509 #address-cells = <1>;
512 compatible = "simple-bus";
514 intc: interrupt-controller@f9000000 {
515 compatible = "qcom,msm-qgic2";
516 interrupt-controller;
517 #interrupt-cells = <3>;
518 reg = <0xf9000000 0x1000>,
522 apcs: syscon@f9011000 {
523 compatible = "syscon";
524 reg = <0xf9011000 0x1000>;
527 qfprom: qfprom@fc4bc000 {
528 #address-cells = <1>;
530 compatible = "qcom,qfprom";
531 reg = <0xfc4bc000 0x1000>;
532 tsens_calib: calib@d0 {
535 tsens_backup: backup@440 {
540 tsens: thermal-sensor@fc4a9000 {
541 compatible = "qcom,msm8974-tsens";
542 reg = <0xfc4a9000 0x1000>, /* TM */
543 <0xfc4a8000 0x1000>; /* SROT */
544 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
545 nvmem-cell-names = "calib", "calib_backup";
546 #qcom,sensors = <11>;
547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "uplow";
549 #thermal-sensor-cells = <1>;
553 #address-cells = <1>;
556 compatible = "arm,armv7-timer-mem";
557 reg = <0xf9020000 0x1000>;
558 clock-frequency = <19200000>;
562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
564 reg = <0xf9021000 0x1000>,
570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
571 reg = <0xf9023000 0x1000>;
577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
578 reg = <0xf9024000 0x1000>;
584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0xf9025000 0x1000>;
591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
592 reg = <0xf9026000 0x1000>;
598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
599 reg = <0xf9027000 0x1000>;
605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
606 reg = <0xf9028000 0x1000>;
611 saw0: power-controller@f9089000 {
612 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
613 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
616 saw1: power-controller@f9099000 {
617 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
618 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
621 saw2: power-controller@f90a9000 {
622 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
623 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
626 saw3: power-controller@f90b9000 {
627 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
628 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
631 saw_l2: power-controller@f9012000 {
632 compatible = "qcom,saw2";
633 reg = <0xf9012000 0x1000>;
637 acc0: clock-controller@f9088000 {
638 compatible = "qcom,kpss-acc-v2";
639 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
642 acc1: clock-controller@f9098000 {
643 compatible = "qcom,kpss-acc-v2";
644 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
647 acc2: clock-controller@f90a8000 {
648 compatible = "qcom,kpss-acc-v2";
649 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
652 acc3: clock-controller@f90b8000 {
653 compatible = "qcom,kpss-acc-v2";
654 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
658 compatible = "qcom,pshold";
659 reg = <0xfc4ab000 0x4>;
662 gcc: clock-controller@fc400000 {
663 compatible = "qcom,gcc-msm8974";
666 #power-domain-cells = <1>;
667 reg = <0xfc400000 0x4000>;
670 tcsr: syscon@fd4a0000 {
671 compatible = "syscon";
672 reg = <0xfd4a0000 0x10000>;
675 tcsr_mutex_block: syscon@fd484000 {
676 compatible = "syscon";
677 reg = <0xfd484000 0x2000>;
680 mmcc: clock-controller@fd8c0000 {
681 compatible = "qcom,mmcc-msm8974";
684 #power-domain-cells = <1>;
685 reg = <0xfd8c0000 0x6000>;
688 tcsr_mutex: tcsr-mutex {
689 compatible = "qcom,tcsr-mutex";
690 syscon = <&tcsr_mutex_block 0 0x80>;
695 rpm_msg_ram: memory@fc428000 {
696 compatible = "qcom,rpm-msg-ram";
697 reg = <0xfc428000 0x4000>;
700 blsp1_uart1: serial@f991d000 {
701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
702 reg = <0xf991d000 0x1000>;
703 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
705 clock-names = "core", "iface";
709 blsp1_uart2: serial@f991e000 {
710 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
711 reg = <0xf991e000 0x1000>;
712 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
714 clock-names = "core", "iface";
719 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
720 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
721 reg-names = "hc_mem", "core_mem";
722 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "hc_irq", "pwr_irq";
725 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
726 <&gcc GCC_SDCC1_AHB_CLK>,
728 clock-names = "core", "iface", "xo";
733 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
734 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
735 reg-names = "hc_mem", "core_mem";
736 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "hc_irq", "pwr_irq";
739 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
740 <&gcc GCC_SDCC3_AHB_CLK>,
742 clock-names = "core", "iface", "xo";
747 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
748 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
749 reg-names = "hc_mem", "core_mem";
750 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "hc_irq", "pwr_irq";
753 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
754 <&gcc GCC_SDCC2_AHB_CLK>,
756 clock-names = "core", "iface", "xo";
761 compatible = "qcom,ci-hdrc";
762 reg = <0xf9a55000 0x200>,
764 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
766 <&gcc GCC_USB_HS_SYSTEM_CLK>;
767 clock-names = "iface", "core";
768 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
769 assigned-clock-rates = <75000000>;
770 resets = <&gcc GCC_USB_HS_BCR>;
771 reset-names = "core";
774 ahb-burst-config = <0>;
775 phy-names = "usb-phy";
781 compatible = "qcom,usb-hs-phy-msm8974",
784 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
785 clock-names = "ref", "sleep";
786 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
787 reset-names = "phy", "por";
792 compatible = "qcom,usb-hs-phy-msm8974",
795 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
796 clock-names = "ref", "sleep";
797 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
798 reset-names = "phy", "por";
805 compatible = "qcom,prng";
806 reg = <0xf9bff000 0x200>;
807 clocks = <&gcc GCC_PRNG_AHB_CLK>;
808 clock-names = "core";
811 remoteproc@fc880000 {
812 compatible = "qcom,msm8974-mss-pil";
813 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
814 reg-names = "qdsp6", "rmb";
816 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
817 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
818 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
819 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
820 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
821 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
823 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
824 <&gcc GCC_MSS_CFG_AHB_CLK>,
825 <&gcc GCC_BOOT_ROM_AHB_CLK>,
827 clock-names = "iface", "bus", "mem", "xo";
829 resets = <&gcc GCC_MSS_RESTART>;
830 reset-names = "mss_restart";
832 cx-supply = <&pm8841_s2>;
833 mss-supply = <&pm8841_s3>;
834 mx-supply = <&pm8841_s1>;
835 pll-supply = <&pm8941_l12>;
837 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
839 qcom,smem-states = <&modem_smp2p_out 0>;
840 qcom,smem-state-names = "stop";
843 memory-region = <&mba_region>;
847 memory-region = <&mpss_region>;
851 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
853 qcom,ipc = <&apcs 8 12>;
860 pronto: remoteproc@fb21b000 {
861 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
862 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
863 reg-names = "ccu", "dxe", "pmu";
865 memory-region = <&wcnss_region>;
867 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
868 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
869 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
870 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
871 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
872 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
874 vddpx-supply = <&pm8941_s3>;
876 qcom,smem-states = <&wcnss_smp2p_out 0>;
877 qcom,smem-state-names = "stop";
882 compatible = "qcom,wcn3680";
884 clocks = <&rpmcc RPM_SMD_CXO_A2>;
887 vddxo-supply = <&pm8941_l6>;
888 vddrfa-supply = <&pm8941_l11>;
889 vddpa-supply = <&pm8941_l19>;
890 vdddig-supply = <&pm8941_s3>;
894 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
896 qcom,ipc = <&apcs 8 17>;
900 compatible = "qcom,wcnss";
901 qcom,smd-channels = "WCNSS_CTRL";
904 qcom,mmio = <&pronto>;
907 compatible = "qcom,wcnss-bt";
911 compatible = "qcom,wcnss-wlan";
913 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
914 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
915 interrupt-names = "tx", "rx";
917 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
918 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
924 msmgpio: pinctrl@fd510000 {
925 compatible = "qcom,msm8974-pinctrl";
926 reg = <0xfd510000 0x4000>;
929 interrupt-controller;
930 #interrupt-cells = <2>;
931 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
936 compatible = "qcom,i2c-qup-v2.1.1";
937 reg = <0xf9923000 0x1000>;
938 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
940 clock-names = "core", "iface";
941 #address-cells = <1>;
947 compatible = "qcom,i2c-qup-v2.1.1";
948 reg = <0xf9924000 0x1000>;
949 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
951 clock-names = "core", "iface";
952 #address-cells = <1>;
956 blsp_i2c3: i2c@f9925000 {
958 compatible = "qcom,i2c-qup-v2.1.1";
959 reg = <0xf9925000 0x1000>;
960 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
962 clock-names = "core", "iface";
963 #address-cells = <1>;
967 blsp_i2c8: i2c@f9964000 {
969 compatible = "qcom,i2c-qup-v2.1.1";
970 reg = <0xf9964000 0x1000>;
971 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
973 clock-names = "core", "iface";
974 #address-cells = <1>;
978 blsp_i2c11: i2c@f9967000 {
980 compatible = "qcom,i2c-qup-v2.1.1";
981 reg = <0xf9967000 0x1000>;
982 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
984 clock-names = "core", "iface";
985 #address-cells = <1>;
987 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
988 dma-names = "tx", "rx";
991 blsp_i2c12: i2c@f9968000 {
993 compatible = "qcom,i2c-qup-v2.1.1";
994 reg = <0xf9968000 0x1000>;
995 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
997 clock-names = "core", "iface";
998 #address-cells = <1>;
1002 spmi_bus: spmi@fc4cf000 {
1003 compatible = "qcom,spmi-pmic-arb";
1004 reg-names = "core", "intr", "cnfg";
1005 reg = <0xfc4cf000 0x1000>,
1006 <0xfc4cb000 0x1000>,
1007 <0xfc4ca000 0x1000>;
1008 interrupt-names = "periph_irq";
1009 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1012 #address-cells = <2>;
1014 interrupt-controller;
1015 #interrupt-cells = <4>;
1018 blsp2_dma: dma-controller@f9944000 {
1019 compatible = "qcom,bam-v1.4.0";
1020 reg = <0xf9944000 0x19000>;
1021 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1023 clock-names = "bam_clk";
1029 compatible = "arm,coresight-tmc", "arm,primecell";
1030 reg = <0xfc322000 0x1000>;
1032 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1033 clock-names = "apb_pclk", "atclk";
1038 remote-endpoint = <&replicator_out0>;
1045 compatible = "arm,coresight-tpiu", "arm,primecell";
1046 reg = <0xfc318000 0x1000>;
1048 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1049 clock-names = "apb_pclk", "atclk";
1054 remote-endpoint = <&replicator_out1>;
1060 replicator@fc31c000 {
1061 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1062 reg = <0xfc31c000 0x1000>;
1064 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1065 clock-names = "apb_pclk", "atclk";
1068 #address-cells = <1>;
1073 replicator_out0: endpoint {
1074 remote-endpoint = <&etr_in>;
1079 replicator_out1: endpoint {
1080 remote-endpoint = <&tpiu_in>;
1087 replicator_in: endpoint {
1088 remote-endpoint = <&etf_out>;
1095 compatible = "arm,coresight-tmc", "arm,primecell";
1096 reg = <0xfc307000 0x1000>;
1098 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1099 clock-names = "apb_pclk", "atclk";
1104 remote-endpoint = <&replicator_in>;
1112 remote-endpoint = <&merger_out>;
1119 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1120 reg = <0xfc31b000 0x1000>;
1122 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1123 clock-names = "apb_pclk", "atclk";
1126 #address-cells = <1>;
1130 * Not described input ports:
1131 * 0 - connected trought funnel to Audio, Modem and
1132 * Resource and Power Manager CPU's
1133 * 2...7 - not-connected
1137 merger_in1: endpoint {
1138 remote-endpoint = <&funnel1_out>;
1145 merger_out: endpoint {
1146 remote-endpoint = <&etf_in>;
1153 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1154 reg = <0xfc31a000 0x1000>;
1156 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1157 clock-names = "apb_pclk", "atclk";
1160 #address-cells = <1>;
1164 * Not described input ports:
1166 * 1 - connected trought funnel to Multimedia CPU
1167 * 2 - connected to Wireless CPU
1171 * 7 - connected to STM
1175 funnel1_in5: endpoint {
1176 remote-endpoint = <&kpss_out>;
1183 funnel1_out: endpoint {
1184 remote-endpoint = <&merger_in1>;
1190 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
1191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1192 reg = <0xfc345000 0x1000>;
1194 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1195 clock-names = "apb_pclk", "atclk";
1198 #address-cells = <1>;
1203 kpss_in0: endpoint {
1204 remote-endpoint = <&etm0_out>;
1209 kpss_in1: endpoint {
1210 remote-endpoint = <&etm1_out>;
1215 kpss_in2: endpoint {
1216 remote-endpoint = <&etm2_out>;
1221 kpss_in3: endpoint {
1222 remote-endpoint = <&etm3_out>;
1229 kpss_out: endpoint {
1230 remote-endpoint = <&funnel1_in5>;
1237 compatible = "arm,coresight-etm4x", "arm,primecell";
1238 reg = <0xfc33c000 0x1000>;
1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1241 clock-names = "apb_pclk", "atclk";
1247 etm0_out: endpoint {
1248 remote-endpoint = <&kpss_in0>;
1255 compatible = "arm,coresight-etm4x", "arm,primecell";
1256 reg = <0xfc33d000 0x1000>;
1258 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1259 clock-names = "apb_pclk", "atclk";
1265 etm1_out: endpoint {
1266 remote-endpoint = <&kpss_in1>;
1273 compatible = "arm,coresight-etm4x", "arm,primecell";
1274 reg = <0xfc33e000 0x1000>;
1276 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1277 clock-names = "apb_pclk", "atclk";
1283 etm2_out: endpoint {
1284 remote-endpoint = <&kpss_in2>;
1291 compatible = "arm,coresight-etm4x", "arm,primecell";
1292 reg = <0xfc33f000 0x1000>;
1294 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1295 clock-names = "apb_pclk", "atclk";
1301 etm3_out: endpoint {
1302 remote-endpoint = <&kpss_in3>;
1309 compatible = "qcom,msm8974-ocmem";
1310 reg = <0xfdd00000 0x2000>,
1311 <0xfec00000 0x180000>;
1314 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1315 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1316 clock-names = "core",
1319 #address-cells = <1>;
1322 gmu_sram: gmu-sram@0 {
1323 reg = <0x0 0x100000>;
1327 bimc: interconnect@fc380000 {
1328 reg = <0xfc380000 0x6a000>;
1329 compatible = "qcom,msm8974-bimc";
1330 #interconnect-cells = <1>;
1331 clock-names = "bus", "bus_a";
1332 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1333 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1336 snoc: interconnect@fc460000 {
1337 reg = <0xfc460000 0x4000>;
1338 compatible = "qcom,msm8974-snoc";
1339 #interconnect-cells = <1>;
1340 clock-names = "bus", "bus_a";
1341 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1342 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1345 pnoc: interconnect@fc468000 {
1346 reg = <0xfc468000 0x4000>;
1347 compatible = "qcom,msm8974-pnoc";
1348 #interconnect-cells = <1>;
1349 clock-names = "bus", "bus_a";
1350 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1351 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1354 ocmemnoc: interconnect@fc470000 {
1355 reg = <0xfc470000 0x4000>;
1356 compatible = "qcom,msm8974-ocmemnoc";
1357 #interconnect-cells = <1>;
1358 clock-names = "bus", "bus_a";
1359 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1360 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1363 mmssnoc: interconnect@fc478000 {
1364 reg = <0xfc478000 0x4000>;
1365 compatible = "qcom,msm8974-mmssnoc";
1366 #interconnect-cells = <1>;
1367 clock-names = "bus", "bus_a";
1368 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1369 <&mmcc MMSS_S0_AXI_CLK>;
1372 cnoc: interconnect@fc480000 {
1373 reg = <0xfc480000 0x4000>;
1374 compatible = "qcom,msm8974-cnoc";
1375 #interconnect-cells = <1>;
1376 clock-names = "bus", "bus_a";
1377 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1378 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1381 mdss: mdss@fd900000 {
1382 status = "disabled";
1384 compatible = "qcom,mdss";
1385 reg = <0xfd900000 0x100>,
1386 <0xfd924000 0x1000>;
1387 reg-names = "mdss_phys",
1390 power-domains = <&mmcc MDSS_GDSC>;
1392 clocks = <&mmcc MDSS_AHB_CLK>,
1393 <&mmcc MDSS_AXI_CLK>,
1394 <&mmcc MDSS_VSYNC_CLK>;
1395 clock-names = "iface",
1399 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1401 interrupt-controller;
1402 #interrupt-cells = <1>;
1404 #address-cells = <1>;
1409 status = "disabled";
1411 compatible = "qcom,mdp5";
1412 reg = <0xfd900100 0x22000>;
1413 reg-names = "mdp_phys";
1415 interrupt-parent = <&mdss>;
1418 clocks = <&mmcc MDSS_AHB_CLK>,
1419 <&mmcc MDSS_AXI_CLK>,
1420 <&mmcc MDSS_MDP_CLK>,
1421 <&mmcc MDSS_VSYNC_CLK>;
1422 clock-names = "iface",
1427 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1428 interconnect-names = "mdp0-mem";
1431 #address-cells = <1>;
1436 mdp5_intf1_out: endpoint {
1437 remote-endpoint = <&dsi0_in>;
1443 dsi0: dsi@fd922800 {
1444 status = "disabled";
1446 compatible = "qcom,mdss-dsi-ctrl";
1447 reg = <0xfd922800 0x1f8>;
1448 reg-names = "dsi_ctrl";
1450 interrupt-parent = <&mdss>;
1451 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1453 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1454 <&mmcc PCLK0_CLK_SRC>;
1455 assigned-clock-parents = <&dsi_phy0 0>,
1458 clocks = <&mmcc MDSS_MDP_CLK>,
1459 <&mmcc MDSS_AHB_CLK>,
1460 <&mmcc MDSS_AXI_CLK>,
1461 <&mmcc MDSS_BYTE0_CLK>,
1462 <&mmcc MDSS_PCLK0_CLK>,
1463 <&mmcc MDSS_ESC0_CLK>,
1464 <&mmcc MMSS_MISC_AHB_CLK>;
1465 clock-names = "mdp_core",
1474 phy-names = "dsi-phy";
1477 #address-cells = <1>;
1483 remote-endpoint = <&mdp5_intf1_out>;
1489 dsi0_out: endpoint {
1495 dsi_phy0: dsi-phy@fd922a00 {
1496 status = "disabled";
1498 compatible = "qcom,dsi-phy-28nm-hpm";
1499 reg = <0xfd922a00 0xd4>,
1502 reg-names = "dsi_pll",
1504 "dsi_phy_regulator";
1508 qcom,dsi-phy-index = <0>;
1510 clocks = <&mmcc MDSS_AHB_CLK>;
1511 clock-names = "iface";
1516 status = "disabled";
1517 compatible = "syscon", "simple-mfd";
1518 reg = <0xfe805000 0x1000>;
1521 compatible = "syscon-reboot-mode";
1528 compatible = "qcom,smd";
1531 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1532 qcom,ipc = <&apcs 8 0>;
1533 qcom,smd-edge = <15>;
1536 compatible = "qcom,rpm-msm8974";
1537 qcom,smd-channels = "rpm_requests";
1539 rpmcc: clock-controller {
1540 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1545 compatible = "qcom,rpm-pm8841-regulators";
1558 compatible = "qcom,rpm-pm8941-regulators";
1589 pm8941_lvs1: lvs1 {};
1590 pm8941_lvs2: lvs2 {};
1591 pm8941_lvs3: lvs3 {};
1597 vreg_boost: vreg-boost {
1598 compatible = "regulator-fixed";
1600 regulator-name = "vreg-boost";
1601 regulator-min-microvolt = <3150000>;
1602 regulator-max-microvolt = <3150000>;
1604 regulator-always-on;
1607 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&boost_bypass_n_pin>;
1613 vreg_vph_pwr: vreg-vph-pwr {
1614 compatible = "regulator-fixed";
1615 regulator-name = "vph-pwr";
1617 regulator-min-microvolt = <3600000>;
1618 regulator-max-microvolt = <3600000>;
1620 regulator-always-on;