arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         model = "Qualcomm MSM8974";
  10         compatible = "qcom,msm8974";
  11         interrupt-parent = <&intc>;
  12
  13         reserved-memory {
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges;
  17
  18                 mpss@08000000 {
  19                         reg = <0x08000000 0x5100000>;
  20                         no-map;
  21                 };
  22
  23                 mba@00d100000 {
  24                         reg = <0x0d100000 0x100000>;
  25                         no-map;
  26                 };
  27
  28                 reserved@0d200000 {
  29                         reg = <0x0d200000 0xa00000>;
  30                         no-map;
  31                 };
  32
  33                 adsp@0dc00000 {
  34                         reg = <0x0dc00000 0x1900000>;
  35                         no-map;
  36                 };
  37
  38                 venus@0f500000 {
  39                         reg = <0x0f500000 0x500000>;
  40                         no-map;
  41                 };
  42
  43                 smem_region: smem@fa00000 {
  44                         reg = <0xfa00000 0x200000>;
  45                         no-map;
  46                 };
  47
  48                 tz@0fc00000 {
  49                         reg = <0x0fc00000 0x160000>;
  50                         no-map;
  51                 };
  52
  53                 rfsa@0fd60000 {
  54                         reg = <0x0fd60000 0x20000>;
  55                         no-map;
  56                 };
  57
  58                 rmtfs@0fd80000 {
  59                         reg = <0x0fd80000 0x180000>;
  60                         no-map;
  61                 };
  62
  63                 unused@0ff00000 {
  64                         reg = <0x0ff00000 0x10100000>;
  65                         no-map;
  66                 };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72                 interrupts = <1 9 0xf04>;
  73
  74                 cpu@0 {
  75                         compatible = "qcom,krait";
  76                         enable-method = "qcom,kpss-acc-v2";
  77                         device_type = "cpu";
  78                         reg = <0>;
  79                         next-level-cache = <&L2>;
  80                         qcom,acc = <&acc0>;
  81                         qcom,saw = <&saw0>;
  82                         cpu-idle-states = <&CPU_SPC>;
  83                 };
  84
  85                 cpu@1 {
  86                         compatible = "qcom,krait";
  87                         enable-method = "qcom,kpss-acc-v2";
  88                         device_type = "cpu";
  89                         reg = <1>;
  90                         next-level-cache = <&L2>;
  91                         qcom,acc = <&acc1>;
  92                         qcom,saw = <&saw1>;
  93                         cpu-idle-states = <&CPU_SPC>;
  94                 };
  95
  96                 cpu@2 {
  97                         compatible = "qcom,krait";
  98                         enable-method = "qcom,kpss-acc-v2";
  99                         device_type = "cpu";
 100                         reg = <2>;
 101                         next-level-cache = <&L2>;
 102                         qcom,acc = <&acc2>;
 103                         qcom,saw = <&saw2>;
 104                         cpu-idle-states = <&CPU_SPC>;
 105                 };
 106
 107                 cpu@3 {
 108                         compatible = "qcom,krait";
 109                         enable-method = "qcom,kpss-acc-v2";
 110                         device_type = "cpu";
 111                         reg = <3>;
 112                         next-level-cache = <&L2>;
 113                         qcom,acc = <&acc3>;
 114                         qcom,saw = <&saw3>;
 115                         cpu-idle-states = <&CPU_SPC>;
 116                 };
 117
 118                 L2: l2-cache {
 119                         compatible = "cache";
 120                         cache-level = <2>;
 121                         qcom,saw = <&saw_l2>;
 122                 };
 123
 124                 idle-states {
 125                         CPU_SPC: spc {
 126                                 compatible = "qcom,idle-state-spc",
 127                                                 "arm,idle-state";
 128                                 entry-latency-us = <150>;
 129                                 exit-latency-us = <200>;
 130                                 min-residency-us = <2000>;
 131                         };
 132                 };
 133         };
 134
 135         thermal-zones {
 136                 cpu-thermal0 {
 137                         polling-delay-passive = <250>;
 138                         polling-delay = <1000>;
 139
 140                         thermal-sensors = <&tsens 5>;
 141
 142                         trips {
 143                                 cpu_alert0: trip0 {
 144                                         temperature = <75000>;
 145                                         hysteresis = <2000>;
 146                                         type = "passive";
 147                                 };
 148                                 cpu_crit0: trip1 {
 149                                         temperature = <110000>;
 150                                         hysteresis = <2000>;
 151                                         type = "critical";
 152                                 };
 153                         };
 154                 };
 155
 156                 cpu-thermal1 {
 157                         polling-delay-passive = <250>;
 158                         polling-delay = <1000>;
 159
 160                         thermal-sensors = <&tsens 6>;
 161
 162                         trips {
 163                                 cpu_alert1: trip0 {
 164                                         temperature = <75000>;
 165                                         hysteresis = <2000>;
 166                                         type = "passive";
 167                                 };
 168                                 cpu_crit1: trip1 {
 169                                         temperature = <110000>;
 170                                         hysteresis = <2000>;
 171                                         type = "critical";
 172                                 };
 173                         };
 174                 };
 175
 176                 cpu-thermal2 {
 177                         polling-delay-passive = <250>;
 178                         polling-delay = <1000>;
 179
 180                         thermal-sensors = <&tsens 7>;
 181
 182                         trips {
 183                                 cpu_alert2: trip0 {
 184                                         temperature = <75000>;
 185                                         hysteresis = <2000>;
 186                                         type = "passive";
 187                                 };
 188                                 cpu_crit2: trip1 {
 189                                         temperature = <110000>;
 190                                         hysteresis = <2000>;
 191                                         type = "critical";
 192                                 };
 193                         };
 194                 };
 195
 196                 cpu-thermal3 {
 197                         polling-delay-passive = <250>;
 198                         polling-delay = <1000>;
 199
 200                         thermal-sensors = <&tsens 8>;
 201
 202                         trips {
 203                                 cpu_alert3: trip0 {
 204                                         temperature = <75000>;
 205                                         hysteresis = <2000>;
 206                                         type = "passive";
 207                                 };
 208                                 cpu_crit3: trip1 {
 209                                         temperature = <110000>;
 210                                         hysteresis = <2000>;
 211                                         type = "critical";
 212                                 };
 213                         };
 214                 };
 215         };
 216
 217         cpu-pmu {
 218                 compatible = "qcom,krait-pmu";
 219                 interrupts = <1 7 0xf04>;
 220         };
 221
 222         clocks {
 223                 xo_board: xo_board {
 224                         compatible = "fixed-clock";
 225                         #clock-cells = <0>;
 226                         clock-frequency = <19200000>;
 227                 };
 228
 229                 sleep_clk: sleep_clk {
 230                         compatible = "fixed-clock";
 231                         #clock-cells = <0>;
 232                         clock-frequency = <32768>;
 233                 };
 234         };
 235
 236         timer {
 237                 compatible = "arm,armv7-timer";
 238                 interrupts = <1 2 0xf08>,
 239                              <1 3 0xf08>,
 240                              <1 4 0xf08>,
 241                              <1 1 0xf08>;
 242                 clock-frequency = <19200000>;
 243         };
 244
 245         smem {
 246                 compatible = "qcom,smem";
 247
 248                 memory-region = <&smem_region>;
 249                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 250
 251                 hwlocks = <&tcsr_mutex 3>;
 252         };
 253
 254         smp2p-modem {
 255                 compatible = "qcom,smp2p";
 256                 qcom,smem = <435>, <428>;
 257
 258                 interrupt-parent = <&intc>;
 259                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 260
 261                 qcom,ipc = <&apcs 8 14>;
 262
 263                 qcom,local-pid = <0>;
 264                 qcom,remote-pid = <1>;
 265
 266                 modem_smp2p_out: master-kernel {
 267                         qcom,entry-name = "master-kernel";
 268                         #qcom,smem-state-cells = <1>;
 269                 };
 270
 271                 modem_smp2p_in: slave-kernel {
 272                         qcom,entry-name = "slave-kernel";
 273
 274                         interrupt-controller;
 275                         #interrupt-cells = <2>;
 276                 };
 277         };
 278
 279         smp2p-wcnss {
 280                 compatible = "qcom,smp2p";
 281                 qcom,smem = <451>, <431>;
 282
 283                 interrupt-parent = <&intc>;
 284                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 285
 286                 qcom,ipc = <&apcs 8 18>;
 287
 288                 qcom,local-pid = <0>;
 289                 qcom,remote-pid = <4>;
 290
 291                 wcnss_smp2p_out: master-kernel {
 292                         qcom,entry-name = "master-kernel";
 293
 294                         #qcom,smem-state-cells = <1>;
 295                 };
 296
 297                 wcnss_smp2p_in: slave-kernel {
 298                         qcom,entry-name = "slave-kernel";
 299
 300                         interrupt-controller;
 301                         #interrupt-cells = <2>;
 302                 };
 303         };
 304
 305         smsm {
 306                 compatible = "qcom,smsm";
 307
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310
 311                 qcom,ipc-1 = <&apcs 8 13>;
 312                 qcom,ipc-2 = <&apcs 8 9>;
 313                 qcom,ipc-3 = <&apcs 8 19>;
 314
 315                 apps_smsm: apps@0 {
 316                         reg = <0>;
 317
 318                         #qcom,smem-state-cells = <1>;
 319                 };
 320
 321                 modem_smsm: modem@1 {
 322                         reg = <1>;
 323                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 324
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328
 329                 adsp_smsm: adsp@2 {
 330                         reg = <2>;
 331                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 332
 333                         interrupt-controller;
 334                         #interrupt-cells = <2>;
 335                 };
 336
 337                 wcnss_smsm: wcnss@7 {
 338                         reg = <7>;
 339                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 340
 341                         interrupt-controller;
 342                         #interrupt-cells = <2>;
 343                 };
 344         };
 345
 346         firmware {
 347                 scm {
 348                         compatible = "qcom,scm";
 349                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 350                         clock-names = "core", "bus", "iface";
 351                 };
 352         };
 353
 354         soc: soc {
 355                 #address-cells = <1>;
 356                 #size-cells = <1>;
 357                 ranges;
 358                 compatible = "simple-bus";
 359
 360                 intc: interrupt-controller@f9000000 {
 361                         compatible = "qcom,msm-qgic2";
 362                         interrupt-controller;
 363                         #interrupt-cells = <3>;
 364                         reg = <0xf9000000 0x1000>,
 365                               <0xf9002000 0x1000>;
 366                 };
 367
 368                 apcs: syscon@f9011000 {
 369                         compatible = "syscon";
 370                         reg = <0xf9011000 0x1000>;
 371                 };
 372
 373                 qfprom: qfprom@fc4bc000 {
 374                         #address-cells = <1>;
 375                         #size-cells = <1>;
 376                         compatible = "qcom,qfprom";
 377                         reg = <0xfc4bc000 0x1000>;
 378                         tsens_calib: calib@d0 {
 379                                 reg = <0xd0 0x18>;
 380                         };
 381                         tsens_backup: backup@440 {
 382                                 reg = <0x440 0x10>;
 383                         };
 384                 };
 385
 386                 tsens: thermal-sensor@fc4a8000 {
 387                         compatible = "qcom,msm8974-tsens";
 388                         reg = <0xfc4a8000 0x2000>;
 389                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 390                         nvmem-cell-names = "calib", "calib_backup";
 391                         #thermal-sensor-cells = <1>;
 392                 };
 393
 394                 timer@f9020000 {
 395                         #address-cells = <1>;
 396                         #size-cells = <1>;
 397                         ranges;
 398                         compatible = "arm,armv7-timer-mem";
 399                         reg = <0xf9020000 0x1000>;
 400                         clock-frequency = <19200000>;
 401
 402                         frame@f9021000 {
 403                                 frame-number = <0>;
 404                                 interrupts = <0 8 0x4>,
 405                                              <0 7 0x4>;
 406                                 reg = <0xf9021000 0x1000>,
 407                                       <0xf9022000 0x1000>;
 408                         };
 409
 410                         frame@f9023000 {
 411                                 frame-number = <1>;
 412                                 interrupts = <0 9 0x4>;
 413                                 reg = <0xf9023000 0x1000>;
 414                                 status = "disabled";
 415                         };
 416
 417                         frame@f9024000 {
 418                                 frame-number = <2>;
 419                                 interrupts = <0 10 0x4>;
 420                                 reg = <0xf9024000 0x1000>;
 421                                 status = "disabled";
 422                         };
 423
 424                         frame@f9025000 {
 425                                 frame-number = <3>;
 426                                 interrupts = <0 11 0x4>;
 427                                 reg = <0xf9025000 0x1000>;
 428                                 status = "disabled";
 429                         };
 430
 431                         frame@f9026000 {
 432                                 frame-number = <4>;
 433                                 interrupts = <0 12 0x4>;
 434                                 reg = <0xf9026000 0x1000>;
 435                                 status = "disabled";
 436                         };
 437
 438                         frame@f9027000 {
 439                                 frame-number = <5>;
 440                                 interrupts = <0 13 0x4>;
 441                                 reg = <0xf9027000 0x1000>;
 442                                 status = "disabled";
 443                         };
 444
 445                         frame@f9028000 {
 446                                 frame-number = <6>;
 447                                 interrupts = <0 14 0x4>;
 448                                 reg = <0xf9028000 0x1000>;
 449                                 status = "disabled";
 450                         };
 451                 };
 452
 453                 saw0: power-controller@f9089000 {
 454                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 455                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 456                 };
 457
 458                 saw1: power-controller@f9099000 {
 459                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 460                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 461                 };
 462
 463                 saw2: power-controller@f90a9000 {
 464                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 465                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 466                 };
 467
 468                 saw3: power-controller@f90b9000 {
 469                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 470                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 471                 };
 472
 473                 saw_l2: power-controller@f9012000 {
 474                         compatible = "qcom,saw2";
 475                         reg = <0xf9012000 0x1000>;
 476                         regulator;
 477                 };
 478
 479                 acc0: clock-controller@f9088000 {
 480                         compatible = "qcom,kpss-acc-v2";
 481                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 482                 };
 483
 484                 acc1: clock-controller@f9098000 {
 485                         compatible = "qcom,kpss-acc-v2";
 486                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 487                 };
 488
 489                 acc2: clock-controller@f90a8000 {
 490                         compatible = "qcom,kpss-acc-v2";
 491                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 492                 };
 493
 494                 acc3: clock-controller@f90b8000 {
 495                         compatible = "qcom,kpss-acc-v2";
 496                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 497                 };
 498
 499                 restart@fc4ab000 {
 500                         compatible = "qcom,pshold";
 501                         reg = <0xfc4ab000 0x4>;
 502                 };
 503
 504                 gcc: clock-controller@fc400000 {
 505                         compatible = "qcom,gcc-msm8974";
 506                         #clock-cells = <1>;
 507                         #reset-cells = <1>;
 508                         #power-domain-cells = <1>;
 509                         reg = <0xfc400000 0x4000>;
 510                 };
 511
 512                 tcsr_mutex_block: syscon@fd484000 {
 513                         compatible = "syscon";
 514                         reg = <0xfd484000 0x2000>;
 515                 };
 516
 517                 mmcc: clock-controller@fd8c0000 {
 518                         compatible = "qcom,mmcc-msm8974";
 519                         #clock-cells = <1>;
 520                         #reset-cells = <1>;
 521                         #power-domain-cells = <1>;
 522                         reg = <0xfd8c0000 0x6000>;
 523                 };
 524
 525                 tcsr_mutex: tcsr-mutex {
 526                         compatible = "qcom,tcsr-mutex";
 527                         syscon = <&tcsr_mutex_block 0 0x80>;
 528
 529                         #hwlock-cells = <1>;
 530                 };
 531
 532                 rpm_msg_ram: memory@fc428000 {
 533                         compatible = "qcom,rpm-msg-ram";
 534                         reg = <0xfc428000 0x4000>;
 535                 };
 536
 537                 blsp1_uart1: serial@f991d000 {
 538                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 539                         reg = <0xf991d000 0x1000>;
 540                         interrupts = <0 107 0x0>;
 541                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 542                         clock-names = "core", "iface";
 543                         status = "disabled";
 544                 };
 545
 546                 blsp1_uart2: serial@f991e000 {
 547                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 548                         reg = <0xf991e000 0x1000>;
 549                         interrupts = <0 108 0x0>;
 550                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 551                         clock-names = "core", "iface";
 552                         status = "disabled";
 553                 };
 554
 555                 sdhci@f9824900 {
 556                         compatible = "qcom,sdhci-msm-v4";
 557                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 558                         reg-names = "hc_mem", "core_mem";
 559                         interrupts = <0 123 0>, <0 138 0>;
 560                         interrupt-names = "hc_irq", "pwr_irq";
 561                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 562                                  <&gcc GCC_SDCC1_AHB_CLK>,
 563                                  <&xo_board>;
 564                         clock-names = "core", "iface", "xo";
 565                         status = "disabled";
 566                 };
 567
 568                 sdhci@f98a4900 {
 569                         compatible = "qcom,sdhci-msm-v4";
 570                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 571                         reg-names = "hc_mem", "core_mem";
 572                         interrupts = <0 125 0>, <0 221 0>;
 573                         interrupt-names = "hc_irq", "pwr_irq";
 574                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 575                                  <&gcc GCC_SDCC2_AHB_CLK>,
 576                                  <&xo_board>;
 577                         clock-names = "core", "iface", "xo";
 578                         status = "disabled";
 579                 };
 580
 581                 rng@f9bff000 {
 582                         compatible = "qcom,prng";
 583                         reg = <0xf9bff000 0x200>;
 584                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 585                         clock-names = "core";
 586                 };
 587
 588                 msmgpio: pinctrl@fd510000 {
 589                         compatible = "qcom,msm8974-pinctrl";
 590                         reg = <0xfd510000 0x4000>;
 591                         gpio-controller;
 592                         #gpio-cells = <2>;
 593                         interrupt-controller;
 594                         #interrupt-cells = <2>;
 595                         interrupts = <0 208 0>;
 596                 };
 597
 598                 i2c@f9924000 {
 599                         status = "disabled";
 600                         compatible = "qcom,i2c-qup-v2.1.1";
 601                         reg = <0xf9924000 0x1000>;
 602                         interrupts = <0 96 IRQ_TYPE_NONE>;
 603                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 604                         clock-names = "core", "iface";
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                 };
 608
 609                 blsp_i2c8: i2c@f9964000 {
 610                         status = "disabled";
 611                         compatible = "qcom,i2c-qup-v2.1.1";
 612                         reg = <0xf9964000 0x1000>;
 613                         interrupts = <0 102 IRQ_TYPE_NONE>;
 614                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 615                         clock-names = "core", "iface";
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                 };
 619
 620                 blsp_i2c11: i2c@f9967000 {
 621                         status = "disabled";
 622                         compatible = "qcom,i2c-qup-v2.1.1";
 623                         reg = <0xf9967000 0x1000>;
 624                         interrupts = <0 105 IRQ_TYPE_NONE>;
 625                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 626                         clock-names = "core", "iface";
 627                         #address-cells = <1>;
 628                         #size-cells = <0>;
 629                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 630                         dma-names = "tx", "rx";
 631                 };
 632
 633                 spmi_bus: spmi@fc4cf000 {
 634                         compatible = "qcom,spmi-pmic-arb";
 635                         reg-names = "core", "intr", "cnfg";
 636                         reg = <0xfc4cf000 0x1000>,
 637                               <0xfc4cb000 0x1000>,
 638                               <0xfc4ca000 0x1000>;
 639                         interrupt-names = "periph_irq";
 640                         interrupts = <0 190 0>;
 641                         qcom,ee = <0>;
 642                         qcom,channel = <0>;
 643                         #address-cells = <2>;
 644                         #size-cells = <0>;
 645                         interrupt-controller;
 646                         #interrupt-cells = <4>;
 647                 };
 648
 649                 blsp2_dma: dma-controller@f9944000 {
 650                         compatible = "qcom,bam-v1.4.0";
 651                         reg = <0xf9944000 0x19000>;
 652                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 654                         clock-names = "bam_clk";
 655                         #dma-cells = <1>;
 656                         qcom,ee = <0>;
 657                 };
 658         };
 659
 660         smd {
 661                 compatible = "qcom,smd";
 662
 663                 modem {
 664                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 665
 666                         qcom,ipc = <&apcs 8 12>;
 667                         qcom,smd-edge = <0>;
 668                 };
 669
 670                 rpm {
 671                         interrupts = <0 168 1>;
 672                         qcom,ipc = <&apcs 8 0>;
 673                         qcom,smd-edge = <15>;
 674
 675                         rpm_requests {
 676                                 compatible = "qcom,rpm-msm8974";
 677                                 qcom,smd-channels = "rpm_requests";
 678
 679                                 pm8841-regulators {
 680                                         compatible = "qcom,rpm-pm8841-regulators";
 681
 682                                         pm8841_s1: s1 {};
 683                                         pm8841_s2: s2 {};
 684                                         pm8841_s3: s3 {};
 685                                         pm8841_s4: s4 {};
 686                                         pm8841_s5: s5 {};
 687                                         pm8841_s6: s6 {};
 688                                         pm8841_s7: s7 {};
 689                                         pm8841_s8: s8 {};
 690                                 };
 691
 692                                 pm8941-regulators {
 693                                         compatible = "qcom,rpm-pm8941-regulators";
 694
 695                                         pm8941_s1: s1 {};
 696                                         pm8941_s2: s2 {};
 697                                         pm8941_s3: s3 {};
 698                                         pm8941_5v: s4 {};
 699
 700                                         pm8941_l1: l1 {};
 701                                         pm8941_l2: l2 {};
 702                                         pm8941_l3: l3 {};
 703                                         pm8941_l4: l4 {};
 704                                         pm8941_l5: l5 {};
 705                                         pm8941_l6: l6 {};
 706                                         pm8941_l7: l7 {};
 707                                         pm8941_l8: l8 {};
 708                                         pm8941_l9: l9 {};
 709                                         pm8941_l10: l10 {};
 710                                         pm8941_l11: l11 {};
 711                                         pm8941_l12: l12 {};
 712                                         pm8941_l13: l13 {};
 713                                         pm8941_l14: l14 {};
 714                                         pm8941_l15: l15 {};
 715                                         pm8941_l16: l16 {};
 716                                         pm8941_l17: l17 {};
 717                                         pm8941_l18: l18 {};
 718                                         pm8941_l19: l19 {};
 719                                         pm8941_l20: l20 {};
 720                                         pm8941_l21: l21 {};
 721                                         pm8941_l22: l22 {};
 722                                         pm8941_l23: l23 {};
 723                                         pm8941_l24: l24 {};
 724
 725                                         pm8941_lvs1: lvs1 {};
 726                                         pm8941_lvs2: lvs2 {};
 727                                         pm8941_lvs3: lvs3 {};
 728
 729                                         pm8941_5vs1: 5vs1 {};
 730                                         pm8941_5vs2: 5vs2 {};
 731                                 };
 732                         };
 733                 };
 734         };
 735
 736         vreg_boost: vreg-boost {
 737                 compatible = "regulator-fixed";
 738
 739                 regulator-name = "vreg-boost";
 740                 regulator-min-microvolt = <3150000>;
 741                 regulator-max-microvolt = <3150000>;
 742
 743                 regulator-always-on;
 744                 regulator-boot-on;
 745
 746                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
 747                 enable-active-high;
 748
 749                 pinctrl-names = "default";
 750                 pinctrl-0 = <&boost_bypass_n_pin>;
 751         };
 752         vreg_vph_pwr: vreg-vph-pwr {
 753                 compatible = "regulator-fixed";
 754                 regulator-name = "vph-pwr";
 755
 756                 regulator-min-microvolt = <3600000>;
 757                 regulator-max-microvolt = <3600000>;
 758
 759                 regulator-always-on;
 760         };
 761 };