arch/arm/boot/dts/qcom-msm8974.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         model = "Qualcomm MSM8974";
  14         compatible = "qcom,msm8974";
  15         interrupt-parent = <&intc>;
  16
  17         reserved-memory {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 mpss@8000000 {
  23                         reg = <0x08000000 0x5100000>;
  24                         no-map;
  25                 };
  26
  27                 mba@d100000 {
  28                         reg = <0x0d100000 0x100000>;
  29                         no-map;
  30                 };
  31
  32                 reserved@d200000 {
  33                         reg = <0x0d200000 0xa00000>;
  34                         no-map;
  35                 };
  36
  37                 adsp_region: adsp@dc00000 {
  38                         reg = <0x0dc00000 0x1900000>;
  39                         no-map;
  40                 };
  41
  42                 venus@f500000 {
  43                         reg = <0x0f500000 0x500000>;
  44                         no-map;
  45                 };
  46
  47                 smem_region: smem@fa00000 {
  48                         reg = <0xfa00000 0x200000>;
  49                         no-map;
  50                 };
  51
  52                 tz@fc00000 {
  53                         reg = <0x0fc00000 0x160000>;
  54                         no-map;
  55                 };
  56
  57                 rfsa@fd60000 {
  58                         reg = <0x0fd60000 0x20000>;
  59                         no-map;
  60                 };
  61
  62                 rmtfs@fd80000 {
  63                         reg = <0x0fd80000 0x180000>;
  64                         no-map;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 interrupts = <GIC_PPI 9 0xf04>;
  72
  73                 CPU0: cpu@0 {
  74                         compatible = "qcom,krait";
  75                         enable-method = "qcom,kpss-acc-v2";
  76                         device_type = "cpu";
  77                         reg = <0>;
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc0>;
  80                         qcom,saw = <&saw0>;
  81                         cpu-idle-states = <&CPU_SPC>;
  82                 };
  83
  84                 CPU1: cpu@1 {
  85                         compatible = "qcom,krait";
  86                         enable-method = "qcom,kpss-acc-v2";
  87                         device_type = "cpu";
  88                         reg = <1>;
  89                         next-level-cache = <&L2>;
  90                         qcom,acc = <&acc1>;
  91                         qcom,saw = <&saw1>;
  92                         cpu-idle-states = <&CPU_SPC>;
  93                 };
  94
  95                 CPU2: cpu@2 {
  96                         compatible = "qcom,krait";
  97                         enable-method = "qcom,kpss-acc-v2";
  98                         device_type = "cpu";
  99                         reg = <2>;
 100                         next-level-cache = <&L2>;
 101                         qcom,acc = <&acc2>;
 102                         qcom,saw = <&saw2>;
 103                         cpu-idle-states = <&CPU_SPC>;
 104                 };
 105
 106                 CPU3: cpu@3 {
 107                         compatible = "qcom,krait";
 108                         enable-method = "qcom,kpss-acc-v2";
 109                         device_type = "cpu";
 110                         reg = <3>;
 111                         next-level-cache = <&L2>;
 112                         qcom,acc = <&acc3>;
 113                         qcom,saw = <&saw3>;
 114                         cpu-idle-states = <&CPU_SPC>;
 115                 };
 116
 117                 L2: l2-cache {
 118                         compatible = "cache";
 119                         cache-level = <2>;
 120                         qcom,saw = <&saw_l2>;
 121                 };
 122
 123                 idle-states {
 124                         CPU_SPC: spc {
 125                                 compatible = "qcom,idle-state-spc",
 126                                                 "arm,idle-state";
 127                                 entry-latency-us = <150>;
 128                                 exit-latency-us = <200>;
 129                                 min-residency-us = <2000>;
 130                         };
 131                 };
 132         };
 133
 134         memory {
 135                 device_type = "memory";
 136                 reg = <0x0 0x0>;
 137         };
 138
 139         thermal-zones {
 140                 cpu-thermal0 {
 141                         polling-delay-passive = <250>;
 142                         polling-delay = <1000>;
 143
 144                         thermal-sensors = <&tsens 5>;
 145
 146                         trips {
 147                                 cpu_alert0: trip0 {
 148                                         temperature = <75000>;
 149                                         hysteresis = <2000>;
 150                                         type = "passive";
 151                                 };
 152                                 cpu_crit0: trip1 {
 153                                         temperature = <110000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical";
 156                                 };
 157                         };
 158                 };
 159
 160                 cpu-thermal1 {
 161                         polling-delay-passive = <250>;
 162                         polling-delay = <1000>;
 163
 164                         thermal-sensors = <&tsens 6>;
 165
 166                         trips {
 167                                 cpu_alert1: trip0 {
 168                                         temperature = <75000>;
 169                                         hysteresis = <2000>;
 170                                         type = "passive";
 171                                 };
 172                                 cpu_crit1: trip1 {
 173                                         temperature = <110000>;
 174                                         hysteresis = <2000>;
 175                                         type = "critical";
 176                                 };
 177                         };
 178                 };
 179
 180                 cpu-thermal2 {
 181                         polling-delay-passive = <250>;
 182                         polling-delay = <1000>;
 183
 184                         thermal-sensors = <&tsens 7>;
 185
 186                         trips {
 187                                 cpu_alert2: trip0 {
 188                                         temperature = <75000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192                                 cpu_crit2: trip1 {
 193                                         temperature = <110000>;
 194                                         hysteresis = <2000>;
 195                                         type = "critical";
 196                                 };
 197                         };
 198                 };
 199
 200                 cpu-thermal3 {
 201                         polling-delay-passive = <250>;
 202                         polling-delay = <1000>;
 203
 204                         thermal-sensors = <&tsens 8>;
 205
 206                         trips {
 207                                 cpu_alert3: trip0 {
 208                                         temperature = <75000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212                                 cpu_crit3: trip1 {
 213                                         temperature = <110000>;
 214                                         hysteresis = <2000>;
 215                                         type = "critical";
 216                                 };
 217                         };
 218                 };
 219         };
 220
 221         cpu-pmu {
 222                 compatible = "qcom,krait-pmu";
 223                 interrupts = <GIC_PPI 7 0xf04>;
 224         };
 225
 226         clocks {
 227                 xo_board: xo_board {
 228                         compatible = "fixed-clock";
 229                         #clock-cells = <0>;
 230                         clock-frequency = <19200000>;
 231                 };
 232
 233                 sleep_clk: sleep_clk {
 234                         compatible = "fixed-clock";
 235                         #clock-cells = <0>;
 236                         clock-frequency = <32768>;
 237                 };
 238         };
 239
 240         timer {
 241                 compatible = "arm,armv7-timer";
 242                 interrupts = <GIC_PPI 2 0xf08>,
 243                              <GIC_PPI 3 0xf08>,
 244                              <GIC_PPI 4 0xf08>,
 245                              <GIC_PPI 1 0xf08>;
 246                 clock-frequency = <19200000>;
 247         };
 248
 249         adsp-pil {
 250                 compatible = "qcom,msm8974-adsp-pil";
 251
 252                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 253                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 254                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 255                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 256                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 257                 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 258
 259                 cx-supply = <&pm8841_s2>;
 260
 261                 clocks = <&xo_board>;
 262                 clock-names = "xo";
 263
 264                 memory-region = <&adsp_region>;
 265
 266                 qcom,smem-states = <&adsp_smp2p_out 0>;
 267                 qcom,smem-state-names = "stop";
 268         };
 269
 270         smem {
 271                 compatible = "qcom,smem";
 272
 273                 memory-region = <&smem_region>;
 274                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 275
 276                 hwlocks = <&tcsr_mutex 3>;
 277         };
 278
 279         smp2p-adsp {
 280                 compatible = "qcom,smp2p";
 281                 qcom,smem = <443>, <429>;
 282
 283                 interrupt-parent = <&intc>;
 284                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 285
 286                 qcom,ipc = <&apcs 8 10>;
 287
 288                 qcom,local-pid = <0>;
 289                 qcom,remote-pid = <2>;
 290
 291                 adsp_smp2p_out: master-kernel {
 292                         qcom,entry-name = "master-kernel";
 293                         #qcom,smem-state-cells = <1>;
 294                 };
 295
 296                 adsp_smp2p_in: slave-kernel {
 297                         qcom,entry-name = "slave-kernel";
 298
 299                         interrupt-controller;
 300                         #interrupt-cells = <2>;
 301                 };
 302         };
 303
 304         smp2p-modem {
 305                 compatible = "qcom,smp2p";
 306                 qcom,smem = <435>, <428>;
 307
 308                 interrupt-parent = <&intc>;
 309                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 310
 311                 qcom,ipc = <&apcs 8 14>;
 312
 313                 qcom,local-pid = <0>;
 314                 qcom,remote-pid = <1>;
 315
 316                 modem_smp2p_out: master-kernel {
 317                         qcom,entry-name = "master-kernel";
 318                         #qcom,smem-state-cells = <1>;
 319                 };
 320
 321                 modem_smp2p_in: slave-kernel {
 322                         qcom,entry-name = "slave-kernel";
 323
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                 };
 327         };
 328
 329         smp2p-wcnss {
 330                 compatible = "qcom,smp2p";
 331                 qcom,smem = <451>, <431>;
 332
 333                 interrupt-parent = <&intc>;
 334                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 335
 336                 qcom,ipc = <&apcs 8 18>;
 337
 338                 qcom,local-pid = <0>;
 339                 qcom,remote-pid = <4>;
 340
 341                 wcnss_smp2p_out: master-kernel {
 342                         qcom,entry-name = "master-kernel";
 343
 344                         #qcom,smem-state-cells = <1>;
 345                 };
 346
 347                 wcnss_smp2p_in: slave-kernel {
 348                         qcom,entry-name = "slave-kernel";
 349
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353         };
 354
 355         smsm {
 356                 compatible = "qcom,smsm";
 357
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360
 361                 qcom,ipc-1 = <&apcs 8 13>;
 362                 qcom,ipc-2 = <&apcs 8 9>;
 363                 qcom,ipc-3 = <&apcs 8 19>;
 364
 365                 apps_smsm: apps@0 {
 366                         reg = <0>;
 367
 368                         #qcom,smem-state-cells = <1>;
 369                 };
 370
 371                 modem_smsm: modem@1 {
 372                         reg = <1>;
 373                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 374
 375                         interrupt-controller;
 376                         #interrupt-cells = <2>;
 377                 };
 378
 379                 adsp_smsm: adsp@2 {
 380                         reg = <2>;
 381                         interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 382
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                 };
 386
 387                 wcnss_smsm: wcnss@7 {
 388                         reg = <7>;
 389                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 390
 391                         interrupt-controller;
 392                         #interrupt-cells = <2>;
 393                 };
 394         };
 395
 396         firmware {
 397                 scm {
 398                         compatible = "qcom,scm";
 399                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 400                         clock-names = "core", "bus", "iface";
 401                 };
 402         };
 403
 404         soc: soc {
 405                 #address-cells = <1>;
 406                 #size-cells = <1>;
 407                 ranges;
 408                 compatible = "simple-bus";
 409
 410                 intc: interrupt-controller@f9000000 {
 411                         compatible = "qcom,msm-qgic2";
 412                         interrupt-controller;
 413                         #interrupt-cells = <3>;
 414                         reg = <0xf9000000 0x1000>,
 415                               <0xf9002000 0x1000>;
 416                 };
 417
 418                 apcs: syscon@f9011000 {
 419                         compatible = "syscon";
 420                         reg = <0xf9011000 0x1000>;
 421                 };
 422
 423                 qfprom: qfprom@fc4bc000 {
 424                         #address-cells = <1>;
 425                         #size-cells = <1>;
 426                         compatible = "qcom,qfprom";
 427                         reg = <0xfc4bc000 0x1000>;
 428                         tsens_calib: calib@d0 {
 429                                 reg = <0xd0 0x18>;
 430                         };
 431                         tsens_backup: backup@440 {
 432                                 reg = <0x440 0x10>;
 433                         };
 434                 };
 435
 436                 tsens: thermal-sensor@fc4a9000 {
 437                         compatible = "qcom,msm8974-tsens";
 438                         reg = <0xfc4a9000 0x1000>, /* TM */
 439                               <0xfc4a8000 0x1000>; /* SROT */
 440                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 441                         nvmem-cell-names = "calib", "calib_backup";
 442                         #qcom,sensors = <11>;
 443                         #thermal-sensor-cells = <1>;
 444                 };
 445
 446                 timer@f9020000 {
 447                         #address-cells = <1>;
 448                         #size-cells = <1>;
 449                         ranges;
 450                         compatible = "arm,armv7-timer-mem";
 451                         reg = <0xf9020000 0x1000>;
 452                         clock-frequency = <19200000>;
 453
 454                         frame@f9021000 {
 455                                 frame-number = <0>;
 456                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 458                                 reg = <0xf9021000 0x1000>,
 459                                       <0xf9022000 0x1000>;
 460                         };
 461
 462                         frame@f9023000 {
 463                                 frame-number = <1>;
 464                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 465                                 reg = <0xf9023000 0x1000>;
 466                                 status = "disabled";
 467                         };
 468
 469                         frame@f9024000 {
 470                                 frame-number = <2>;
 471                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 472                                 reg = <0xf9024000 0x1000>;
 473                                 status = "disabled";
 474                         };
 475
 476                         frame@f9025000 {
 477                                 frame-number = <3>;
 478                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 479                                 reg = <0xf9025000 0x1000>;
 480                                 status = "disabled";
 481                         };
 482
 483                         frame@f9026000 {
 484                                 frame-number = <4>;
 485                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 486                                 reg = <0xf9026000 0x1000>;
 487                                 status = "disabled";
 488                         };
 489
 490                         frame@f9027000 {
 491                                 frame-number = <5>;
 492                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 493                                 reg = <0xf9027000 0x1000>;
 494                                 status = "disabled";
 495                         };
 496
 497                         frame@f9028000 {
 498                                 frame-number = <6>;
 499                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 500                                 reg = <0xf9028000 0x1000>;
 501                                 status = "disabled";
 502                         };
 503                 };
 504
 505                 saw0: power-controller@f9089000 {
 506                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 507                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 508                 };
 509
 510                 saw1: power-controller@f9099000 {
 511                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 512                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 513                 };
 514
 515                 saw2: power-controller@f90a9000 {
 516                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 517                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 518                 };
 519
 520                 saw3: power-controller@f90b9000 {
 521                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 522                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 523                 };
 524
 525                 saw_l2: power-controller@f9012000 {
 526                         compatible = "qcom,saw2";
 527                         reg = <0xf9012000 0x1000>;
 528                         regulator;
 529                 };
 530
 531                 acc0: clock-controller@f9088000 {
 532                         compatible = "qcom,kpss-acc-v2";
 533                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 534                 };
 535
 536                 acc1: clock-controller@f9098000 {
 537                         compatible = "qcom,kpss-acc-v2";
 538                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 539                 };
 540
 541                 acc2: clock-controller@f90a8000 {
 542                         compatible = "qcom,kpss-acc-v2";
 543                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 544                 };
 545
 546                 acc3: clock-controller@f90b8000 {
 547                         compatible = "qcom,kpss-acc-v2";
 548                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 549                 };
 550
 551                 restart@fc4ab000 {
 552                         compatible = "qcom,pshold";
 553                         reg = <0xfc4ab000 0x4>;
 554                 };
 555
 556                 gcc: clock-controller@fc400000 {
 557                         compatible = "qcom,gcc-msm8974";
 558                         #clock-cells = <1>;
 559                         #reset-cells = <1>;
 560                         #power-domain-cells = <1>;
 561                         reg = <0xfc400000 0x4000>;
 562                 };
 563
 564                 tcsr: syscon@fd4a0000 {
 565                         compatible = "syscon";
 566                         reg = <0xfd4a0000 0x10000>;
 567                 };
 568
 569                 tcsr_mutex_block: syscon@fd484000 {
 570                         compatible = "syscon";
 571                         reg = <0xfd484000 0x2000>;
 572                 };
 573
 574                 mmcc: clock-controller@fd8c0000 {
 575                         compatible = "qcom,mmcc-msm8974";
 576                         #clock-cells = <1>;
 577                         #reset-cells = <1>;
 578                         #power-domain-cells = <1>;
 579                         reg = <0xfd8c0000 0x6000>;
 580                 };
 581
 582                 tcsr_mutex: tcsr-mutex {
 583                         compatible = "qcom,tcsr-mutex";
 584                         syscon = <&tcsr_mutex_block 0 0x80>;
 585
 586                         #hwlock-cells = <1>;
 587                 };
 588
 589                 rpm_msg_ram: memory@fc428000 {
 590                         compatible = "qcom,rpm-msg-ram";
 591                         reg = <0xfc428000 0x4000>;
 592                 };
 593
 594                 blsp1_uart1: serial@f991d000 {
 595                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 596                         reg = <0xf991d000 0x1000>;
 597                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 599                         clock-names = "core", "iface";
 600                         status = "disabled";
 601                 };
 602
 603                 blsp1_uart2: serial@f991e000 {
 604                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 605                         reg = <0xf991e000 0x1000>;
 606                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 608                         clock-names = "core", "iface";
 609                         status = "disabled";
 610                 };
 611
 612                 sdhci@f9824900 {
 613                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 614                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 615                         reg-names = "hc_mem", "core_mem";
 616                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 618                         interrupt-names = "hc_irq", "pwr_irq";
 619                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 620                                  <&gcc GCC_SDCC1_AHB_CLK>,
 621                                  <&xo_board>;
 622                         clock-names = "core", "iface", "xo";
 623                         status = "disabled";
 624                 };
 625
 626                 sdhci@f9864900 {
 627                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 628                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 629                         reg-names = "hc_mem", "core_mem";
 630                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 632                         interrupt-names = "hc_irq", "pwr_irq";
 633                         clocks = <&gcc GCC_SDCC3_APPS_CLK>,
 634                                  <&gcc GCC_SDCC3_AHB_CLK>,
 635                                  <&xo_board>;
 636                         clock-names = "core", "iface", "xo";
 637                         status = "disabled";
 638                 };
 639
 640                 sdhci@f98a4900 {
 641                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 642                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 643                         reg-names = "hc_mem", "core_mem";
 644                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 646                         interrupt-names = "hc_irq", "pwr_irq";
 647                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 648                                  <&gcc GCC_SDCC2_AHB_CLK>,
 649                                  <&xo_board>;
 650                         clock-names = "core", "iface", "xo";
 651                         status = "disabled";
 652                 };
 653
 654                 otg: usb@f9a55000 {
 655                         compatible = "qcom,ci-hdrc";
 656                         reg = <0xf9a55000 0x200>,
 657                               <0xf9a55200 0x200>;
 658                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 659                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 660                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 661                         clock-names = "iface", "core";
 662                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 663                         assigned-clock-rates = <75000000>;
 664                         resets = <&gcc GCC_USB_HS_BCR>;
 665                         reset-names = "core";
 666                         phy_type = "ulpi";
 667                         dr_mode = "otg";
 668                         ahb-burst-config = <0>;
 669                         phy-names = "usb-phy";
 670                         status = "disabled";
 671                         #reset-cells = <1>;
 672
 673                         ulpi {
 674                                 usb_hs1_phy: phy@a {
 675                                         compatible = "qcom,usb-hs-phy-msm8974",
 676                                                      "qcom,usb-hs-phy";
 677                                         #phy-cells = <0>;
 678                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 679                                         clock-names = "ref", "sleep";
 680                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 681                                         reset-names = "phy", "por";
 682                                         status = "disabled";
 683                                 };
 684
 685                                 usb_hs2_phy: phy@b {
 686                                         compatible = "qcom,usb-hs-phy-msm8974",
 687                                                      "qcom,usb-hs-phy";
 688                                         #phy-cells = <0>;
 689                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
 690                                         clock-names = "ref", "sleep";
 691                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
 692                                         reset-names = "phy", "por";
 693                                         status = "disabled";
 694                                 };
 695                         };
 696                 };
 697
 698                 rng@f9bff000 {
 699                         compatible = "qcom,prng";
 700                         reg = <0xf9bff000 0x200>;
 701                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 702                         clock-names = "core";
 703                 };
 704
 705                 msmgpio: pinctrl@fd510000 {
 706                         compatible = "qcom,msm8974-pinctrl";
 707                         reg = <0xfd510000 0x4000>;
 708                         gpio-controller;
 709                         #gpio-cells = <2>;
 710                         interrupt-controller;
 711                         #interrupt-cells = <2>;
 712                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 713                 };
 714
 715                 i2c@f9923000 {
 716                         status = "disabled";
 717                         compatible = "qcom,i2c-qup-v2.1.1";
 718                         reg = <0xf9923000 0x1000>;
 719                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 720                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 721                         clock-names = "core", "iface";
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                 };
 725
 726                 i2c@f9924000 {
 727                         status = "disabled";
 728                         compatible = "qcom,i2c-qup-v2.1.1";
 729                         reg = <0xf9924000 0x1000>;
 730                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 732                         clock-names = "core", "iface";
 733                         #address-cells = <1>;
 734                         #size-cells = <0>;
 735                 };
 736
 737                 blsp_i2c3: i2c@f9925000 {
 738                         status = "disabled";
 739                         compatible = "qcom,i2c-qup-v2.1.1";
 740                         reg = <0xf9925000 0x1000>;
 741                         interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 743                         clock-names = "core", "iface";
 744                         #address-cells = <1>;
 745                         #size-cells = <0>;
 746                 };
 747
 748                 blsp_i2c8: i2c@f9964000 {
 749                         status = "disabled";
 750                         compatible = "qcom,i2c-qup-v2.1.1";
 751                         reg = <0xf9964000 0x1000>;
 752                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 753                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 754                         clock-names = "core", "iface";
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                 };
 758
 759                 blsp_i2c11: i2c@f9967000 {
 760                         status = "disabled";
 761                         compatible = "qcom,i2c-qup-v2.1.1";
 762                         reg = <0xf9967000 0x1000>;
 763                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 765                         clock-names = "core", "iface";
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 769                         dma-names = "tx", "rx";
 770                 };
 771
 772                 blsp_i2c12: i2c@f9968000 {
 773                         status = "disabled";
 774                         compatible = "qcom,i2c-qup-v2.1.1";
 775                         reg = <0xf9968000 0x1000>;
 776                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 777                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 778                         clock-names = "core", "iface";
 779                         #address-cells = <1>;
 780                         #size-cells = <0>;
 781                 };
 782
 783                 spmi_bus: spmi@fc4cf000 {
 784                         compatible = "qcom,spmi-pmic-arb";
 785                         reg-names = "core", "intr", "cnfg";
 786                         reg = <0xfc4cf000 0x1000>,
 787                               <0xfc4cb000 0x1000>,
 788                               <0xfc4ca000 0x1000>;
 789                         interrupt-names = "periph_irq";
 790                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 791                         qcom,ee = <0>;
 792                         qcom,channel = <0>;
 793                         #address-cells = <2>;
 794                         #size-cells = <0>;
 795                         interrupt-controller;
 796                         #interrupt-cells = <4>;
 797                 };
 798
 799                 blsp2_dma: dma-controller@f9944000 {
 800                         compatible = "qcom,bam-v1.4.0";
 801                         reg = <0xf9944000 0x19000>;
 802                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 803                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 804                         clock-names = "bam_clk";
 805                         #dma-cells = <1>;
 806                         qcom,ee = <0>;
 807                 };
 808
 809                 etr@fc322000 {
 810                         compatible = "arm,coresight-tmc", "arm,primecell";
 811                         reg = <0xfc322000 0x1000>;
 812
 813                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 814                         clock-names = "apb_pclk", "atclk";
 815
 816                         in-ports {
 817                                 port {
 818                                         etr_in: endpoint {
 819                                                 remote-endpoint = <&replicator_out0>;
 820                                         };
 821                                 };
 822                         };
 823                 };
 824
 825                 tpiu@fc318000 {
 826                         compatible = "arm,coresight-tpiu", "arm,primecell";
 827                         reg = <0xfc318000 0x1000>;
 828
 829                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 830                         clock-names = "apb_pclk", "atclk";
 831
 832                         in-ports {
 833                                 port {
 834                                         tpiu_in: endpoint {
 835                                                 remote-endpoint = <&replicator_out1>;
 836                                         };
 837                                  };
 838                         };
 839                 };
 840
 841                 replicator@fc31c000 {
 842                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 843                         reg = <0xfc31c000 0x1000>;
 844
 845                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 846                         clock-names = "apb_pclk", "atclk";
 847
 848                         out-ports {
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851
 852                                 port@0 {
 853                                         reg = <0>;
 854                                         replicator_out0: endpoint {
 855                                                 remote-endpoint = <&etr_in>;
 856                                         };
 857                                 };
 858                                 port@1 {
 859                                         reg = <1>;
 860                                         replicator_out1: endpoint {
 861                                                 remote-endpoint = <&tpiu_in>;
 862                                         };
 863                                 };
 864                         };
 865
 866                         in-ports {
 867                                 port {
 868                                         replicator_in: endpoint {
 869                                                 remote-endpoint = <&etf_out>;
 870                                         };
 871                                 };
 872                         };
 873                 };
 874
 875                 etf@fc307000 {
 876                         compatible = "arm,coresight-tmc", "arm,primecell";
 877                         reg = <0xfc307000 0x1000>;
 878
 879                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 880                         clock-names = "apb_pclk", "atclk";
 881
 882                         out-ports {
 883                                 port {
 884                                         etf_out: endpoint {
 885                                                 remote-endpoint = <&replicator_in>;
 886                                         };
 887                                 };
 888                         };
 889
 890                         in-ports {
 891                                 port {
 892                                         etf_in: endpoint {
 893                                                 remote-endpoint = <&merger_out>;
 894                                         };
 895                                 };
 896                         };
 897                 };
 898
 899                 funnel@fc31b000 {
 900                         compatible = "arm,coresight-funnel", "arm,primecell";
 901                         reg = <0xfc31b000 0x1000>;
 902
 903                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 904                         clock-names = "apb_pclk", "atclk";
 905
 906                         in-ports {
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909
 910                                 /*
 911                                  * Not described input ports:
 912                                  * 0 - connected trought funnel to Audio, Modem and
 913                                  *     Resource and Power Manager CPU's
 914                                  * 2...7 - not-connected
 915                                  */
 916                                 port@1 {
 917                                         reg = <1>;
 918                                         merger_in1: endpoint {
 919                                                 remote-endpoint = <&funnel1_out>;
 920                                         };
 921                                 };
 922                         };
 923
 924                         out-ports {
 925                                 port {
 926                                         merger_out: endpoint {
 927                                                 remote-endpoint = <&etf_in>;
 928                                         };
 929                                 };
 930                         };
 931                 };
 932
 933                 funnel@fc31a000 {
 934                         compatible = "arm,coresight-funnel", "arm,primecell";
 935                         reg = <0xfc31a000 0x1000>;
 936
 937                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 938                         clock-names = "apb_pclk", "atclk";
 939
 940                         in-ports {
 941                                 #address-cells = <1>;
 942                                 #size-cells = <0>;
 943
 944                                 /*
 945                                  * Not described input ports:
 946                                  * 0 - not-connected
 947                                  * 1 - connected trought funnel to Multimedia CPU
 948                                  * 2 - connected to Wireless CPU
 949                                  * 3 - not-connected
 950                                  * 4 - not-connected
 951                                  * 6 - not-connected
 952                                  * 7 - connected to STM
 953                                  */
 954                                 port@5 {
 955                                         reg = <5>;
 956                                         funnel1_in5: endpoint {
 957                                                 remote-endpoint = <&kpss_out>;
 958                                         };
 959                                 };
 960                         };
 961
 962                         out-ports {
 963                                 port {
 964                                         funnel1_out: endpoint {
 965                                                 remote-endpoint = <&merger_in1>;
 966                                         };
 967                                 };
 968                         };
 969                 };
 970
 971                 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
 972                         compatible = "arm,coresight-funnel", "arm,primecell";
 973                         reg = <0xfc345000 0x1000>;
 974
 975                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 976                         clock-names = "apb_pclk", "atclk";
 977
 978                         in-ports {
 979                                 #address-cells = <1>;
 980                                 #size-cells = <0>;
 981
 982                                 port@0 {
 983                                         reg = <0>;
 984                                         kpss_in0: endpoint {
 985                                                 remote-endpoint = <&etm0_out>;
 986                                         };
 987                                 };
 988                                 port@1 {
 989                                         reg = <1>;
 990                                         kpss_in1: endpoint {
 991                                                 remote-endpoint = <&etm1_out>;
 992                                         };
 993                                 };
 994                                 port@2 {
 995                                         reg = <2>;
 996                                         kpss_in2: endpoint {
 997                                                 remote-endpoint = <&etm2_out>;
 998                                         };
 999                                 };
1000                                 port@3 {
1001                                         reg = <3>;
1002                                         kpss_in3: endpoint {
1003                                                 remote-endpoint = <&etm3_out>;
1004                                         };
1005                                 };
1006                         };
1007
1008                         out-ports {
1009                                 port {
1010                                         kpss_out: endpoint {
1011                                                 remote-endpoint = <&funnel1_in5>;
1012                                         };
1013                                 };
1014                         };
1015                 };
1016
1017                 etm@fc33c000 {
1018                         compatible = "arm,coresight-etm4x", "arm,primecell";
1019                         reg = <0xfc33c000 0x1000>;
1020
1021                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1022                         clock-names = "apb_pclk", "atclk";
1023
1024                         cpu = <&CPU0>;
1025
1026                         out-ports {
1027                                 port {
1028                                         etm0_out: endpoint {
1029                                                 remote-endpoint = <&kpss_in0>;
1030                                         };
1031                                 };
1032                         };
1033                 };
1034
1035                 etm@fc33d000 {
1036                         compatible = "arm,coresight-etm4x", "arm,primecell";
1037                         reg = <0xfc33d000 0x1000>;
1038
1039                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1040                         clock-names = "apb_pclk", "atclk";
1041
1042                         cpu = <&CPU1>;
1043
1044                         out-ports {
1045                                 port {
1046                                         etm1_out: endpoint {
1047                                                 remote-endpoint = <&kpss_in1>;
1048                                         };
1049                                 };
1050                         };
1051                 };
1052
1053                 etm@fc33e000 {
1054                         compatible = "arm,coresight-etm4x", "arm,primecell";
1055                         reg = <0xfc33e000 0x1000>;
1056
1057                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1058                         clock-names = "apb_pclk", "atclk";
1059
1060                         cpu = <&CPU2>;
1061
1062                         out-ports {
1063                                 port {
1064                                         etm2_out: endpoint {
1065                                                 remote-endpoint = <&kpss_in2>;
1066                                         };
1067                                 };
1068                         };
1069                 };
1070
1071                 etm@fc33f000 {
1072                         compatible = "arm,coresight-etm4x", "arm,primecell";
1073                         reg = <0xfc33f000 0x1000>;
1074
1075                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1076                         clock-names = "apb_pclk", "atclk";
1077
1078                         cpu = <&CPU3>;
1079
1080                         out-ports {
1081                                 port {
1082                                         etm3_out: endpoint {
1083                                                 remote-endpoint = <&kpss_in3>;
1084                                         };
1085                                 };
1086                         };
1087                 };
1088         };
1089
1090         smd {
1091                 compatible = "qcom,smd";
1092
1093                 adsp {
1094                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1095
1096                         qcom,ipc = <&apcs 8 8>;
1097                         qcom,smd-edge = <1>;
1098                 };
1099
1100                 modem {
1101                         interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1102
1103                         qcom,ipc = <&apcs 8 12>;
1104                         qcom,smd-edge = <0>;
1105                 };
1106
1107                 rpm {
1108                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1109                         qcom,ipc = <&apcs 8 0>;
1110                         qcom,smd-edge = <15>;
1111
1112                         rpm_requests {
1113                                 compatible = "qcom,rpm-msm8974";
1114                                 qcom,smd-channels = "rpm_requests";
1115
1116                                 rpmcc: clock-controller {
1117                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1118                                         #clock-cells = <1>;
1119                                 };
1120
1121                                 pm8841-regulators {
1122                                         compatible = "qcom,rpm-pm8841-regulators";
1123
1124                                         pm8841_s1: s1 {};
1125                                         pm8841_s2: s2 {};
1126                                         pm8841_s3: s3 {};
1127                                         pm8841_s4: s4 {};
1128                                         pm8841_s5: s5 {};
1129                                         pm8841_s6: s6 {};
1130                                         pm8841_s7: s7 {};
1131                                         pm8841_s8: s8 {};
1132                                 };
1133
1134                                 pm8941-regulators {
1135                                         compatible = "qcom,rpm-pm8941-regulators";
1136
1137                                         pm8941_s1: s1 {};
1138                                         pm8941_s2: s2 {};
1139                                         pm8941_s3: s3 {};
1140
1141                                         pm8941_l1: l1 {};
1142                                         pm8941_l2: l2 {};
1143                                         pm8941_l3: l3 {};
1144                                         pm8941_l4: l4 {};
1145                                         pm8941_l5: l5 {};
1146                                         pm8941_l6: l6 {};
1147                                         pm8941_l7: l7 {};
1148                                         pm8941_l8: l8 {};
1149                                         pm8941_l9: l9 {};
1150                                         pm8941_l10: l10 {};
1151                                         pm8941_l11: l11 {};
1152                                         pm8941_l12: l12 {};
1153                                         pm8941_l13: l13 {};
1154                                         pm8941_l14: l14 {};
1155                                         pm8941_l15: l15 {};
1156                                         pm8941_l16: l16 {};
1157                                         pm8941_l17: l17 {};
1158                                         pm8941_l18: l18 {};
1159                                         pm8941_l19: l19 {};
1160                                         pm8941_l20: l20 {};
1161                                         pm8941_l21: l21 {};
1162                                         pm8941_l22: l22 {};
1163                                         pm8941_l23: l23 {};
1164                                         pm8941_l24: l24 {};
1165
1166                                         pm8941_lvs1: lvs1 {};
1167                                         pm8941_lvs2: lvs2 {};
1168                                         pm8941_lvs3: lvs3 {};
1169                                 };
1170                         };
1171                 };
1172         };
1173
1174         vreg_boost: vreg-boost {
1175                 compatible = "regulator-fixed";
1176
1177                 regulator-name = "vreg-boost";
1178                 regulator-min-microvolt = <3150000>;
1179                 regulator-max-microvolt = <3150000>;
1180
1181                 regulator-always-on;
1182                 regulator-boot-on;
1183
1184                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1185                 enable-active-high;
1186
1187                 pinctrl-names = "default";
1188                 pinctrl-0 = <&boost_bypass_n_pin>;
1189         };
1190         vreg_vph_pwr: vreg-vph-pwr {
1191                 compatible = "regulator-fixed";
1192                 regulator-name = "vph-pwr";
1193
1194                 regulator-min-microvolt = <3600000>;
1195                 regulator-max-microvolt = <3600000>;
1196
1197                 regulator-always-on;
1198         };
1199 };