arch/arm/boot/dts/qcom-msm8960.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         model = "Qualcomm MSM8960";
  11         compatible = "qcom,msm8960";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 interrupts = <1 14 0x304>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,krait";
  21                         enable-method = "qcom,kpss-acc-v1";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <1>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                 };
  38
  39                 L2: l2-cache {
  40                         compatible = "cache";
  41                         cache-level = <2>;
  42                 };
  43         };
  44
  45         cpu-pmu {
  46                 compatible = "qcom,krait-pmu";
  47                 interrupts = <1 10 0x304>;
  48                 qcom,no-pc-write;
  49         };
  50
  51         soc: soc {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55                 compatible = "simple-bus";
  56
  57                 intc: interrupt-controller@2000000 {
  58                         compatible = "qcom,msm-qgic2";
  59                         interrupt-controller;
  60                         #interrupt-cells = <3>;
  61                         reg = <0x02000000 0x1000>,
  62                               <0x02002000 0x1000>;
  63                 };
  64
  65                 timer@200a000 {
  66                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
  67                         interrupts = <1 1 0x301>,
  68                                      <1 2 0x301>,
  69                                      <1 3 0x301>;
  70                         reg = <0x0200a000 0x100>;
  71                         clock-frequency = <27000000>,
  72                                           <32768>;
  73                         cpu-offset = <0x80000>;
  74                 };
  75
  76                 msmgpio: gpio@800000 {
  77                         compatible = "qcom,msm-gpio";
  78                         gpio-controller;
  79                         #gpio-cells = <2>;
  80                         ngpio = <150>;
  81                         interrupts = <0 16 0x4>;
  82                         interrupt-controller;
  83                         #interrupt-cells = <2>;
  84                         reg = <0x800000 0x4000>;
  85                 };
  86
  87                 gcc: clock-controller@900000 {
  88                         compatible = "qcom,gcc-msm8960";
  89                         #clock-cells = <1>;
  90                         #reset-cells = <1>;
  91                         reg = <0x900000 0x4000>;
  92                 };
  93
  94                 lcc: clock-controller@28000000 {
  95                         compatible = "qcom,lcc-msm8960";
  96                         reg = <0x28000000 0x1000>;
  97                         #clock-cells = <1>;
  98                         #reset-cells = <1>;
  99                 };
 100
 101                 clock-controller@4000000 {
 102                         compatible = "qcom,mmcc-msm8960";
 103                         reg = <0x4000000 0x1000>;
 104                         #clock-cells = <1>;
 105                         #reset-cells = <1>;
 106                 };
 107
 108                 acc0: clock-controller@2088000 {
 109                         compatible = "qcom,kpss-acc-v1";
 110                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 111                 };
 112
 113                 acc1: clock-controller@2098000 {
 114                         compatible = "qcom,kpss-acc-v1";
 115                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 116                 };
 117
 118                 saw0: regulator@2089000 {
 119                         compatible = "qcom,saw2";
 120                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 121                         regulator;
 122                 };
 123
 124                 saw1: regulator@2099000 {
 125                         compatible = "qcom,saw2";
 126                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 127                         regulator;
 128                 };
 129
 130                 gsbi5: gsbi@16400000 {
 131                         compatible = "qcom,gsbi-v1.0.0";
 132                         cell-index = <5>;
 133                         reg = <0x16400000 0x100>;
 134                         clocks = <&gcc GSBI5_H_CLK>;
 135                         clock-names = "iface";
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         syscon-tcsr = <&tcsr>;
 141
 142                         serial@16440000 {
 143                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 144                                 reg = <0x16440000 0x1000>,
 145                                       <0x16400000 0x1000>;
 146                                 interrupts = <0 154 0x0>;
 147                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 148                                 clock-names = "core", "iface";
 149                                 status = "disabled";
 150                         };
 151                 };
 152
 153                 qcom,ssbi@500000 {
 154                         compatible = "qcom,ssbi";
 155                         reg = <0x500000 0x1000>;
 156                         qcom,controller-type = "pmic-arbiter";
 157
 158                         pmicintc: pmic@0 {
 159                                 compatible = "qcom,pm8921";
 160                                 interrupt-parent = <&msmgpio>;
 161                                 interrupts = <104 8>;
 162                                 #interrupt-cells = <2>;
 163                                 interrupt-controller;
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166
 167                                 pwrkey@1c {
 168                                         compatible = "qcom,pm8921-pwrkey";
 169                                         reg = <0x1c>;
 170                                         interrupt-parent = <&pmicintc>;
 171                                         interrupts = <50 1>, <51 1>;
 172                                         debounce = <15625>;
 173                                         pull-up;
 174                                 };
 175
 176                                 keypad@148 {
 177                                         compatible = "qcom,pm8921-keypad";
 178                                         reg = <0x148>;
 179                                         interrupt-parent = <&pmicintc>;
 180                                         interrupts = <74 1>, <75 1>;
 181                                         debounce = <15>;
 182                                         scan-delay = <32>;
 183                                         row-hold = <91500>;
 184                                 };
 185
 186                                 rtc@11d {
 187                                         compatible = "qcom,pm8921-rtc";
 188                                         interrupt-parent = <&pmicintc>;
 189                                         interrupts = <39 1>;
 190                                         reg = <0x11d>;
 191                                         allow-set-time;
 192                                 };
 193                         };
 194                 };
 195
 196                 rng@1a500000 {
 197                         compatible = "qcom,prng";
 198                         reg = <0x1a500000 0x200>;
 199                         clocks = <&gcc PRNG_CLK>;
 200                         clock-names = "core";
 201                 };
 202
 203                 /* Temporary fixed regulator */
 204                 vsdcc_fixed: vsdcc-regulator {
 205                         compatible = "regulator-fixed";
 206                         regulator-name = "SDCC Power";
 207                         regulator-min-microvolt = <2700000>;
 208                         regulator-max-microvolt = <2700000>;
 209                         regulator-always-on;
 210                 };
 211
 212                 amba {
 213                         compatible = "arm,amba-bus";
 214                         #address-cells = <1>;
 215                         #size-cells = <1>;
 216                         ranges;
 217                         sdcc1: sdcc@12400000 {
 218                                 status          = "disabled";
 219                                 compatible      = "arm,pl18x", "arm,primecell";
 220                                 arm,primecell-periphid = <0x00051180>;
 221                                 reg             = <0x12400000 0x8000>;
 222                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 223                                 interrupt-names = "cmd_irq";
 224                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 225                                 clock-names     = "mclk", "apb_pclk";
 226                                 bus-width       = <8>;
 227                                 max-frequency   = <96000000>;
 228                                 non-removable;
 229                                 cap-sd-highspeed;
 230                                 cap-mmc-highspeed;
 231                                 vmmc-supply = <&vsdcc_fixed>;
 232                         };
 233
 234                         sdcc3: sdcc@12180000 {
 235                                 compatible      = "arm,pl18x", "arm,primecell";
 236                                 arm,primecell-periphid = <0x00051180>;
 237                                 status          = "disabled";
 238                                 reg             = <0x12180000 0x8000>;
 239                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 240                                 interrupt-names = "cmd_irq";
 241                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 242                                 clock-names     = "mclk", "apb_pclk";
 243                                 bus-width       = <4>;
 244                                 cap-sd-highspeed;
 245                                 cap-mmc-highspeed;
 246                                 max-frequency   = <192000000>;
 247                                 no-1-8-v;
 248                                 vmmc-supply = <&vsdcc_fixed>;
 249                         };
 250                 };
 251
 252                 tcsr: syscon@1a400000 {
 253                         compatible = "qcom,tcsr-msm8960", "syscon";
 254                         reg = <0x1a400000 0x100>;
 255                 };
 256         };
 257 };