arch/arm/boot/dts/qcom-msm8960.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 /include/ "skeleton.dtsi"
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   8 #include <dt-bindings/mfd/qcom-rpm.h>
   9 #include <dt-bindings/soc/qcom,gsbi.h>
  10
  11 / {
  12         model = "Qualcomm MSM8960";
  13         compatible = "qcom,msm8960";
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 interrupts = <1 14 0x304>;
  20
  21                 cpu@0 {
  22                         compatible = "qcom,krait";
  23                         enable-method = "qcom,kpss-acc-v1";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         next-level-cache = <&L2>;
  27                         qcom,acc = <&acc0>;
  28                         qcom,saw = <&saw0>;
  29                 };
  30
  31                 cpu@1 {
  32                         compatible = "qcom,krait";
  33                         enable-method = "qcom,kpss-acc-v1";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         next-level-cache = <&L2>;
  37                         qcom,acc = <&acc1>;
  38                         qcom,saw = <&saw1>;
  39                 };
  40
  41                 L2: l2-cache {
  42                         compatible = "cache";
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         cpu-pmu {
  48                 compatible = "qcom,krait-pmu";
  49                 interrupts = <1 10 0x304>;
  50                 qcom,no-pc-write;
  51         };
  52
  53         clocks {
  54                 cxo_board {
  55                         compatible = "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <19200000>;
  58                         clock-output-names = "cxo_board";
  59                 };
  60
  61                 pxo_board {
  62                         compatible = "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <27000000>;
  65                         clock-output-names = "pxo_board";
  66                 };
  67
  68                 sleep_clk {
  69                         compatible = "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <32768>;
  72                         clock-output-names = "sleep_clk";
  73                 };
  74         };
  75
  76         soc: soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges;
  80                 compatible = "simple-bus";
  81
  82                 intc: interrupt-controller@2000000 {
  83                         compatible = "qcom,msm-qgic2";
  84                         interrupt-controller;
  85                         #interrupt-cells = <3>;
  86                         reg = <0x02000000 0x1000>,
  87                               <0x02002000 0x1000>;
  88                 };
  89
  90                 timer@200a000 {
  91                         compatible = "qcom,kpss-timer",
  92                                      "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
  93                         interrupts = <1 1 0x301>,
  94                                      <1 2 0x301>,
  95                                      <1 3 0x301>;
  96                         reg = <0x0200a000 0x100>;
  97                         clock-frequency = <27000000>,
  98                                           <32768>;
  99                         cpu-offset = <0x80000>;
 100                 };
 101
 102                 msmgpio: pinctrl@800000 {
 103                         compatible = "qcom,msm8960-pinctrl";
 104                         gpio-controller;
 105                         #gpio-cells = <2>;
 106                         interrupts = <0 16 0x4>;
 107                         interrupt-controller;
 108                         #interrupt-cells = <2>;
 109                         reg = <0x800000 0x4000>;
 110                 };
 111
 112                 gcc: clock-controller@900000 {
 113                         compatible = "qcom,gcc-msm8960";
 114                         #clock-cells = <1>;
 115                         #reset-cells = <1>;
 116                         reg = <0x900000 0x4000>;
 117                 };
 118
 119                 lcc: clock-controller@28000000 {
 120                         compatible = "qcom,lcc-msm8960";
 121                         reg = <0x28000000 0x1000>;
 122                         #clock-cells = <1>;
 123                         #reset-cells = <1>;
 124                 };
 125
 126                 clock-controller@4000000 {
 127                         compatible = "qcom,mmcc-msm8960";
 128                         reg = <0x4000000 0x1000>;
 129                         #clock-cells = <1>;
 130                         #reset-cells = <1>;
 131                 };
 132
 133                 l2cc: clock-controller@2011000 {
 134                         compatible      = "syscon";
 135                         reg             = <0x2011000 0x1000>;
 136                 };
 137
 138                 rpm@108000 {
 139                         compatible      = "qcom,rpm-msm8960";
 140                         reg             = <0x108000 0x1000>;
 141                         qcom,ipc        = <&l2cc 0x8 2>;
 142
 143                         interrupts      = <0 19 0>, <0 21 0>, <0 22 0>;
 144                         interrupt-names = "ack", "err", "wakeup";
 145
 146                         regulators {
 147                                 compatible = "qcom,rpm-pm8921-regulators";
 148                         };
 149                 };
 150
 151                 acc0: clock-controller@2088000 {
 152                         compatible = "qcom,kpss-acc-v1";
 153                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 154                 };
 155
 156                 acc1: clock-controller@2098000 {
 157                         compatible = "qcom,kpss-acc-v1";
 158                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 159                 };
 160
 161                 saw0: regulator@2089000 {
 162                         compatible = "qcom,saw2";
 163                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 164                         regulator;
 165                 };
 166
 167                 saw1: regulator@2099000 {
 168                         compatible = "qcom,saw2";
 169                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 170                         regulator;
 171                 };
 172
 173                 gsbi5: gsbi@16400000 {
 174                         compatible = "qcom,gsbi-v1.0.0";
 175                         cell-index = <5>;
 176                         reg = <0x16400000 0x100>;
 177                         clocks = <&gcc GSBI5_H_CLK>;
 178                         clock-names = "iface";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         ranges;
 182
 183                         syscon-tcsr = <&tcsr>;
 184
 185                         gsbi5_serial: serial@16440000 {
 186                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 187                                 reg = <0x16440000 0x1000>,
 188                                       <0x16400000 0x1000>;
 189                                 interrupts = <0 154 0x0>;
 190                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 191                                 clock-names = "core", "iface";
 192                                 status = "disabled";
 193                         };
 194                 };
 195
 196                 qcom,ssbi@500000 {
 197                         compatible = "qcom,ssbi";
 198                         reg = <0x500000 0x1000>;
 199                         qcom,controller-type = "pmic-arbiter";
 200
 201                         pmicintc: pmic@0 {
 202                                 compatible = "qcom,pm8921";
 203                                 interrupt-parent = <&msmgpio>;
 204                                 interrupts = <104 8>;
 205                                 #interrupt-cells = <2>;
 206                                 interrupt-controller;
 207                                 #address-cells = <1>;
 208                                 #size-cells = <0>;
 209
 210                                 pwrkey@1c {
 211                                         compatible = "qcom,pm8921-pwrkey";
 212                                         reg = <0x1c>;
 213                                         interrupt-parent = <&pmicintc>;
 214                                         interrupts = <50 1>, <51 1>;
 215                                         debounce = <15625>;
 216                                         pull-up;
 217                                 };
 218
 219                                 keypad@148 {
 220                                         compatible = "qcom,pm8921-keypad";
 221                                         reg = <0x148>;
 222                                         interrupt-parent = <&pmicintc>;
 223                                         interrupts = <74 1>, <75 1>;
 224                                         debounce = <15>;
 225                                         scan-delay = <32>;
 226                                         row-hold = <91500>;
 227                                 };
 228
 229                                 rtc@11d {
 230                                         compatible = "qcom,pm8921-rtc";
 231                                         interrupt-parent = <&pmicintc>;
 232                                         interrupts = <39 1>;
 233                                         reg = <0x11d>;
 234                                         allow-set-time;
 235                                 };
 236                         };
 237                 };
 238
 239                 rng@1a500000 {
 240                         compatible = "qcom,prng";
 241                         reg = <0x1a500000 0x200>;
 242                         clocks = <&gcc PRNG_CLK>;
 243                         clock-names = "core";
 244                 };
 245
 246                 /* Temporary fixed regulator */
 247                 vsdcc_fixed: vsdcc-regulator {
 248                         compatible = "regulator-fixed";
 249                         regulator-name = "SDCC Power";
 250                         regulator-min-microvolt = <2700000>;
 251                         regulator-max-microvolt = <2700000>;
 252                         regulator-always-on;
 253                 };
 254
 255                 amba {
 256                         compatible = "simple-bus";
 257                         #address-cells = <1>;
 258                         #size-cells = <1>;
 259                         ranges;
 260                         sdcc1: sdcc@12400000 {
 261                                 status          = "disabled";
 262                                 compatible      = "arm,pl18x", "arm,primecell";
 263                                 arm,primecell-periphid = <0x00051180>;
 264                                 reg             = <0x12400000 0x8000>;
 265                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 266                                 interrupt-names = "cmd_irq";
 267                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 268                                 clock-names     = "mclk", "apb_pclk";
 269                                 bus-width       = <8>;
 270                                 max-frequency   = <96000000>;
 271                                 non-removable;
 272                                 cap-sd-highspeed;
 273                                 cap-mmc-highspeed;
 274                                 vmmc-supply = <&vsdcc_fixed>;
 275                         };
 276
 277                         sdcc3: sdcc@12180000 {
 278                                 compatible      = "arm,pl18x", "arm,primecell";
 279                                 arm,primecell-periphid = <0x00051180>;
 280                                 status          = "disabled";
 281                                 reg             = <0x12180000 0x8000>;
 282                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 283                                 interrupt-names = "cmd_irq";
 284                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 285                                 clock-names     = "mclk", "apb_pclk";
 286                                 bus-width       = <4>;
 287                                 cap-sd-highspeed;
 288                                 cap-mmc-highspeed;
 289                                 max-frequency   = <192000000>;
 290                                 no-1-8-v;
 291                                 vmmc-supply = <&vsdcc_fixed>;
 292                         };
 293                 };
 294
 295                 tcsr: syscon@1a400000 {
 296                         compatible = "qcom,tcsr-msm8960", "syscon";
 297                         reg = <0x1a400000 0x100>;
 298                 };
 299
 300                 gsbi@16000000 {
 301                         compatible = "qcom,gsbi-v1.0.0";
 302                         cell-index = <1>;
 303                         reg = <0x16000000 0x100>;
 304                         clocks = <&gcc GSBI1_H_CLK>;
 305                         clock-names = "iface";
 306                         #address-cells = <1>;
 307                         #size-cells = <1>;
 308                         ranges;
 309
 310                         spi@16080000 {
 311                                 compatible = "qcom,spi-qup-v1.1.1";
 312                                 #address-cells = <1>;
 313                                 #size-cells = <0>;
 314                                 reg = <0x16080000 0x1000>;
 315                                 interrupts = <0 147 0>;
 316                                 spi-max-frequency = <24000000>;
 317                                 cs-gpios = <&msmgpio 8 0>;
 318
 319                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 320                                 clock-names = "core", "iface";
 321                                 status = "disabled";
 322                         };
 323                 };
 324         };
 325 };