arch/arm/boot/dts/qcom-msm8660.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         model = "Qualcomm MSM8660";
  11         compatible = "qcom,msm8660";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,scorpion";
  20                         enable-method = "qcom,gcc-msm8660";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "qcom,scorpion";
  28                         enable-method = "qcom,gcc-msm8660";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         next-level-cache = <&L2>;
  32                 };
  33
  34                 L2: l2-cache {
  35                         compatible = "cache";
  36                         cache-level = <2>;
  37                 };
  38         };
  39
  40         soc: soc {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 ranges;
  44                 compatible = "simple-bus";
  45
  46                 intc: interrupt-controller@2080000 {
  47                         compatible = "qcom,msm-8660-qgic";
  48                         interrupt-controller;
  49                         #interrupt-cells = <3>;
  50                         reg = < 0x02080000 0x1000 >,
  51                               < 0x02081000 0x1000 >;
  52                 };
  53
  54                 timer@2000000 {
  55                         compatible = "qcom,scss-timer", "qcom,msm-timer";
  56                         interrupts = <1 0 0x301>,
  57                                      <1 1 0x301>,
  58                                      <1 2 0x301>;
  59                         reg = <0x02000000 0x100>;
  60                         clock-frequency = <27000000>,
  61                                           <32768>;
  62                         cpu-offset = <0x40000>;
  63                 };
  64
  65                 msmgpio: gpio@800000 {
  66                         compatible = "qcom,msm-gpio";
  67                         reg = <0x00800000 0x4000>;
  68                         gpio-controller;
  69                         #gpio-cells = <2>;
  70                         ngpio = <173>;
  71                         interrupts = <0 16 0x4>;
  72                         interrupt-controller;
  73                         #interrupt-cells = <2>;
  74                 };
  75
  76                 gcc: clock-controller@900000 {
  77                         compatible = "qcom,gcc-msm8660";
  78                         #clock-cells = <1>;
  79                         #reset-cells = <1>;
  80                         reg = <0x900000 0x4000>;
  81                 };
  82
  83                 gsbi12: gsbi@19c00000 {
  84                         compatible = "qcom,gsbi-v1.0.0";
  85                         cell-index = <12>;
  86                         reg = <0x19c00000 0x100>;
  87                         clocks = <&gcc GSBI12_H_CLK>;
  88                         clock-names = "iface";
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         ranges;
  92
  93                         syscon-tcsr = <&tcsr>;
  94
  95                         serial@19c40000 {
  96                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  97                                 reg = <0x19c40000 0x1000>,
  98                                       <0x19c00000 0x1000>;
  99                                 interrupts = <0 195 0x0>;
 100                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 101                                 clock-names = "core", "iface";
 102                                 status = "disabled";
 103                         };
 104                 };
 105
 106                 qcom,ssbi@500000 {
 107                         compatible = "qcom,ssbi";
 108                         reg = <0x500000 0x1000>;
 109                         qcom,controller-type = "pmic-arbiter";
 110
 111                         pmicintc: pmic@0 {
 112                                 compatible = "qcom,pm8058";
 113                                 interrupt-parent = <&msmgpio>;
 114                                 interrupts = <88 8>;
 115                                 #interrupt-cells = <2>;
 116                                 interrupt-controller;
 117                                 #address-cells = <1>;
 118                                 #size-cells = <0>;
 119
 120                                 pwrkey@1c {
 121                                         compatible = "qcom,pm8058-pwrkey";
 122                                         reg = <0x1c>;
 123                                         interrupt-parent = <&pmicintc>;
 124                                         interrupts = <50 1>, <51 1>;
 125                                         debounce = <15625>;
 126                                         pull-up;
 127                                 };
 128
 129                                 keypad@148 {
 130                                         compatible = "qcom,pm8058-keypad";
 131                                         reg = <0x148>;
 132                                         interrupt-parent = <&pmicintc>;
 133                                         interrupts = <74 1>, <75 1>;
 134                                         debounce = <15>;
 135                                         scan-delay = <32>;
 136                                         row-hold = <91500>;
 137                                 };
 138
 139                                 rtc@11d {
 140                                         compatible = "qcom,pm8058-rtc";
 141                                         interrupt-parent = <&pmicintc>;
 142                                         interrupts = <39 1>;
 143                                         reg = <0x11d>;
 144                                         allow-set-time;
 145                                 };
 146
 147                                 vibrator@4a {
 148                                         compatible = "qcom,pm8058-vib";
 149                                         reg = <0x4a>;
 150                                 };
 151                         };
 152                 };
 153
 154                 /* Temporary fixed regulator */
 155                 vsdcc_fixed: vsdcc-regulator {
 156                         compatible = "regulator-fixed";
 157                         regulator-name = "SDCC Power";
 158                         regulator-min-microvolt = <2700000>;
 159                         regulator-max-microvolt = <2700000>;
 160                         regulator-always-on;
 161                 };
 162
 163                 amba {
 164                         compatible = "arm,amba-bus";
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         ranges;
 168                         sdcc1: sdcc@12400000 {
 169                                 status          = "disabled";
 170                                 compatible      = "arm,pl18x", "arm,primecell";
 171                                 arm,primecell-periphid = <0x00051180>;
 172                                 reg             = <0x12400000 0x8000>;
 173                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 174                                 interrupt-names = "cmd_irq";
 175                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 176                                 clock-names     = "mclk", "apb_pclk";
 177                                 bus-width       = <8>;
 178                                 max-frequency   = <48000000>;
 179                                 non-removable;
 180                                 cap-sd-highspeed;
 181                                 cap-mmc-highspeed;
 182                                 vmmc-supply = <&vsdcc_fixed>;
 183                         };
 184
 185                         sdcc3: sdcc@12180000 {
 186                                 compatible      = "arm,pl18x", "arm,primecell";
 187                                 arm,primecell-periphid = <0x00051180>;
 188                                 status          = "disabled";
 189                                 reg             = <0x12180000 0x8000>;
 190                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 191                                 interrupt-names = "cmd_irq";
 192                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 193                                 clock-names     = "mclk", "apb_pclk";
 194                                 bus-width       = <4>;
 195                                 cap-sd-highspeed;
 196                                 cap-mmc-highspeed;
 197                                 max-frequency   = <48000000>;
 198                                 no-1-8-v;
 199                                 vmmc-supply = <&vsdcc_fixed>;
 200                         };
 201                 };
 202
 203                 tcsr: syscon@1a400000 {
 204                         compatible = "qcom,tcsr-msm8660", "syscon";
 205                         reg = <0x1a400000 0x100>;
 206                 };
 207         };
 208
 209 };