arch/arm/boot/dts/qcom-msm8660.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9
  10 / {
  11         model = "Qualcomm MSM8660";
  12         compatible = "qcom,msm8660";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,scorpion";
  21                         enable-method = "qcom,gcc-msm8660";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                 };
  26
  27                 cpu@1 {
  28                         compatible = "qcom,scorpion";
  29                         enable-method = "qcom,gcc-msm8660";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         next-level-cache = <&L2>;
  33                 };
  34
  35                 L2: l2-cache {
  36                         compatible = "cache";
  37                         cache-level = <2>;
  38                 };
  39         };
  40
  41         cpu-pmu {
  42                 compatible = "qcom,scorpion-mp-pmu";
  43                 interrupts = <1 9 0x304>;
  44         };
  45
  46         clocks {
  47                 cxo_board {
  48                         compatible = "fixed-clock";
  49                         #clock-cells = <0>;
  50                         clock-frequency = <19200000>;
  51                 };
  52
  53                 pxo_board {
  54                         compatible = "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <27000000>;
  57                 };
  58
  59                 sleep_clk {
  60                         compatible = "fixed-clock";
  61                         #clock-cells = <0>;
  62                         clock-frequency = <32768>;
  63                 };
  64         };
  65
  66         /*
  67          * These channels from the ADC are simply hardware monitors.
  68          * That is why the ADC is referred to as "HKADC" - HouseKeeping
  69          * ADC.
  70          */
  71         iio-hwmon {
  72                 compatible = "iio-hwmon";
  73                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
  74                             <&xoadc 0x00 0x02>, /* DC in (charger) */
  75                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
  76                             <&xoadc 0x00 0x0b>, /* Die temperature */
  77                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
  78                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
  79                             <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
  80         };
  81
  82         soc: soc {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 ranges;
  86                 compatible = "simple-bus";
  87
  88                 intc: interrupt-controller@2080000 {
  89                         compatible = "qcom,msm-8660-qgic";
  90                         interrupt-controller;
  91                         #interrupt-cells = <3>;
  92                         reg = < 0x02080000 0x1000 >,
  93                               < 0x02081000 0x1000 >;
  94                 };
  95
  96                 timer@2000000 {
  97                         compatible = "qcom,scss-timer", "qcom,msm-timer";
  98                         interrupts = <1 0 0x301>,
  99                                      <1 1 0x301>,
 100                                      <1 2 0x301>;
 101                         reg = <0x02000000 0x100>;
 102                         clock-frequency = <27000000>,
 103                                           <32768>;
 104                         cpu-offset = <0x40000>;
 105                 };
 106
 107                 tlmm: pinctrl@800000 {
 108                         compatible = "qcom,msm8660-pinctrl";
 109                         reg = <0x800000 0x4000>;
 110
 111                         gpio-controller;
 112                         #gpio-cells = <2>;
 113                         interrupts = <0 16 0x4>;
 114                         interrupt-controller;
 115                         #interrupt-cells = <2>;
 116
 117                 };
 118
 119                 gcc: clock-controller@900000 {
 120                         compatible = "qcom,gcc-msm8660";
 121                         #clock-cells = <1>;
 122                         #reset-cells = <1>;
 123                         reg = <0x900000 0x4000>;
 124                 };
 125
 126
 127                 gsbi8: gsbi@19800000 {
 128                         compatible = "qcom,gsbi-v1.0.0";
 129                         cell-index = <12>;
 130                         reg = <0x19800000 0x100>;
 131                         clocks = <&gcc GSBI8_H_CLK>;
 132                         clock-names = "iface";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         ranges;
 136
 137                         syscon-tcsr = <&tcsr>;
 138
 139                         gsbi8_i2c: i2c@19880000 {
 140                                 compatible = "qcom,i2c-qup-v1.1.1";
 141                                 reg = <0x19880000 0x1000>;
 142                                 interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
 143                                 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
 144                                 clock-names = "core", "iface";
 145                                 #address-cells = <1>;
 146                                 #size-cells = <0>;
 147                                 status = "disabled";
 148                         };
 149                 };
 150
 151                 gsbi12: gsbi@19c00000 {
 152                         compatible = "qcom,gsbi-v1.0.0";
 153                         cell-index = <12>;
 154                         reg = <0x19c00000 0x100>;
 155                         clocks = <&gcc GSBI12_H_CLK>;
 156                         clock-names = "iface";
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         ranges;
 160
 161                         syscon-tcsr = <&tcsr>;
 162
 163                         gsbi12_serial: serial@19c40000 {
 164                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 165                                 reg = <0x19c40000 0x1000>,
 166                                       <0x19c00000 0x1000>;
 167                                 interrupts = <0 195 IRQ_TYPE_NONE>;
 168                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 169                                 clock-names = "core", "iface";
 170                                 status = "disabled";
 171                         };
 172
 173                         gsbi12_i2c: i2c@19c80000 {
 174                                 compatible = "qcom,i2c-qup-v1.1.1";
 175                                 reg = <0x19c80000 0x1000>;
 176                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 177                                 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
 178                                 clock-names = "core", "iface";
 179                                 #address-cells = <1>;
 180                                 #size-cells = <0>;
 181                                 status = "disabled";
 182                         };
 183                 };
 184
 185                 external-bus@1a100000 {
 186                         compatible = "qcom,msm8660-ebi2";
 187                         #address-cells = <2>;
 188                         #size-cells = <1>;
 189                         ranges = <0 0x0 0x1a800000 0x00800000>,
 190                                  <1 0x0 0x1b000000 0x00800000>,
 191                                  <2 0x0 0x1b800000 0x00800000>,
 192                                  <3 0x0 0x1d000000 0x08000000>,
 193                                  <4 0x0 0x1c800000 0x00800000>,
 194                                  <5 0x0 0x1c000000 0x00800000>;
 195                         reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
 196                         reg-names = "ebi2", "xmem";
 197                         clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
 198                         clock-names = "ebi2x", "ebi2";
 199                         status = "disabled";
 200                 };
 201
 202                 qcom,ssbi@500000 {
 203                         compatible = "qcom,ssbi";
 204                         reg = <0x500000 0x1000>;
 205                         qcom,controller-type = "pmic-arbiter";
 206
 207                         pm8058: pmic@0 {
 208                                 compatible = "qcom,pm8058";
 209                                 interrupt-parent = <&tlmm>;
 210                                 interrupts = <88 8>;
 211                                 #interrupt-cells = <2>;
 212                                 interrupt-controller;
 213                                 #address-cells = <1>;
 214                                 #size-cells = <0>;
 215
 216                                 pm8058_gpio: gpio@150 {
 217                                         compatible = "qcom,pm8058-gpio",
 218                                                      "qcom,ssbi-gpio";
 219                                         reg = <0x150>;
 220                                         interrupt-parent = <&pm8058>;
 221                                         interrupts = <192 IRQ_TYPE_NONE>,
 222                                                      <193 IRQ_TYPE_NONE>,
 223                                                      <194 IRQ_TYPE_NONE>,
 224                                                      <195 IRQ_TYPE_NONE>,
 225                                                      <196 IRQ_TYPE_NONE>,
 226                                                      <197 IRQ_TYPE_NONE>,
 227                                                      <198 IRQ_TYPE_NONE>,
 228                                                      <199 IRQ_TYPE_NONE>,
 229                                                      <200 IRQ_TYPE_NONE>,
 230                                                      <201 IRQ_TYPE_NONE>,
 231                                                      <202 IRQ_TYPE_NONE>,
 232                                                      <203 IRQ_TYPE_NONE>,
 233                                                      <204 IRQ_TYPE_NONE>,
 234                                                      <205 IRQ_TYPE_NONE>,
 235                                                      <206 IRQ_TYPE_NONE>,
 236                                                      <207 IRQ_TYPE_NONE>,
 237                                                      <208 IRQ_TYPE_NONE>,
 238                                                      <209 IRQ_TYPE_NONE>,
 239                                                      <210 IRQ_TYPE_NONE>,
 240                                                      <211 IRQ_TYPE_NONE>,
 241                                                      <212 IRQ_TYPE_NONE>,
 242                                                      <213 IRQ_TYPE_NONE>,
 243                                                      <214 IRQ_TYPE_NONE>,
 244                                                      <215 IRQ_TYPE_NONE>,
 245                                                      <216 IRQ_TYPE_NONE>,
 246                                                      <217 IRQ_TYPE_NONE>,
 247                                                      <218 IRQ_TYPE_NONE>,
 248                                                      <219 IRQ_TYPE_NONE>,
 249                                                      <220 IRQ_TYPE_NONE>,
 250                                                      <221 IRQ_TYPE_NONE>,
 251                                                      <222 IRQ_TYPE_NONE>,
 252                                                      <223 IRQ_TYPE_NONE>,
 253                                                      <224 IRQ_TYPE_NONE>,
 254                                                      <225 IRQ_TYPE_NONE>,
 255                                                      <226 IRQ_TYPE_NONE>,
 256                                                      <227 IRQ_TYPE_NONE>,
 257                                                      <228 IRQ_TYPE_NONE>,
 258                                                      <229 IRQ_TYPE_NONE>,
 259                                                      <230 IRQ_TYPE_NONE>,
 260                                                      <231 IRQ_TYPE_NONE>,
 261                                                      <232 IRQ_TYPE_NONE>,
 262                                                      <233 IRQ_TYPE_NONE>,
 263                                                      <234 IRQ_TYPE_NONE>,
 264                                                      <235 IRQ_TYPE_NONE>;
 265                                         gpio-controller;
 266                                         #gpio-cells = <2>;
 267
 268                                 };
 269
 270                                 pm8058_mpps: mpps@50 {
 271                                         compatible = "qcom,pm8058-mpp",
 272                                                      "qcom,ssbi-mpp";
 273                                         reg = <0x50>;
 274                                         gpio-controller;
 275                                         #gpio-cells = <2>;
 276                                         interrupt-parent = <&pm8058>;
 277                                         interrupts =
 278                                         <128 IRQ_TYPE_NONE>,
 279                                         <129 IRQ_TYPE_NONE>,
 280                                         <130 IRQ_TYPE_NONE>,
 281                                         <131 IRQ_TYPE_NONE>,
 282                                         <132 IRQ_TYPE_NONE>,
 283                                         <133 IRQ_TYPE_NONE>,
 284                                         <134 IRQ_TYPE_NONE>,
 285                                         <135 IRQ_TYPE_NONE>,
 286                                         <136 IRQ_TYPE_NONE>,
 287                                         <137 IRQ_TYPE_NONE>,
 288                                         <138 IRQ_TYPE_NONE>,
 289                                         <139 IRQ_TYPE_NONE>;
 290                                 };
 291
 292                                 pwrkey@1c {
 293                                         compatible = "qcom,pm8058-pwrkey";
 294                                         reg = <0x1c>;
 295                                         interrupt-parent = <&pm8058>;
 296                                         interrupts = <50 1>, <51 1>;
 297                                         debounce = <15625>;
 298                                         pull-up;
 299                                 };
 300
 301                                 keypad@148 {
 302                                         compatible = "qcom,pm8058-keypad";
 303                                         reg = <0x148>;
 304                                         interrupt-parent = <&pm8058>;
 305                                         interrupts = <74 1>, <75 1>;
 306                                         debounce = <15>;
 307                                         scan-delay = <32>;
 308                                         row-hold = <91500>;
 309                                 };
 310
 311                                 xoadc: xoadc@197 {
 312                                         compatible = "qcom,pm8058-adc";
 313                                         reg = <0x197>;
 314                                         interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
 315                                         #address-cells = <2>;
 316                                         #size-cells = <0>;
 317                                         #io-channel-cells = <2>;
 318
 319                                         vcoin: adc-channel@00 {
 320                                                 reg = <0x00 0x00>;
 321                                         };
 322                                         vbat: adc-channel@01 {
 323                                                 reg = <0x00 0x01>;
 324                                         };
 325                                         dcin: adc-channel@02 {
 326                                                 reg = <0x00 0x02>;
 327                                         };
 328                                         ichg: adc-channel@03 {
 329                                                 reg = <0x00 0x03>;
 330                                         };
 331                                         vph_pwr: adc-channel@04 {
 332                                                 reg = <0x00 0x04>;
 333                                         };
 334                                         usb_vbus: adc-channel@0a {
 335                                                 reg = <0x00 0x0a>;
 336                                         };
 337                                         die_temp: adc-channel@0b {
 338                                                 reg = <0x00 0x0b>;
 339                                         };
 340                                         ref_625mv: adc-channel@0c {
 341                                                 reg = <0x00 0x0c>;
 342                                         };
 343                                         ref_1250mv: adc-channel@0d {
 344                                                 reg = <0x00 0x0d>;
 345                                         };
 346                                         ref_325mv: adc-channel@0e {
 347                                                 reg = <0x00 0x0e>;
 348                                         };
 349                                         ref_muxoff: adc-channel@0f {
 350                                                 reg = <0x00 0x0f>;
 351                                         };
 352                                 };
 353
 354                                 rtc@1e8 {
 355                                         compatible = "qcom,pm8058-rtc";
 356                                         reg = <0x1e8>;
 357                                         interrupt-parent = <&pm8058>;
 358                                         interrupts = <39 1>;
 359                                         allow-set-time;
 360                                 };
 361
 362                                 vibrator@4a {
 363                                         compatible = "qcom,pm8058-vib";
 364                                         reg = <0x4a>;
 365                                 };
 366                         };
 367                 };
 368
 369                 l2cc: clock-controller@2082000 {
 370                         compatible      = "syscon";
 371                         reg             = <0x02082000 0x1000>;
 372                 };
 373
 374                 rpm: rpm@104000 {
 375                         compatible      = "qcom,rpm-msm8660";
 376                         reg             = <0x00104000 0x1000>;
 377                         qcom,ipc        = <&l2cc 0x8 2>;
 378
 379                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 380                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 381                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 382                         interrupt-names = "ack", "err", "wakeup";
 383                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 384                         clock-names = "ram";
 385
 386                         rpmcc: clock-controller {
 387                                 compatible      = "qcom,rpmcc-apq8660", "qcom,rpmcc";
 388                                 #clock-cells = <1>;
 389                         };
 390
 391                         pm8901-regulators {
 392                                 compatible = "qcom,rpm-pm8901-regulators";
 393
 394                                 pm8901_l0: l0 {};
 395                                 pm8901_l1: l1 {};
 396                                 pm8901_l2: l2 {};
 397                                 pm8901_l3: l3 {};
 398                                 pm8901_l4: l4 {};
 399                                 pm8901_l5: l5 {};
 400                                 pm8901_l6: l6 {};
 401
 402                                 /* S0 and S1 Handled as SAW regulators by SPM */
 403                                 pm8901_s2: s2 {};
 404                                 pm8901_s3: s3 {};
 405                                 pm8901_s4: s4 {};
 406
 407                                 pm8901_lvs0: lvs0 {};
 408                                 pm8901_lvs1: lvs1 {};
 409                                 pm8901_lvs2: lvs2 {};
 410                                 pm8901_lvs3: lvs3 {};
 411
 412                                 pm8901_mvs: mvs {};
 413                         };
 414
 415                         pm8058-regulators {
 416                                 compatible = "qcom,rpm-pm8058-regulators";
 417
 418                                 pm8058_l0: l0 {};
 419                                 pm8058_l1: l1 {};
 420                                 pm8058_l2: l2 {};
 421                                 pm8058_l3: l3 {};
 422                                 pm8058_l4: l4 {};
 423                                 pm8058_l5: l5 {};
 424                                 pm8058_l6: l6 {};
 425                                 pm8058_l7: l7 {};
 426                                 pm8058_l8: l8 {};
 427                                 pm8058_l9: l9 {};
 428                                 pm8058_l10: l10 {};
 429                                 pm8058_l11: l11 {};
 430                                 pm8058_l12: l12 {};
 431                                 pm8058_l13: l13 {};
 432                                 pm8058_l14: l14 {};
 433                                 pm8058_l15: l15 {};
 434                                 pm8058_l16: l16 {};
 435                                 pm8058_l17: l17 {};
 436                                 pm8058_l18: l18 {};
 437                                 pm8058_l19: l19 {};
 438                                 pm8058_l20: l20 {};
 439                                 pm8058_l21: l21 {};
 440                                 pm8058_l22: l22 {};
 441                                 pm8058_l23: l23 {};
 442                                 pm8058_l24: l24 {};
 443                                 pm8058_l25: l25 {};
 444
 445                                 pm8058_s0: s0 {};
 446                                 pm8058_s1: s1 {};
 447                                 pm8058_s2: s2 {};
 448                                 pm8058_s3: s3 {};
 449                                 pm8058_s4: s4 {};
 450
 451                                 pm8058_lvs0: lvs0 {};
 452                                 pm8058_lvs1: lvs1 {};
 453
 454                                 pm8058_ncp: ncp {};
 455                         };
 456                 };
 457
 458                 amba {
 459                         compatible = "simple-bus";
 460                         #address-cells = <1>;
 461                         #size-cells = <1>;
 462                         ranges;
 463                         sdcc1: sdcc@12400000 {
 464                                 status          = "disabled";
 465                                 compatible      = "arm,pl18x", "arm,primecell";
 466                                 arm,primecell-periphid = <0x00051180>;
 467                                 reg             = <0x12400000 0x8000>;
 468                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 469                                 interrupt-names = "cmd_irq";
 470                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 471                                 clock-names     = "mclk", "apb_pclk";
 472                                 bus-width       = <8>;
 473                                 max-frequency   = <48000000>;
 474                                 non-removable;
 475                                 cap-sd-highspeed;
 476                                 cap-mmc-highspeed;
 477                         };
 478
 479                         sdcc2: sdcc@12140000 {
 480                                 status          = "disabled";
 481                                 compatible      = "arm,pl18x", "arm,primecell";
 482                                 arm,primecell-periphid = <0x00051180>;
 483                                 reg             = <0x12140000 0x8000>;
 484                                 interrupts      = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 485                                 interrupt-names = "cmd_irq";
 486                                 clocks          = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 487                                 clock-names     = "mclk", "apb_pclk";
 488                                 bus-width       = <8>;
 489                                 max-frequency   = <48000000>;
 490                                 cap-sd-highspeed;
 491                                 cap-mmc-highspeed;
 492                         };
 493
 494                         sdcc3: sdcc@12180000 {
 495                                 compatible      = "arm,pl18x", "arm,primecell";
 496                                 arm,primecell-periphid = <0x00051180>;
 497                                 status          = "disabled";
 498                                 reg             = <0x12180000 0x8000>;
 499                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 500                                 interrupt-names = "cmd_irq";
 501                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 502                                 clock-names     = "mclk", "apb_pclk";
 503                                 bus-width       = <4>;
 504                                 cap-sd-highspeed;
 505                                 cap-mmc-highspeed;
 506                                 max-frequency   = <48000000>;
 507                                 no-1-8-v;
 508                         };
 509
 510                         sdcc4: sdcc@121c0000 {
 511                                 compatible      = "arm,pl18x", "arm,primecell";
 512                                 arm,primecell-periphid = <0x00051180>;
 513                                 status          = "disabled";
 514                                 reg             = <0x121c0000 0x8000>;
 515                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 516                                 interrupt-names = "cmd_irq";
 517                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 518                                 clock-names     = "mclk", "apb_pclk";
 519                                 bus-width       = <4>;
 520                                 max-frequency   = <48000000>;
 521                                 cap-sd-highspeed;
 522                                 cap-mmc-highspeed;
 523                         };
 524
 525                         sdcc5: sdcc@12200000 {
 526                                 compatible      = "arm,pl18x", "arm,primecell";
 527                                 arm,primecell-periphid = <0x00051180>;
 528                                 status          = "disabled";
 529                                 reg             = <0x12200000 0x8000>;
 530                                 interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 531                                 interrupt-names = "cmd_irq";
 532                                 clocks          = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
 533                                 clock-names     = "mclk", "apb_pclk";
 534                                 bus-width       = <4>;
 535                                 cap-sd-highspeed;
 536                                 cap-mmc-highspeed;
 537                                 max-frequency   = <48000000>;
 538                         };
 539                 };
 540
 541                 tcsr: syscon@1a400000 {
 542                         compatible = "qcom,tcsr-msm8660", "syscon";
 543                         reg = <0x1a400000 0x100>;
 544                 };
 545         };
 546
 547 };