arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include "skeleton.dtsi"
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/soc/qcom,gsbi.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                 };
  31
  32                 cpu@1 {
  33                         compatible = "qcom,krait";
  34                         enable-method = "qcom,kpss-acc-v1";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc1>;
  39                         qcom,saw = <&saw1>;
  40                 };
  41
  42                 L2: l2-cache {
  43                         compatible = "cache";
  44                         cache-level = <2>;
  45                 };
  46         };
  47
  48         cpu-pmu {
  49                 compatible = "qcom,krait-pmu";
  50                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  51                                           IRQ_TYPE_LEVEL_HIGH)>;
  52         };
  53
  54         reserved-memory {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 nss@40000000 {
  60                         reg = <0x40000000 0x1000000>;
  61                         no-map;
  62                 };
  63
  64                 smem@41000000 {
  65                         reg = <0x41000000 0x200000>;
  66                         no-map;
  67                 };
  68         };
  69
  70         clocks {
  71                 cxo_board {
  72                         compatible = "fixed-clock";
  73                         #clock-cells = <0>;
  74                         clock-frequency = <25000000>;
  75                 };
  76
  77                 pxo_board {
  78                         compatible = "fixed-clock";
  79                         #clock-cells = <0>;
  80                         clock-frequency = <25000000>;
  81                 };
  82
  83                 sleep_clk: sleep_clk {
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         #clock-cells = <0>;
  87                 };
  88         };
  89
  90         soc: soc {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94                 compatible = "simple-bus";
  95
  96                 lpass@28100000 {
  97                         compatible = "qcom,lpass-cpu";
  98                         status = "disabled";
  99                         clocks = <&lcc AHBIX_CLK>,
 100                                         <&lcc MI2S_OSR_CLK>,
 101                                         <&lcc MI2S_BIT_CLK>;
 102                         clock-names = "ahbix-clk",
 103                                         "mi2s-osr-clk",
 104                                         "mi2s-bit-clk";
 105                         interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
 106                         interrupt-names = "lpass-irq-lpaif";
 107                         reg = <0x28100000 0x10000>;
 108                         reg-names = "lpass-lpaif";
 109                 };
 110
 111                 qcom_pinmux: pinmux@800000 {
 112                         compatible = "qcom,ipq8064-pinctrl";
 113                         reg = <0x800000 0x4000>;
 114
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117                         interrupt-controller;
 118                         #interrupt-cells = <2>;
 119                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 120
 121                         pcie0_pins: pcie0_pinmux {
 122                                 mux {
 123                                         pins = "gpio3";
 124                                         function = "pcie1_rst";
 125                                         drive-strength = <12>;
 126                                         bias-disable;
 127                                 };
 128                         };
 129
 130                         pcie1_pins: pcie1_pinmux {
 131                                 mux {
 132                                         pins = "gpio48";
 133                                         function = "pcie2_rst";
 134                                         drive-strength = <12>;
 135                                         bias-disable;
 136                                 };
 137                         };
 138
 139                         pcie2_pins: pcie2_pinmux {
 140                                 mux {
 141                                         pins = "gpio63";
 142                                         function = "pcie3_rst";
 143                                         drive-strength = <12>;
 144                                         bias-disable;
 145                                 };
 146                         };
 147
 148                         spi_pins: spi_pins {
 149                                 mux {
 150                                         pins = "gpio18", "gpio19", "gpio21";
 151                                         function = "gsbi5";
 152                                         drive-strength = <10>;
 153                                         bias-none;
 154                                 };
 155                         };
 156
 157                         leds_pins: leds_pins {
 158                                 mux {
 159                                         pins = "gpio7", "gpio8", "gpio9",
 160                                                "gpio26", "gpio53";
 161                                         function = "gpio";
 162                                         drive-strength = <2>;
 163                                         bias-pull-down;
 164                                         output-low;
 165                                 };
 166                         };
 167
 168                         buttons_pins: buttons_pins {
 169                                 mux {
 170                                         pins = "gpio54";
 171                                         drive-strength = <2>;
 172                                         bias-pull-up;
 173                                 };
 174                         };
 175                 };
 176
 177                 intc: interrupt-controller@2000000 {
 178                         compatible = "qcom,msm-qgic2";
 179                         interrupt-controller;
 180                         #interrupt-cells = <3>;
 181                         reg = <0x02000000 0x1000>,
 182                               <0x02002000 0x1000>;
 183                 };
 184
 185                 timer@200a000 {
 186                         compatible = "qcom,kpss-timer",
 187                                      "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
 188                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
 189                                                  IRQ_TYPE_EDGE_RISING)>,
 190                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
 191                                                  IRQ_TYPE_EDGE_RISING)>,
 192                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
 193                                                  IRQ_TYPE_EDGE_RISING)>,
 194                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
 195                                                  IRQ_TYPE_EDGE_RISING)>,
 196                                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
 197                                                  IRQ_TYPE_EDGE_RISING)>;
 198                         reg = <0x0200a000 0x100>;
 199                         clock-frequency = <25000000>,
 200                                           <32768>;
 201                         clocks = <&sleep_clk>;
 202                         clock-names = "sleep";
 203                         cpu-offset = <0x80000>;
 204                 };
 205
 206                 acc0: clock-controller@2088000 {
 207                         compatible = "qcom,kpss-acc-v1";
 208                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 209                 };
 210
 211                 acc1: clock-controller@2098000 {
 212                         compatible = "qcom,kpss-acc-v1";
 213                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 214                 };
 215
 216                 saw0: regulator@2089000 {
 217                         compatible = "qcom,saw2";
 218                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 219                         regulator;
 220                 };
 221
 222                 saw1: regulator@2099000 {
 223                         compatible = "qcom,saw2";
 224                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 225                         regulator;
 226                 };
 227
 228                 gsbi2: gsbi@12480000 {
 229                         compatible = "qcom,gsbi-v1.0.0";
 230                         cell-index = <2>;
 231                         reg = <0x12480000 0x100>;
 232                         clocks = <&gcc GSBI2_H_CLK>;
 233                         clock-names = "iface";
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         ranges;
 237                         status = "disabled";
 238
 239                         syscon-tcsr = <&tcsr>;
 240
 241                         serial@12490000 {
 242                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 243                                 reg = <0x12490000 0x1000>,
 244                                       <0x12480000 0x1000>;
 245                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 246                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 247                                 clock-names = "core", "iface";
 248                                 status = "disabled";
 249                         };
 250
 251                         i2c@124a0000 {
 252                                 compatible = "qcom,i2c-qup-v1.1.1";
 253                                 reg = <0x124a0000 0x1000>;
 254                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 255
 256                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 257                                 clock-names = "core", "iface";
 258                                 status = "disabled";
 259
 260                                 #address-cells = <1>;
 261                                 #size-cells = <0>;
 262                         };
 263
 264                 };
 265
 266                 gsbi4: gsbi@16300000 {
 267                         compatible = "qcom,gsbi-v1.0.0";
 268                         cell-index = <4>;
 269                         reg = <0x16300000 0x100>;
 270                         clocks = <&gcc GSBI4_H_CLK>;
 271                         clock-names = "iface";
 272                         #address-cells = <1>;
 273                         #size-cells = <1>;
 274                         ranges;
 275                         status = "disabled";
 276
 277                         syscon-tcsr = <&tcsr>;
 278
 279                         gsbi4_serial: serial@16340000 {
 280                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 281                                 reg = <0x16340000 0x1000>,
 282                                       <0x16300000 0x1000>;
 283                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 284                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 285                                 clock-names = "core", "iface";
 286                                 status = "disabled";
 287                         };
 288
 289                         i2c@16380000 {
 290                                 compatible = "qcom,i2c-qup-v1.1.1";
 291                                 reg = <0x16380000 0x1000>;
 292                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 293
 294                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 295                                 clock-names = "core", "iface";
 296                                 status = "disabled";
 297
 298                                 #address-cells = <1>;
 299                                 #size-cells = <0>;
 300                         };
 301                 };
 302
 303                 gsbi5: gsbi@1a200000 {
 304                         compatible = "qcom,gsbi-v1.0.0";
 305                         cell-index = <5>;
 306                         reg = <0x1a200000 0x100>;
 307                         clocks = <&gcc GSBI5_H_CLK>;
 308                         clock-names = "iface";
 309                         #address-cells = <1>;
 310                         #size-cells = <1>;
 311                         ranges;
 312                         status = "disabled";
 313
 314                         syscon-tcsr = <&tcsr>;
 315
 316                         serial@1a240000 {
 317                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 318                                 reg = <0x1a240000 0x1000>,
 319                                       <0x1a200000 0x1000>;
 320                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 321                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 322                                 clock-names = "core", "iface";
 323                                 status = "disabled";
 324                         };
 325
 326                         i2c@1a280000 {
 327                                 compatible = "qcom,i2c-qup-v1.1.1";
 328                                 reg = <0x1a280000 0x1000>;
 329                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 330
 331                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 332                                 clock-names = "core", "iface";
 333                                 status = "disabled";
 334
 335                                 #address-cells = <1>;
 336                                 #size-cells = <0>;
 337                         };
 338
 339                         spi@1a280000 {
 340                                 compatible = "qcom,spi-qup-v1.1.1";
 341                                 reg = <0x1a280000 0x1000>;
 342                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 343
 344                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 345                                 clock-names = "core", "iface";
 346                                 status = "disabled";
 347
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350                         };
 351                 };
 352
 353                 gsbi7: gsbi@16600000 {
 354                         status = "disabled";
 355                         compatible = "qcom,gsbi-v1.0.0";
 356                         cell-index = <7>;
 357                         reg = <0x16600000 0x100>;
 358                         clocks = <&gcc GSBI7_H_CLK>;
 359                         clock-names = "iface";
 360                         #address-cells = <1>;
 361                         #size-cells = <1>;
 362                         ranges;
 363                         syscon-tcsr = <&tcsr>;
 364
 365                         gsbi7_serial: serial@16640000 {
 366                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 367                                 reg = <0x16640000 0x1000>,
 368                                       <0x16600000 0x1000>;
 369                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 371                                 clock-names = "core", "iface";
 372                                 status = "disabled";
 373                         };
 374                 };
 375
 376                 sata_phy: sata-phy@1b400000 {
 377                         compatible = "qcom,ipq806x-sata-phy";
 378                         reg = <0x1b400000 0x200>;
 379
 380                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 381                         clock-names = "cfg";
 382
 383                         #phy-cells = <0>;
 384                         status = "disabled";
 385                 };
 386
 387                 sata@29000000 {
 388                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 389                         reg = <0x29000000 0x180>;
 390
 391                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 392
 393                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 394                                  <&gcc SATA_H_CLK>,
 395                                  <&gcc SATA_A_CLK>,
 396                                  <&gcc SATA_RXOOB_CLK>,
 397                                  <&gcc SATA_PMALIVE_CLK>;
 398                         clock-names = "slave_face", "iface", "core",
 399                                         "rxoob", "pmalive";
 400
 401                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 402                         assigned-clock-rates = <100000000>, <100000000>;
 403
 404                         phys = <&sata_phy>;
 405                         phy-names = "sata-phy";
 406                         status = "disabled";
 407                 };
 408
 409                 qcom,ssbi@500000 {
 410                         compatible = "qcom,ssbi";
 411                         reg = <0x00500000 0x1000>;
 412                         qcom,controller-type = "pmic-arbiter";
 413                 };
 414
 415                 gcc: clock-controller@900000 {
 416                         compatible = "qcom,gcc-ipq8064";
 417                         reg = <0x00900000 0x4000>;
 418                         #clock-cells = <1>;
 419                         #reset-cells = <1>;
 420                 };
 421
 422                 tcsr: syscon@1a400000 {
 423                         compatible = "qcom,tcsr-ipq8064", "syscon";
 424                         reg = <0x1a400000 0x100>;
 425                 };
 426
 427                 lcc: clock-controller@28000000 {
 428                         compatible = "qcom,lcc-ipq8064";
 429                         reg = <0x28000000 0x1000>;
 430                         #clock-cells = <1>;
 431                         #reset-cells = <1>;
 432                 };
 433
 434                 pcie0: pci@1b500000 {
 435                         compatible = "qcom,pcie-ipq8064";
 436                         reg = <0x1b500000 0x1000
 437                                0x1b502000 0x80
 438                                0x1b600000 0x100
 439                                0x0ff00000 0x100000>;
 440                         reg-names = "dbi", "elbi", "parf", "config";
 441                         device_type = "pci";
 442                         linux,pci-domain = <0>;
 443                         bus-range = <0x00 0xff>;
 444                         num-lanes = <1>;
 445                         #address-cells = <3>;
 446                         #size-cells = <2>;
 447
 448                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 449                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 450
 451                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 452                         interrupt-names = "msi";
 453                         #interrupt-cells = <1>;
 454                         interrupt-map-mask = <0 0 0 0x7>;
 455                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 456                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 457                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 458                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 459
 460                         clocks = <&gcc PCIE_A_CLK>,
 461                                  <&gcc PCIE_H_CLK>,
 462                                  <&gcc PCIE_PHY_CLK>,
 463                                  <&gcc PCIE_AUX_CLK>,
 464                                  <&gcc PCIE_ALT_REF_CLK>;
 465                         clock-names = "core", "iface", "phy", "aux", "ref";
 466
 467                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 468                         assigned-clock-rates = <100000000>;
 469
 470                         resets = <&gcc PCIE_ACLK_RESET>,
 471                                  <&gcc PCIE_HCLK_RESET>,
 472                                  <&gcc PCIE_POR_RESET>,
 473                                  <&gcc PCIE_PCI_RESET>,
 474                                  <&gcc PCIE_PHY_RESET>,
 475                                  <&gcc PCIE_EXT_RESET>;
 476                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 477
 478                         pinctrl-0 = <&pcie0_pins>;
 479                         pinctrl-names = "default";
 480
 481                         status = "disabled";
 482                         perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 483                 };
 484
 485                 pcie1: pci@1b700000 {
 486                         compatible = "qcom,pcie-ipq8064";
 487                         reg = <0x1b700000 0x1000
 488                                0x1b702000 0x80
 489                                0x1b800000 0x100
 490                                0x31f00000 0x100000>;
 491                         reg-names = "dbi", "elbi", "parf", "config";
 492                         device_type = "pci";
 493                         linux,pci-domain = <1>;
 494                         bus-range = <0x00 0xff>;
 495                         num-lanes = <1>;
 496                         #address-cells = <3>;
 497                         #size-cells = <2>;
 498
 499                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 500                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 501
 502                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 503                         interrupt-names = "msi";
 504                         #interrupt-cells = <1>;
 505                         interrupt-map-mask = <0 0 0 0x7>;
 506                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 507                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 508                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 509                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 510
 511                         clocks = <&gcc PCIE_1_A_CLK>,
 512                                  <&gcc PCIE_1_H_CLK>,
 513                                  <&gcc PCIE_1_PHY_CLK>,
 514                                  <&gcc PCIE_1_AUX_CLK>,
 515                                  <&gcc PCIE_1_ALT_REF_CLK>;
 516                         clock-names = "core", "iface", "phy", "aux", "ref";
 517
 518                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 519                         assigned-clock-rates = <100000000>;
 520
 521                         resets = <&gcc PCIE_1_ACLK_RESET>,
 522                                  <&gcc PCIE_1_HCLK_RESET>,
 523                                  <&gcc PCIE_1_POR_RESET>,
 524                                  <&gcc PCIE_1_PCI_RESET>,
 525                                  <&gcc PCIE_1_PHY_RESET>,
 526                                  <&gcc PCIE_1_EXT_RESET>;
 527                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 528
 529                         pinctrl-0 = <&pcie1_pins>;
 530                         pinctrl-names = "default";
 531
 532                         status = "disabled";
 533                         perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 534                 };
 535
 536                 pcie2: pci@1b900000 {
 537                         compatible = "qcom,pcie-ipq8064";
 538                         reg = <0x1b900000 0x1000
 539                                0x1b902000 0x80
 540                                0x1ba00000 0x100
 541                                0x35f00000 0x100000>;
 542                         reg-names = "dbi", "elbi", "parf", "config";
 543                         device_type = "pci";
 544                         linux,pci-domain = <2>;
 545                         bus-range = <0x00 0xff>;
 546                         num-lanes = <1>;
 547                         #address-cells = <3>;
 548                         #size-cells = <2>;
 549
 550                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 551                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 552
 553                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 554                         interrupt-names = "msi";
 555                         #interrupt-cells = <1>;
 556                         interrupt-map-mask = <0 0 0 0x7>;
 557                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 558                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 559                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 560                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 561
 562                         clocks = <&gcc PCIE_2_A_CLK>,
 563                                  <&gcc PCIE_2_H_CLK>,
 564                                  <&gcc PCIE_2_PHY_CLK>,
 565                                  <&gcc PCIE_2_AUX_CLK>,
 566                                  <&gcc PCIE_2_ALT_REF_CLK>;
 567                         clock-names = "core", "iface", "phy", "aux", "ref";
 568
 569                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 570                         assigned-clock-rates = <100000000>;
 571
 572                         resets = <&gcc PCIE_2_ACLK_RESET>,
 573                                  <&gcc PCIE_2_HCLK_RESET>,
 574                                  <&gcc PCIE_2_POR_RESET>,
 575                                  <&gcc PCIE_2_PCI_RESET>,
 576                                  <&gcc PCIE_2_PHY_RESET>,
 577                                  <&gcc PCIE_2_EXT_RESET>;
 578                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 579
 580                         pinctrl-0 = <&pcie2_pins>;
 581                         pinctrl-names = "default";
 582
 583                         status = "disabled";
 584                         perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 585                 };
 586
 587                 vsdcc_fixed: vsdcc-regulator {
 588                         compatible = "regulator-fixed";
 589                         regulator-name = "SDCC Power";
 590                         regulator-min-microvolt = <3300000>;
 591                         regulator-max-microvolt = <3300000>;
 592                         regulator-always-on;
 593                 };
 594
 595                 sdcc1bam:dma@12402000 {
 596                         compatible = "qcom,bam-v1.3.0";
 597                         reg = <0x12402000 0x8000>;
 598                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&gcc SDC1_H_CLK>;
 600                         clock-names = "bam_clk";
 601                         #dma-cells = <1>;
 602                         qcom,ee = <0>;
 603                 };
 604
 605                 sdcc3bam:dma@12182000 {
 606                         compatible = "qcom,bam-v1.3.0";
 607                         reg = <0x12182000 0x8000>;
 608                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&gcc SDC3_H_CLK>;
 610                         clock-names = "bam_clk";
 611                         #dma-cells = <1>;
 612                         qcom,ee = <0>;
 613                 };
 614
 615                 amba {
 616                         compatible = "simple-bus";
 617                         #address-cells = <1>;
 618                         #size-cells = <1>;
 619                         ranges;
 620
 621                         sdcc@12400000 {
 622                                 status          = "disabled";
 623                                 compatible      = "arm,pl18x", "arm,primecell";
 624                                 arm,primecell-periphid = <0x00051180>;
 625                                 reg             = <0x12400000 0x2000>;
 626                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 627                                 interrupt-names = "cmd_irq";
 628                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 629                                 clock-names     = "mclk", "apb_pclk";
 630                                 bus-width       = <8>;
 631                                 max-frequency   = <96000000>;
 632                                 non-removable;
 633                                 cap-sd-highspeed;
 634                                 cap-mmc-highspeed;
 635                                 mmc-ddr-1_8v;
 636                                 vmmc-supply = <&vsdcc_fixed>;
 637                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 638                                 dma-names = "tx", "rx";
 639                         };
 640
 641                         sdcc@12180000 {
 642                                 compatible      = "arm,pl18x", "arm,primecell";
 643                                 arm,primecell-periphid = <0x00051180>;
 644                                 status          = "disabled";
 645                                 reg             = <0x12180000 0x2000>;
 646                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 647                                 interrupt-names = "cmd_irq";
 648                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 649                                 clock-names     = "mclk", "apb_pclk";
 650                                 bus-width       = <8>;
 651                                 cap-sd-highspeed;
 652                                 cap-mmc-highspeed;
 653                                 max-frequency   = <192000000>;
 654                                 #mmc-ddr-1_8v;
 655                                 sd-uhs-sdr104;
 656                                 sd-uhs-ddr50;
 657                                 vqmmc-supply = <&vsdcc_fixed>;
 658                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 659                                 dma-names = "tx", "rx";
 660                         };
 661                 };
 662         };
 663 };