arch/arm/boot/dts/qcom-ipq4019.dtsi

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "skeleton.dtsi"
  17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. IPQ4019";
  23         compatible = "qcom,ipq4019";
  24         interrupt-parent = <&intc>;
  25
  26         reserved-memory {
  27                 #address-cells = <0x1>;
  28                 #size-cells = <0x1>;
  29                 ranges;
  30
  31                 smem_region: smem@87e00000 {
  32                         reg = <0x87e00000 0x080000>;
  33                         no-map;
  34                 };
  35
  36                 tz@87e80000 {
  37                         reg = <0x87e80000 0x180000>;
  38                         no-map;
  39                 };
  40         };
  41
  42         aliases {
  43                 spi0 = &blsp1_spi1;
  44                 spi1 = &blsp1_spi2;
  45                 i2c0 = &blsp1_i2c3;
  46                 i2c1 = &blsp1_i2c4;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a7";
  55                         enable-method = "qcom,kpss-acc-v1";
  56                         qcom,acc = <&acc0>;
  57                         qcom,saw = <&saw0>;
  58                         reg = <0x0>;
  59                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  60                         clock-frequency = <0>;
  61                         operating-points = <
  62                                 /* kHz  uV (fixed) */
  63                                 48000   1100000
  64                                 200000  1100000
  65                                 500000  1100000
  66                                 716000  1100000
  67                         >;
  68                         clock-latency = <256000>;
  69                 };
  70
  71                 cpu@1 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a7";
  74                         enable-method = "qcom,kpss-acc-v1";
  75                         qcom,acc = <&acc1>;
  76                         qcom,saw = <&saw1>;
  77                         reg = <0x1>;
  78                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  79                         clock-frequency = <0>;
  80                 };
  81
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         enable-method = "qcom,kpss-acc-v1";
  86                         qcom,acc = <&acc2>;
  87                         qcom,saw = <&saw2>;
  88                         reg = <0x2>;
  89                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  90                         clock-frequency = <0>;
  91                 };
  92
  93                 cpu@3 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         enable-method = "qcom,kpss-acc-v1";
  97                         qcom,acc = <&acc3>;
  98                         qcom,saw = <&saw3>;
  99                         reg = <0x3>;
 100                         clocks = <&gcc GCC_APPS_CLK_SRC>;
 101                         clock-frequency = <0>;
 102                 };
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a7-pmu";
 107                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 108                                          IRQ_TYPE_LEVEL_HIGH)>;
 109         };
 110
 111         clocks {
 112                 sleep_clk: sleep_clk {
 113                         compatible = "fixed-clock";
 114                         clock-frequency = <32768>;
 115                         #clock-cells = <0>;
 116                 };
 117
 118                 xo: xo {
 119                         compatible = "fixed-clock";
 120                         clock-frequency = <48000000>;
 121                         #clock-cells = <0>;
 122                 };
 123         };
 124
 125         firmware {
 126                 scm {
 127                         compatible = "qcom,scm-ipq4019";
 128                 };
 129         };
 130
 131         timer {
 132                 compatible = "arm,armv7-timer";
 133                 interrupts = <1 2 0xf08>,
 134                              <1 3 0xf08>,
 135                              <1 4 0xf08>,
 136                              <1 1 0xf08>;
 137                 clock-frequency = <48000000>;
 138         };
 139
 140         soc {
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 ranges;
 144                 compatible = "simple-bus";
 145
 146                 intc: interrupt-controller@b000000 {
 147                         compatible = "qcom,msm-qgic2";
 148                         interrupt-controller;
 149                         #interrupt-cells = <3>;
 150                         reg = <0x0b000000 0x1000>,
 151                         <0x0b002000 0x1000>;
 152                 };
 153
 154                 gcc: clock-controller@1800000 {
 155                         compatible = "qcom,gcc-ipq4019";
 156                         #clock-cells = <1>;
 157                         #reset-cells = <1>;
 158                         reg = <0x1800000 0x60000>;
 159                 };
 160
 161                 rng@22000 {
 162                         compatible = "qcom,prng";
 163                         reg = <0x22000 0x140>;
 164                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 165                         clock-names = "core";
 166                         status = "disabled";
 167                 };
 168
 169                 tlmm: pinctrl@1000000 {
 170                         compatible = "qcom,ipq4019-pinctrl";
 171                         reg = <0x01000000 0x300000>;
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                         interrupt-controller;
 175                         #interrupt-cells = <2>;
 176                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 177                 };
 178
 179                 blsp_dma: dma@7884000 {
 180                         compatible = "qcom,bam-v1.7.0";
 181                         reg = <0x07884000 0x23000>;
 182                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 184                         clock-names = "bam_clk";
 185                         #dma-cells = <1>;
 186                         qcom,ee = <0>;
 187                         status = "disabled";
 188                 };
 189
 190                 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
 191                         compatible = "qcom,spi-qup-v2.2.1";
 192                         reg = <0x78b5000 0x600>;
 193                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 195                                  <&gcc GCC_BLSP1_AHB_CLK>;
 196                         clock-names = "core", "iface";
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 200                         dma-names = "rx", "tx";
 201                         status = "disabled";
 202                 };
 203
 204                 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
 205                         compatible = "qcom,spi-qup-v2.2.1";
 206                         reg = <0x78b6000 0x600>;
 207                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 208                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 209                                 <&gcc GCC_BLSP1_AHB_CLK>;
 210                         clock-names = "core", "iface";
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 214                         dma-names = "rx", "tx";
 215                         status = "disabled";
 216                 };
 217
 218                 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
 219                         compatible = "qcom,i2c-qup-v2.2.1";
 220                         reg = <0x78b7000 0x600>;
 221                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 223                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 224                         clock-names = "iface", "core";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 228                         dma-names = "rx", "tx";
 229                         status = "disabled";
 230                 };
 231
 232                 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
 233                         compatible = "qcom,i2c-qup-v2.2.1";
 234                         reg = <0x78b8000 0x600>;
 235                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 237                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 238                         clock-names = "iface", "core";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 242                         dma-names = "rx", "tx";
 243                         status = "disabled";
 244                 };
 245
 246                 cryptobam: dma@8e04000 {
 247                         compatible = "qcom,bam-v1.7.0";
 248                         reg = <0x08e04000 0x20000>;
 249                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 251                         clock-names = "bam_clk";
 252                         #dma-cells = <1>;
 253                         qcom,ee = <1>;
 254                         qcom,controlled-remotely;
 255                         status = "disabled";
 256                 };
 257
 258                 crypto@8e3a000 {
 259                         compatible = "qcom,crypto-v5.1";
 260                         reg = <0x08e3a000 0x6000>;
 261                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 262                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 263                                  <&gcc GCC_CRYPTO_CLK>;
 264                         clock-names = "iface", "bus", "core";
 265                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 266                         dma-names = "rx", "tx";
 267                         status = "disabled";
 268                 };
 269
 270                 acc0: clock-controller@b088000 {
 271                         compatible = "qcom,kpss-acc-v1";
 272                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 273                 };
 274
 275                 acc1: clock-controller@b098000 {
 276                         compatible = "qcom,kpss-acc-v1";
 277                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 278                 };
 279
 280                 acc2: clock-controller@b0a8000 {
 281                         compatible = "qcom,kpss-acc-v1";
 282                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 283                 };
 284
 285                 acc3: clock-controller@b0b8000 {
 286                         compatible = "qcom,kpss-acc-v1";
 287                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 288                 };
 289
 290                 saw0: regulator@b089000 {
 291                         compatible = "qcom,saw2";
 292                         reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
 293                         regulator;
 294                 };
 295
 296                 saw1: regulator@b099000 {
 297                         compatible = "qcom,saw2";
 298                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 299                         regulator;
 300                 };
 301
 302                 saw2: regulator@b0a9000 {
 303                         compatible = "qcom,saw2";
 304                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 305                         regulator;
 306                 };
 307
 308                 saw3: regulator@b0b9000 {
 309                         compatible = "qcom,saw2";
 310                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 311                         regulator;
 312                 };
 313
 314                 blsp1_uart1: serial@78af000 {
 315                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 316                         reg = <0x78af000 0x200>;
 317                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 318                         status = "disabled";
 319                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 320                                 <&gcc GCC_BLSP1_AHB_CLK>;
 321                         clock-names = "core", "iface";
 322                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 323                         dma-names = "rx", "tx";
 324                 };
 325
 326                 blsp1_uart2: serial@78b0000 {
 327                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 328                         reg = <0x78b0000 0x200>;
 329                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 330                         status = "disabled";
 331                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 332                                 <&gcc GCC_BLSP1_AHB_CLK>;
 333                         clock-names = "core", "iface";
 334                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 335                         dma-names = "rx", "tx";
 336                 };
 337
 338                 watchdog@b017000 {
 339                         compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
 340                         reg = <0xb017000 0x40>;
 341                         clocks = <&sleep_clk>;
 342                         timeout-sec = <10>;
 343                         status = "disabled";
 344                 };
 345
 346                 restart@4ab000 {
 347                         compatible = "qcom,pshold";
 348                         reg = <0x4ab000 0x4>;
 349                 };
 350
 351                 pcie0: pci@40000000 {
 352                         compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
 353                         reg =  <0x40000000 0xf1d
 354                                 0x40000f20 0xa8
 355                                 0x80000 0x2000
 356                                 0x40100000 0x1000>;
 357                         reg-names = "dbi", "elbi", "parf", "config";
 358                         device_type = "pci";
 359                         linux,pci-domain = <0>;
 360                         bus-range = <0x00 0xff>;
 361                         num-lanes = <1>;
 362                         #address-cells = <3>;
 363                         #size-cells = <2>;
 364
 365                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
 366                                   0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
 367
 368                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
 369                         interrupt-names = "msi";
 370                         #interrupt-cells = <1>;
 371                         interrupt-map-mask = <0 0 0 0x7>;
 372                         interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 373                                         <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 374                                         <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 375                                         <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 376                         clocks = <&gcc GCC_PCIE_AHB_CLK>,
 377                                  <&gcc GCC_PCIE_AXI_M_CLK>,
 378                                  <&gcc GCC_PCIE_AXI_S_CLK>;
 379                         clock-names = "aux",
 380                                       "master_bus",
 381                                       "slave_bus";
 382
 383                         resets = <&gcc PCIE_AXI_M_ARES>,
 384                                  <&gcc PCIE_AXI_S_ARES>,
 385                                  <&gcc PCIE_PIPE_ARES>,
 386                                  <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 387                                  <&gcc PCIE_AXI_S_XPU_ARES>,
 388                                  <&gcc PCIE_PARF_XPU_ARES>,
 389                                  <&gcc PCIE_PHY_ARES>,
 390                                  <&gcc PCIE_AXI_M_STICKY_ARES>,
 391                                  <&gcc PCIE_PIPE_STICKY_ARES>,
 392                                  <&gcc PCIE_PWR_ARES>,
 393                                  <&gcc PCIE_AHB_ARES>,
 394                                  <&gcc PCIE_PHY_AHB_ARES>;
 395                         reset-names = "axi_m",
 396                                       "axi_s",
 397                                       "pipe",
 398                                       "axi_m_vmid",
 399                                       "axi_s_xpu",
 400                                       "parf",
 401                                       "phy",
 402                                       "axi_m_sticky",
 403                                       "pipe_sticky",
 404                                       "pwr",
 405                                       "ahb",
 406                                       "phy_ahb";
 407
 408                         status = "disabled";
 409                 };
 410
 411                 qpic_bam: dma@7984000 {
 412                         compatible = "qcom,bam-v1.7.0";
 413                         reg = <0x7984000 0x1a000>;
 414                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 415                         clocks = <&gcc GCC_QPIC_CLK>;
 416                         clock-names = "bam_clk";
 417                         #dma-cells = <1>;
 418                         qcom,ee = <0>;
 419                         status = "disabled";
 420                 };
 421
 422                 nand: qpic-nand@79b0000 {
 423                         compatible = "qcom,ipq4019-nand";
 424                         reg = <0x79b0000 0x1000>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         clocks = <&gcc GCC_QPIC_CLK>,
 428                                  <&gcc GCC_QPIC_AHB_CLK>;
 429                         clock-names = "core", "aon";
 430
 431                         dmas = <&qpic_bam 0>,
 432                                <&qpic_bam 1>,
 433                                <&qpic_bam 2>;
 434                         dma-names = "tx", "rx", "cmd";
 435                         status = "disabled";
 436
 437                         nand@0 {
 438                                 reg = <0>;
 439
 440                                 nand-ecc-strength = <4>;
 441                                 nand-ecc-step-size = <512>;
 442                                 nand-bus-width = <8>;
 443                         };
 444                 };
 445
 446                 wifi0: wifi@a000000 {
 447                         compatible = "qcom,ipq4019-wifi";
 448                         reg = <0xa000000 0x200000>;
 449                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 450                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 451                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 452                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 453                                  <&gcc WIFI0_CORE_WARM_RESET>,
 454                                  <&gcc WIFI0_CORE_COLD_RESET>;
 455                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 456                                       "wifi_radio_warm", "wifi_radio_cold",
 457                                       "wifi_core_warm", "wifi_core_cold";
 458                         clocks = <&gcc GCC_WCSS2G_CLK>,
 459                                  <&gcc GCC_WCSS2G_REF_CLK>,
 460                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 461                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 462                                       "wifi_wcss_rtc";
 463                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 464                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 465                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 466                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 467                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 468                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 469                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 470                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 471                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 472                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 473                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 474                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 475                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 476                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 477                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 478                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 479                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 480                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 481                                            "msi4",  "msi5",  "msi6",  "msi7",
 482                                            "msi8",  "msi9", "msi10", "msi11",
 483                                           "msi12", "msi13", "msi14", "msi15",
 484                                           "legacy";
 485                         status = "disabled";
 486                 };
 487
 488                 wifi1: wifi@a800000 {
 489                         compatible = "qcom,ipq4019-wifi";
 490                         reg = <0xa800000 0x200000>;
 491                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 492                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 493                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 494                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 495                                  <&gcc WIFI1_CORE_WARM_RESET>,
 496                                  <&gcc WIFI1_CORE_COLD_RESET>;
 497                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 498                                       "wifi_radio_warm", "wifi_radio_cold",
 499                                       "wifi_core_warm", "wifi_core_cold";
 500                         clocks = <&gcc GCC_WCSS5G_CLK>,
 501                                  <&gcc GCC_WCSS5G_REF_CLK>,
 502                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 503                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 504                                       "wifi_wcss_rtc";
 505                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 506                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 507                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 508                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 509                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 510                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 511                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 512                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 513                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 514                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 515                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 516                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 517                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 518                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 519                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 520                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 521                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 522                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 523                                            "msi4",  "msi5",  "msi6",  "msi7",
 524                                            "msi8",  "msi9", "msi10", "msi11",
 525                                           "msi12", "msi13", "msi14", "msi15",
 526                                           "legacy";
 527                         status = "disabled";
 528                 };
 529         };
 530 };