arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   6 #include <dt-bindings/soc/qcom,gsbi.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,krait";
  20                         enable-method = "qcom,kpss-acc-v1";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         qcom,acc = <&acc0>;
  25                         qcom,saw = <&saw0>;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "qcom,krait";
  30                         enable-method = "qcom,kpss-acc-v1";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc1>;
  35                         qcom,saw = <&saw1>;
  36                 };
  37
  38                 cpu@2 {
  39                         compatible = "qcom,krait";
  40                         enable-method = "qcom,kpss-acc-v1";
  41                         device_type = "cpu";
  42                         reg = <2>;
  43                         next-level-cache = <&L2>;
  44                         qcom,acc = <&acc2>;
  45                         qcom,saw = <&saw2>;
  46                 };
  47
  48                 cpu@3 {
  49                         compatible = "qcom,krait";
  50                         enable-method = "qcom,kpss-acc-v1";
  51                         device_type = "cpu";
  52                         reg = <3>;
  53                         next-level-cache = <&L2>;
  54                         qcom,acc = <&acc3>;
  55                         qcom,saw = <&saw3>;
  56                 };
  57
  58                 L2: l2-cache {
  59                         compatible = "cache";
  60                         cache-level = <2>;
  61                 };
  62         };
  63
  64         cpu-pmu {
  65                 compatible = "qcom,krait-pmu";
  66                 interrupts = <1 10 0x304>;
  67         };
  68
  69         soc: soc {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 ranges;
  73                 compatible = "simple-bus";
  74
  75                 tlmm_pinmux: pinctrl@800000 {
  76                         compatible = "qcom,apq8064-pinctrl";
  77                         reg = <0x800000 0x4000>;
  78
  79                         gpio-controller;
  80                         #gpio-cells = <2>;
  81                         interrupt-controller;
  82                         #interrupt-cells = <2>;
  83                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  84
  85                         pinctrl-names = "default";
  86                         pinctrl-0 = <&ps_hold>;
  87
  88                         sdc4_gpios: sdc4-gpios {
  89                                 pios {
  90                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
  91                                         function = "sdc4";
  92                                 };
  93                         };
  94
  95                         ps_hold: ps_hold {
  96                                 mux {
  97                                         pins = "gpio78";
  98                                         function = "ps_hold";
  99                                 };
 100                         };
 101                 };
 102
 103                 intc: interrupt-controller@2000000 {
 104                         compatible = "qcom,msm-qgic2";
 105                         interrupt-controller;
 106                         #interrupt-cells = <3>;
 107                         reg = <0x02000000 0x1000>,
 108                               <0x02002000 0x1000>;
 109                 };
 110
 111                 timer@200a000 {
 112                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 113                         interrupts = <1 1 0x301>,
 114                                      <1 2 0x301>,
 115                                      <1 3 0x301>;
 116                         reg = <0x0200a000 0x100>;
 117                         clock-frequency = <27000000>,
 118                                           <32768>;
 119                         cpu-offset = <0x80000>;
 120                 };
 121
 122                 acc0: clock-controller@2088000 {
 123                         compatible = "qcom,kpss-acc-v1";
 124                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 125                 };
 126
 127                 acc1: clock-controller@2098000 {
 128                         compatible = "qcom,kpss-acc-v1";
 129                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 130                 };
 131
 132                 acc2: clock-controller@20a8000 {
 133                         compatible = "qcom,kpss-acc-v1";
 134                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 135                 };
 136
 137                 acc3: clock-controller@20b8000 {
 138                         compatible = "qcom,kpss-acc-v1";
 139                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 140                 };
 141
 142                 saw0: regulator@2089000 {
 143                         compatible = "qcom,saw2";
 144                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 145                         regulator;
 146                 };
 147
 148                 saw1: regulator@2099000 {
 149                         compatible = "qcom,saw2";
 150                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 151                         regulator;
 152                 };
 153
 154                 saw2: regulator@20a9000 {
 155                         compatible = "qcom,saw2";
 156                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 157                         regulator;
 158                 };
 159
 160                 saw3: regulator@20b9000 {
 161                         compatible = "qcom,saw2";
 162                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 163                         regulator;
 164                 };
 165
 166                 gsbi1: gsbi@12440000 {
 167                         status = "disabled";
 168                         compatible = "qcom,gsbi-v1.0.0";
 169                         reg = <0x12440000 0x100>;
 170                         clocks = <&gcc GSBI1_H_CLK>;
 171                         clock-names = "iface";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         ranges;
 175
 176                         i2c1: i2c@12460000 {
 177                                 compatible = "qcom,i2c-qup-v1.1.1";
 178                                 reg = <0x12460000 0x1000>;
 179                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 180                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 181                                 clock-names = "core", "iface";
 182                                 #address-cells = <1>;
 183                                 #size-cells = <0>;
 184                         };
 185                 };
 186
 187                 gsbi2: gsbi@12480000 {
 188                         status = "disabled";
 189                         compatible = "qcom,gsbi-v1.0.0";
 190                         reg = <0x12480000 0x100>;
 191                         clocks = <&gcc GSBI2_H_CLK>;
 192                         clock-names = "iface";
 193                         #address-cells = <1>;
 194                         #size-cells = <1>;
 195                         ranges;
 196
 197                         i2c2: i2c@124a0000 {
 198                                 compatible = "qcom,i2c-qup-v1.1.1";
 199                                 reg = <0x124a0000 0x1000>;
 200                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 201                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 202                                 clock-names = "core", "iface";
 203                                 #address-cells = <1>;
 204                                 #size-cells = <0>;
 205                         };
 206                 };
 207
 208                 gsbi7: gsbi@16600000 {
 209                         status = "disabled";
 210                         compatible = "qcom,gsbi-v1.0.0";
 211                         reg = <0x16600000 0x100>;
 212                         clocks = <&gcc GSBI7_H_CLK>;
 213                         clock-names = "iface";
 214                         #address-cells = <1>;
 215                         #size-cells = <1>;
 216                         ranges;
 217
 218                         serial@16640000 {
 219                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 220                                 reg = <0x16640000 0x1000>,
 221                                       <0x16600000 0x1000>;
 222                                 interrupts = <0 158 0x0>;
 223                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 224                                 clock-names = "core", "iface";
 225                                 status = "disabled";
 226                         };
 227                 };
 228
 229                 qcom,ssbi@500000 {
 230                         compatible = "qcom,ssbi";
 231                         reg = <0x00500000 0x1000>;
 232                         qcom,controller-type = "pmic-arbiter";
 233                 };
 234
 235                 gcc: clock-controller@900000 {
 236                         compatible = "qcom,gcc-apq8064";
 237                         reg = <0x00900000 0x4000>;
 238                         #clock-cells = <1>;
 239                         #reset-cells = <1>;
 240                 };
 241
 242                 mmcc: clock-controller@4000000 {
 243                         compatible = "qcom,mmcc-apq8064";
 244                         reg = <0x4000000 0x1000>;
 245                         #clock-cells = <1>;
 246                         #reset-cells = <1>;
 247                 };
 248
 249                 /* Temporary fixed regulator */
 250                 vsdcc_fixed: vsdcc-regulator {
 251                         compatible = "regulator-fixed";
 252                         regulator-name = "SDCC Power";
 253                         regulator-min-microvolt = <2700000>;
 254                         regulator-max-microvolt = <2700000>;
 255                         regulator-always-on;
 256                 };
 257
 258                 sdcc1bam:dma@12402000{
 259                         compatible = "qcom,bam-v1.3.0";
 260                         reg = <0x12402000 0x8000>;
 261                         interrupts = <0 98 0>;
 262                         clocks = <&gcc SDC1_H_CLK>;
 263                         clock-names = "bam_clk";
 264                         #dma-cells = <1>;
 265                         qcom,ee = <0>;
 266                 };
 267
 268                 sdcc3bam:dma@12182000{
 269                         compatible = "qcom,bam-v1.3.0";
 270                         reg = <0x12182000 0x8000>;
 271                         interrupts = <0 96 0>;
 272                         clocks = <&gcc SDC3_H_CLK>;
 273                         clock-names = "bam_clk";
 274                         #dma-cells = <1>;
 275                         qcom,ee = <0>;
 276                 };
 277
 278                 sdcc4bam:dma@121c2000{
 279                         compatible = "qcom,bam-v1.3.0";
 280                         reg = <0x121c2000 0x8000>;
 281                         interrupts = <0 95 0>;
 282                         clocks = <&gcc SDC4_H_CLK>;
 283                         clock-names = "bam_clk";
 284                         #dma-cells = <1>;
 285                         qcom,ee = <0>;
 286                 };
 287
 288                 amba {
 289                         compatible = "arm,amba-bus";
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                         ranges;
 293                         sdcc1: sdcc@12400000 {
 294                                 status          = "disabled";
 295                                 compatible      = "arm,pl18x", "arm,primecell";
 296                                 arm,primecell-periphid = <0x00051180>;
 297                                 reg             = <0x12400000 0x2000>;
 298                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 299                                 interrupt-names = "cmd_irq";
 300                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 301                                 clock-names     = "mclk", "apb_pclk";
 302                                 bus-width       = <8>;
 303                                 max-frequency   = <96000000>;
 304                                 non-removable;
 305                                 cap-sd-highspeed;
 306                                 cap-mmc-highspeed;
 307                                 vmmc-supply = <&vsdcc_fixed>;
 308                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 309                                 dma-names = "tx", "rx";
 310                         };
 311
 312                         sdcc3: sdcc@12180000 {
 313                                 compatible      = "arm,pl18x", "arm,primecell";
 314                                 arm,primecell-periphid = <0x00051180>;
 315                                 status          = "disabled";
 316                                 reg             = <0x12180000 0x2000>;
 317                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 318                                 interrupt-names = "cmd_irq";
 319                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 320                                 clock-names     = "mclk", "apb_pclk";
 321                                 bus-width       = <4>;
 322                                 cap-sd-highspeed;
 323                                 cap-mmc-highspeed;
 324                                 max-frequency   = <192000000>;
 325                                 no-1-8-v;
 326                                 vmmc-supply = <&vsdcc_fixed>;
 327                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 328                                 dma-names = "tx", "rx";
 329                         };
 330
 331                         sdcc4: sdcc@121c0000 {
 332                                 compatible      = "arm,pl18x", "arm,primecell";
 333                                 arm,primecell-periphid = <0x00051180>;
 334                                 status          = "disabled";
 335                                 reg             = <0x121c0000 0x2000>;
 336                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 337                                 interrupt-names = "cmd_irq";
 338                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 339                                 clock-names     = "mclk", "apb_pclk";
 340                                 bus-width       = <4>;
 341                                 cap-sd-highspeed;
 342                                 cap-mmc-highspeed;
 343                                 max-frequency   = <48000000>;
 344                                 vmmc-supply = <&vsdcc_fixed>;
 345                                 vqmmc-supply = <&vsdcc_fixed>;
 346                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 347                                 dma-names = "tx", "rx";
 348                                 pinctrl-names = "default";
 349                                 pinctrl-0 = <&sdc4_gpios>;
 350                         };
 351                 };
 352         };
 353 };