arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 / {
  10         compatible = "sirf,prima2";
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0x0>;
  23                         d-cache-line-size = <32>;
  24                         i-cache-line-size = <32>;
  25                         d-cache-size = <32768>;
  26                         i-cache-size = <32768>;
  27                         /* from bootloader */
  28                         timebase-frequency = <0>;
  29                         bus-frequency = <0>;
  30                         clock-frequency = <0>;
  31                         clocks = <&clks 12>;
  32                         operating-points = <
  33                                 /* kHz    uV */
  34                                 200000  1025000
  35                                 400000  1025000
  36                                 664000  1050000
  37                                 800000  1100000
  38                         >;
  39                         clock-latency = <150000>;
  40                 };
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a9-pmu";
  45                 interrupts = <29>;
  46         };
  47
  48         axi {
  49                 compatible = "simple-bus";
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges = <0x40000000 0x40000000 0x80000000>;
  53
  54                 l2-cache-controller@80040000 {
  55                         compatible = "arm,pl310-cache";
  56                         reg = <0x80040000 0x1000>;
  57                         interrupts = <59>;
  58                         arm,tag-latency = <1 1 1>;
  59                         arm,data-latency = <1 1 1>;
  60                         arm,filter-ranges = <0 0x40000000>;
  61                 };
  62
  63                 intc: interrupt-controller@80020000 {
  64                         #interrupt-cells = <1>;
  65                         interrupt-controller;
  66                         compatible = "sirf,prima2-intc";
  67                         reg = <0x80020000 0x1000>;
  68                 };
  69
  70                 sys-iobg {
  71                         compatible = "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0x88000000 0x88000000 0x40000>;
  75
  76                         clks: clock-controller@88000000 {
  77                                 compatible = "sirf,prima2-clkc";
  78                                 reg = <0x88000000 0x1000>;
  79                                 interrupts = <3>;
  80                                 #clock-cells = <1>;
  81                         };
  82
  83                         rstc: reset-controller@88010000 {
  84                                 compatible = "sirf,prima2-rstc";
  85                                 reg = <0x88010000 0x1000>;
  86                                 #reset-cells = <1>;
  87                         };
  88
  89                         rsc-controller@88020000 {
  90                                 compatible = "sirf,prima2-rsc";
  91                                 reg = <0x88020000 0x1000>;
  92                         };
  93
  94                         cphifbg@88030000 {
  95                                 compatible = "sirf,prima2-cphifbg";
  96                                 reg = <0x88030000 0x1000>;
  97                                 clocks = <&clks 42>;
  98                         };
  99                 };
 100
 101                 mem-iobg {
 102                         compatible = "simple-bus";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         ranges = <0x90000000 0x90000000 0x10000>;
 106
 107                         memory-controller@90000000 {
 108                                 compatible = "sirf,prima2-memc";
 109                                 reg = <0x90000000 0x2000>;
 110                                 interrupts = <27>;
 111                                 clocks = <&clks 5>;
 112                         };
 113
 114                         memc-monitor {
 115                                 compatible = "sirf,prima2-memcmon";
 116                                 reg = <0x90002000 0x200>;
 117                                 interrupts = <4>;
 118                                 clocks = <&clks 32>;
 119                         };
 120                 };
 121
 122                 disp-iobg {
 123                         compatible = "simple-bus";
 124                         #address-cells = <1>;
 125                         #size-cells = <1>;
 126                         ranges = <0x90010000 0x90010000 0x30000>;
 127
 128                         display@90010000 {
 129                                 compatible = "sirf,prima2-lcd";
 130                                 reg = <0x90010000 0x20000>;
 131                                 interrupts = <30>;
 132                         };
 133
 134                         vpp@90020000 {
 135                                 compatible = "sirf,prima2-vpp";
 136                                 reg = <0x90020000 0x10000>;
 137                                 interrupts = <31>;
 138                                 clocks = <&clks 35>;
 139                                 resets = <&rstc 6>;
 140                         };
 141                 };
 142
 143                 graphics-iobg {
 144                         compatible = "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         ranges = <0x98000000 0x98000000 0x8000000>;
 148
 149                         graphics@98000000 {
 150                                 compatible = "powervr,sgx531";
 151                                 reg = <0x98000000 0x8000000>;
 152                                 interrupts = <6>;
 153                                 clocks = <&clks 32>;
 154                         };
 155                 };
 156
 157                 multimedia-iobg {
 158                         compatible = "simple-bus";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 162
 163                         multimedia@a0000000 {
 164                                 compatible = "sirf,prima2-video-codec";
 165                                 reg = <0xa0000000 0x8000000>;
 166                                 interrupts = <5>;
 167                                 clocks = <&clks 33>;
 168                         };
 169                 };
 170
 171                 dsp-iobg {
 172                         compatible = "simple-bus";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 176
 177                         dspif@a8000000 {
 178                                 compatible = "sirf,prima2-dspif";
 179                                 reg = <0xa8000000 0x10000>;
 180                                 interrupts = <9>;
 181                                 resets = <&rstc 1>;
 182                         };
 183
 184                         gps@a8010000 {
 185                                 compatible = "sirf,prima2-gps";
 186                                 reg = <0xa8010000 0x10000>;
 187                                 interrupts = <7>;
 188                                 clocks = <&clks 9>;
 189                                 resets = <&rstc 2>;
 190                         };
 191
 192                         dsp@a9000000 {
 193                                 compatible = "sirf,prima2-dsp";
 194                                 reg = <0xa9000000 0x1000000>;
 195                                 interrupts = <8>;
 196                                 clocks = <&clks 8>;
 197                                 resets = <&rstc 0>;
 198                         };
 199                 };
 200
 201                 peri-iobg {
 202                         compatible = "simple-bus";
 203                         #address-cells = <1>;
 204                         #size-cells = <1>;
 205                         ranges = <0xb0000000 0xb0000000 0x180000>,
 206                                <0x56000000 0x56000000 0x1b00000>;
 207
 208                         timer@b0020000 {
 209                                 compatible = "sirf,prima2-tick";
 210                                 reg = <0xb0020000 0x1000>;
 211                                 interrupts = <0>;
 212                                 clocks = <&clks 11>;
 213                         };
 214
 215                         nand@b0030000 {
 216                                 compatible = "sirf,prima2-nand";
 217                                 reg = <0xb0030000 0x10000>;
 218                                 interrupts = <41>;
 219                                 clocks = <&clks 26>;
 220                         };
 221
 222                         audio@b0040000 {
 223                                 compatible = "sirf,prima2-audio";
 224                                 reg = <0xb0040000 0x10000>;
 225                                 interrupts = <35>;
 226                                 clocks = <&clks 27>;
 227                         };
 228
 229                         uart0: uart@b0050000 {
 230                                 cell-index = <0>;
 231                                 compatible = "sirf,prima2-uart";
 232                                 reg = <0xb0050000 0x1000>;
 233                                 interrupts = <17>;
 234                                 fifosize = <128>;
 235                                 clocks = <&clks 13>;
 236                                 dmas = <&dmac1 5>, <&dmac0 2>;
 237                                 dma-names = "rx", "tx";
 238                         };
 239
 240                         uart1: uart@b0060000 {
 241                                 cell-index = <1>;
 242                                 compatible = "sirf,prima2-uart";
 243                                 reg = <0xb0060000 0x1000>;
 244                                 interrupts = <18>;
 245                                 fifosize = <32>;
 246                                 clocks = <&clks 14>;
 247                         };
 248
 249                         uart2: uart@b0070000 {
 250                                 cell-index = <2>;
 251                                 compatible = "sirf,prima2-uart";
 252                                 reg = <0xb0070000 0x1000>;
 253                                 interrupts = <19>;
 254                                 fifosize = <128>;
 255                                 clocks = <&clks 15>;
 256                                 dmas = <&dmac0 6>, <&dmac0 7>;
 257                                 dma-names = "rx", "tx";
 258                         };
 259
 260                         usp0: usp@b0080000 {
 261                                 cell-index = <0>;
 262                                 compatible = "sirf,prima2-usp";
 263                                 reg = <0xb0080000 0x10000>;
 264                                 interrupts = <20>;
 265                                 fifosize = <128>;
 266                                 clocks = <&clks 28>;
 267                                 dmas = <&dmac1 1>, <&dmac1 2>;
 268                                 dma-names = "rx", "tx";
 269                         };
 270
 271                         usp1: usp@b0090000 {
 272                                 cell-index = <1>;
 273                                 compatible = "sirf,prima2-usp";
 274                                 reg = <0xb0090000 0x10000>;
 275                                 interrupts = <21>;
 276                                 fifosize = <128>;
 277                                 clocks = <&clks 29>;
 278                                 dmas = <&dmac0 14>, <&dmac0 15>;
 279                                 dma-names = "rx", "tx";
 280                         };
 281
 282                         usp2: usp@b00a0000 {
 283                                 cell-index = <2>;
 284                                 compatible = "sirf,prima2-usp";
 285                                 reg = <0xb00a0000 0x10000>;
 286                                 interrupts = <22>;
 287                                 fifosize = <128>;
 288                                 clocks = <&clks 30>;
 289                                 dmas = <&dmac0 10>, <&dmac0 11>;
 290                                 dma-names = "rx", "tx";
 291                         };
 292
 293                         dmac0: dma-controller@b00b0000 {
 294                                 cell-index = <0>;
 295                                 compatible = "sirf,prima2-dmac";
 296                                 reg = <0xb00b0000 0x10000>;
 297                                 interrupts = <12>;
 298                                 clocks = <&clks 24>;
 299                                 #dma-cells = <1>;
 300                         };
 301
 302                         dmac1: dma-controller@b0160000 {
 303                                 cell-index = <1>;
 304                                 compatible = "sirf,prima2-dmac";
 305                                 reg = <0xb0160000 0x10000>;
 306                                 interrupts = <13>;
 307                                 clocks = <&clks 25>;
 308                                 #dma-cells = <1>;
 309                         };
 310
 311                         vip@b00C0000 {
 312                                 compatible = "sirf,prima2-vip";
 313                                 reg = <0xb00C0000 0x10000>;
 314                                 clocks = <&clks 31>;
 315                                 interrupts = <14>;
 316                                 sirf,vip-dma-rx-channel = <16>;
 317                         };
 318
 319                         spi0: spi@b00d0000 {
 320                                 cell-index = <0>;
 321                                 compatible = "sirf,prima2-spi";
 322                                 reg = <0xb00d0000 0x10000>;
 323                                 interrupts = <15>;
 324                                 sirf,spi-num-chipselects = <1>;
 325                                 dmas = <&dmac1 9>,
 326                                      <&dmac1 4>;
 327                                 dma-names = "rx", "tx";
 328                                 #address-cells = <1>;
 329                                 #size-cells = <0>;
 330                                 clocks = <&clks 19>;
 331                                 status = "disabled";
 332                         };
 333
 334                         spi1: spi@b0170000 {
 335                                 cell-index = <1>;
 336                                 compatible = "sirf,prima2-spi";
 337                                 reg = <0xb0170000 0x10000>;
 338                                 interrupts = <16>;
 339                                 sirf,spi-num-chipselects = <1>;
 340                                 dmas = <&dmac0 12>,
 341                                      <&dmac0 13>;
 342                                 dma-names = "rx", "tx";
 343                                 #address-cells = <1>;
 344                                 #size-cells = <0>;
 345                                 clocks = <&clks 20>;
 346                                 status = "disabled";
 347                         };
 348
 349                         i2c0: i2c@b00e0000 {
 350                                 cell-index = <0>;
 351                                 compatible = "sirf,prima2-i2c";
 352                                 reg = <0xb00e0000 0x10000>;
 353                                 interrupts = <24>;
 354                                 clocks = <&clks 17>;
 355                                 #address-cells = <1>;
 356                                 #size-cells = <0>;
 357                         };
 358
 359                         i2c1: i2c@b00f0000 {
 360                                 cell-index = <1>;
 361                                 compatible = "sirf,prima2-i2c";
 362                                 reg = <0xb00f0000 0x10000>;
 363                                 interrupts = <25>;
 364                                 clocks = <&clks 18>;
 365                                 #address-cells = <1>;
 366                                 #size-cells = <0>;
 367                         };
 368
 369                         tsc@b0110000 {
 370                                 compatible = "sirf,prima2-tsc";
 371                                 reg = <0xb0110000 0x10000>;
 372                                 interrupts = <33>;
 373                                 clocks = <&clks 16>;
 374                         };
 375
 376                         gpio: pinctrl@b0120000 {
 377                                 #gpio-cells = <2>;
 378                                 #interrupt-cells = <2>;
 379                                 compatible = "sirf,prima2-pinctrl";
 380                                 reg = <0xb0120000 0x10000>;
 381                                 interrupts = <43 44 45 46 47>;
 382                                 gpio-controller;
 383                                 interrupt-controller;
 384
 385                                 lcd_16pins_a: lcd0@0 {
 386                                         lcd {
 387                                                 sirf,pins = "lcd_16bitsgrp";
 388                                                 sirf,function = "lcd_16bits";
 389                                         };
 390                                 };
 391                                 lcd_18pins_a: lcd0@1 {
 392                                         lcd {
 393                                                 sirf,pins = "lcd_18bitsgrp";
 394                                                 sirf,function = "lcd_18bits";
 395                                         };
 396                                 };
 397                                 lcd_24pins_a: lcd0@2 {
 398                                         lcd {
 399                                                 sirf,pins = "lcd_24bitsgrp";
 400                                                 sirf,function = "lcd_24bits";
 401                                         };
 402                                 };
 403                                 lcdrom_pins_a: lcdrom0@0 {
 404                                         lcd {
 405                                                 sirf,pins = "lcdromgrp";
 406                                                 sirf,function = "lcdrom";
 407                                         };
 408                                 };
 409                                 uart0_pins_a: uart0@0 {
 410                                         uart {
 411                                                 sirf,pins = "uart0grp";
 412                                                 sirf,function = "uart0";
 413                                         };
 414                                 };
 415                                 uart0_noflow_pins_a: uart0@1 {
 416                                         uart {
 417                                                 sirf,pins = "uart0_nostreamctrlgrp";
 418                                                 sirf,function = "uart0_nostreamctrl";
 419                                         };
 420                                 };
 421                                 uart1_pins_a: uart1@0 {
 422                                         uart {
 423                                                 sirf,pins = "uart1grp";
 424                                                 sirf,function = "uart1";
 425                                         };
 426                                 };
 427                                 uart2_pins_a: uart2@0 {
 428                                         uart {
 429                                                 sirf,pins = "uart2grp";
 430                                                 sirf,function = "uart2";
 431                                         };
 432                                 };
 433                                 uart2_noflow_pins_a: uart2@1 {
 434                                         uart {
 435                                                 sirf,pins = "uart2_nostreamctrlgrp";
 436                                                 sirf,function = "uart2_nostreamctrl";
 437                                         };
 438                                 };
 439                                 spi0_pins_a: spi0@0 {
 440                                         spi {
 441                                                 sirf,pins = "spi0grp";
 442                                                 sirf,function = "spi0";
 443                                         };
 444                                 };
 445                                 spi1_pins_a: spi1@0 {
 446                                         spi {
 447                                                 sirf,pins = "spi1grp";
 448                                                 sirf,function = "spi1";
 449                                         };
 450                                 };
 451                                 i2c0_pins_a: i2c0@0 {
 452                                         i2c {
 453                                                 sirf,pins = "i2c0grp";
 454                                                 sirf,function = "i2c0";
 455                                         };
 456                                 };
 457                                 i2c1_pins_a: i2c1@0 {
 458                                         i2c {
 459                                                 sirf,pins = "i2c1grp";
 460                                                 sirf,function = "i2c1";
 461                                         };
 462                                 };
 463                                 pwm0_pins_a: pwm0@0 {
 464                                         pwm {
 465                                                 sirf,pins = "pwm0grp";
 466                                                 sirf,function = "pwm0";
 467                                         };
 468                                 };
 469                                 pwm1_pins_a: pwm1@0 {
 470                                         pwm {
 471                                                 sirf,pins = "pwm1grp";
 472                                                 sirf,function = "pwm1";
 473                                         };
 474                                 };
 475                                 pwm2_pins_a: pwm2@0 {
 476                                         pwm {
 477                                                 sirf,pins = "pwm2grp";
 478                                                 sirf,function = "pwm2";
 479                                         };
 480                                 };
 481                                 pwm3_pins_a: pwm3@0 {
 482                                         pwm {
 483                                                 sirf,pins = "pwm3grp";
 484                                                 sirf,function = "pwm3";
 485                                         };
 486                                 };
 487                                 gps_pins_a: gps@0 {
 488                                         gps {
 489                                                 sirf,pins = "gpsgrp";
 490                                                 sirf,function = "gps";
 491                                         };
 492                                 };
 493                                 vip_pins_a: vip@0 {
 494                                         vip {
 495                                                 sirf,pins = "vipgrp";
 496                                                 sirf,function = "vip";
 497                                         };
 498                                 };
 499                                 sdmmc0_pins_a: sdmmc0@0 {
 500                                         sdmmc0 {
 501                                                 sirf,pins = "sdmmc0grp";
 502                                                 sirf,function = "sdmmc0";
 503                                         };
 504                                 };
 505                                 sdmmc1_pins_a: sdmmc1@0 {
 506                                         sdmmc1 {
 507                                                 sirf,pins = "sdmmc1grp";
 508                                                 sirf,function = "sdmmc1";
 509                                         };
 510                                 };
 511                                 sdmmc2_pins_a: sdmmc2@0 {
 512                                         sdmmc2 {
 513                                                 sirf,pins = "sdmmc2grp";
 514                                                 sirf,function = "sdmmc2";
 515                                         };
 516                                 };
 517                                 sdmmc3_pins_a: sdmmc3@0 {
 518                                         sdmmc3 {
 519                                                 sirf,pins = "sdmmc3grp";
 520                                                 sirf,function = "sdmmc3";
 521                                         };
 522                                 };
 523                                 sdmmc4_pins_a: sdmmc4@0 {
 524                                         sdmmc4 {
 525                                                 sirf,pins = "sdmmc4grp";
 526                                                 sirf,function = "sdmmc4";
 527                                         };
 528                                 };
 529                                 sdmmc5_pins_a: sdmmc5@0 {
 530                                         sdmmc5 {
 531                                                 sirf,pins = "sdmmc5grp";
 532                                                 sirf,function = "sdmmc5";
 533                                         };
 534                                 };
 535                                 i2s_mclk_pins_a: i2s_mclk@0 {
 536                                         i2s_mclk {
 537                                                 sirf,pins = "i2smclkgrp";
 538                                                 sirf,function = "i2s_mclk";
 539                                         };
 540                                 };
 541                                 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
 542                                         i2s_ext_clk_input {
 543                                                 sirf,pins = "i2s_ext_clk_inputgrp";
 544                                                 sirf,function = "i2s_ext_clk_input";
 545                                         };
 546                                 };
 547                                 i2s_pins_a: i2s@0 {
 548                                         i2s {
 549                                                 sirf,pins = "i2sgrp";
 550                                                 sirf,function = "i2s";
 551                                         };
 552                                 };
 553                                 i2s_no_din_pins_a: i2s_no_din@0 {
 554                                         i2s_no_din {
 555                                                 sirf,pins = "i2s_no_dingrp";
 556                                                 sirf,function = "i2s_no_din";
 557                                         };
 558                                 };
 559                                 i2s_6chn_pins_a: i2s_6chn@0 {
 560                                         i2s_6chn {
 561                                                 sirf,pins = "i2s_6chngrp";
 562                                                 sirf,function = "i2s_6chn";
 563                                         };
 564                                 };
 565                                 ac97_pins_a: ac97@0 {
 566                                         ac97 {
 567                                                 sirf,pins = "ac97grp";
 568                                                 sirf,function = "ac97";
 569                                         };
 570                                 };
 571                                 nand_pins_a: nand@0 {
 572                                         nand {
 573                                                 sirf,pins = "nandgrp";
 574                                                 sirf,function = "nand";
 575                                         };
 576                                 };
 577                                 usp0_pins_a: usp0@0 {
 578                                         usp0 {
 579                                                 sirf,pins = "usp0grp";
 580                                                 sirf,function = "usp0";
 581                                         };
 582                                 };
 583                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 584                                         usp0 {
 585                                                 sirf,pins =
 586                                                         "usp0_uart_nostreamctrl_grp";
 587                                                 sirf,function =
 588                                                         "usp0_uart_nostreamctrl";
 589                                         };
 590                                 };
 591                                 usp0_only_utfs_pins_a: usp0@2 {
 592                                         usp0 {
 593                                                 sirf,pins = "usp0_only_utfs_grp";
 594                                                 sirf,function = "usp0_only_utfs";
 595                                         };
 596                                 };
 597                                 usp0_only_urfs_pins_a: usp0@3 {
 598                                         usp0 {
 599                                                 sirf,pins = "usp0_only_urfs_grp";
 600                                                 sirf,function = "usp0_only_urfs";
 601                                         };
 602                                 };
 603                                 usp1_pins_a: usp1@0 {
 604                                         usp1 {
 605                                                 sirf,pins = "usp1grp";
 606                                                 sirf,function = "usp1";
 607                                         };
 608                                 };
 609                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 610                                         usp1 {
 611                                                 sirf,pins =
 612                                                         "usp1_uart_nostreamctrl_grp";
 613                                                 sirf,function =
 614                                                         "usp1_uart_nostreamctrl";
 615                                         };
 616                                 };
 617                                 usp2_pins_a: usp2@0 {
 618                                         usp2 {
 619                                                 sirf,pins = "usp2grp";
 620                                                 sirf,function = "usp2";
 621                                         };
 622                                 };
 623                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 624                                         usp2 {
 625                                                 sirf,pins =
 626                                                         "usp2_uart_nostreamctrl_grp";
 627                                                 sirf,function =
 628                                                         "usp2_uart_nostreamctrl";
 629                                         };
 630                                 };
 631                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 632                                         usb0_utmi_drvbus {
 633                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 634                                                 sirf,function = "usb0_utmi_drvbus";
 635                                         };
 636                                 };
 637                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 638                                         usb1_utmi_drvbus {
 639                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 640                                                 sirf,function = "usb1_utmi_drvbus";
 641                                         };
 642                                 };
 643                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 644                                         usb1_dp_dn {
 645                                                 sirf,pins = "usb1_dp_dngrp";
 646                                                 sirf,function = "usb1_dp_dn";
 647                                         };
 648                                 };
 649                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 650                                         uart1_route_io_usb1 {
 651                                                 sirf,pins = "uart1_route_io_usb1grp";
 652                                                 sirf,function = "uart1_route_io_usb1";
 653                                         };
 654                                 };
 655                                 warm_rst_pins_a: warm_rst@0 {
 656                                         warm_rst {
 657                                                 sirf,pins = "warm_rstgrp";
 658                                                 sirf,function = "warm_rst";
 659                                         };
 660                                 };
 661                                 pulse_count_pins_a: pulse_count@0 {
 662                                         pulse_count {
 663                                                 sirf,pins = "pulse_countgrp";
 664                                                 sirf,function = "pulse_count";
 665                                         };
 666                                 };
 667                                 cko0_pins_a: cko0@0 {
 668                                         cko0 {
 669                                                 sirf,pins = "cko0grp";
 670                                                 sirf,function = "cko0";
 671                                         };
 672                                 };
 673                                 cko1_pins_a: cko1@0 {
 674                                         cko1 {
 675                                                 sirf,pins = "cko1grp";
 676                                                 sirf,function = "cko1";
 677                                         };
 678                                 };
 679                         };
 680
 681                         pwm@b0130000 {
 682                                 compatible = "sirf,prima2-pwm";
 683                                 reg = <0xb0130000 0x10000>;
 684                                 clocks = <&clks 21>;
 685                         };
 686
 687                         efusesys@b0140000 {
 688                                 compatible = "sirf,prima2-efuse";
 689                                 reg = <0xb0140000 0x10000>;
 690                                 clocks = <&clks 22>;
 691                         };
 692
 693                         pulsec@b0150000 {
 694                                 compatible = "sirf,prima2-pulsec";
 695                                 reg = <0xb0150000 0x10000>;
 696                                 interrupts = <48>;
 697                                 clocks = <&clks 23>;
 698                         };
 699
 700                         pci-iobg {
 701                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 702                                 #address-cells = <1>;
 703                                 #size-cells = <1>;
 704                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 705
 706                                 sd0: sdhci@56000000 {
 707                                         cell-index = <0>;
 708                                         compatible = "sirf,prima2-sdhc";
 709                                         reg = <0x56000000 0x100000>;
 710                                         interrupts = <38>;
 711                                         status = "disabled";
 712                                         bus-width = <8>;
 713                                         clocks = <&clks 36>;
 714                                 };
 715
 716                                 sd1: sdhci@56100000 {
 717                                         cell-index = <1>;
 718                                         compatible = "sirf,prima2-sdhc";
 719                                         reg = <0x56100000 0x100000>;
 720                                         interrupts = <38>;
 721                                         status = "disabled";
 722                                         bus-width = <4>;
 723                                         clocks = <&clks 36>;
 724                                 };
 725
 726                                 sd2: sdhci@56200000 {
 727                                         cell-index = <2>;
 728                                         compatible = "sirf,prima2-sdhc";
 729                                         reg = <0x56200000 0x100000>;
 730                                         interrupts = <23>;
 731                                         status = "disabled";
 732                                         clocks = <&clks 37>;
 733                                 };
 734
 735                                 sd3: sdhci@56300000 {
 736                                         cell-index = <3>;
 737                                         compatible = "sirf,prima2-sdhc";
 738                                         reg = <0x56300000 0x100000>;
 739                                         interrupts = <23>;
 740                                         status = "disabled";
 741                                         clocks = <&clks 37>;
 742                                 };
 743
 744                                 sd4: sdhci@56400000 {
 745                                         cell-index = <4>;
 746                                         compatible = "sirf,prima2-sdhc";
 747                                         reg = <0x56400000 0x100000>;
 748                                         interrupts = <39>;
 749                                         status = "disabled";
 750                                         clocks = <&clks 38>;
 751                                 };
 752
 753                                 sd5: sdhci@56500000 {
 754                                         cell-index = <5>;
 755                                         compatible = "sirf,prima2-sdhc";
 756                                         reg = <0x56500000 0x100000>;
 757                                         interrupts = <39>;
 758                                         clocks = <&clks 38>;
 759                                 };
 760
 761                                 pci-copy@57900000 {
 762                                         compatible = "sirf,prima2-pcicp";
 763                                         reg = <0x57900000 0x100000>;
 764                                         interrupts = <40>;
 765                                 };
 766
 767                                 rom-interface@57a00000 {
 768                                         compatible = "sirf,prima2-romif";
 769                                         reg = <0x57a00000 0x100000>;
 770                                 };
 771                         };
 772                 };
 773
 774                 rtc-iobg {
 775                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 776                         #address-cells = <1>;
 777                         #size-cells = <1>;
 778                         reg = <0x80030000 0x10000>;
 779
 780                         gpsrtc@1000 {
 781                                 compatible = "sirf,prima2-gpsrtc";
 782                                 reg = <0x1000 0x1000>;
 783                                 interrupts = <55 56 57>;
 784                         };
 785
 786                         sysrtc@2000 {
 787                                 compatible = "sirf,prima2-sysrtc";
 788                                 reg = <0x2000 0x1000>;
 789                                 interrupts = <52 53 54>;
 790                         };
 791
 792                         minigpsrtc@2000 {
 793                                 compatible = "sirf,prima2-minigpsrtc";
 794                                 reg = <0x2000 0x1000>;
 795                                 interrupts = <54>;
 796                         };
 797
 798                         pwrc@3000 {
 799                                 compatible = "sirf,prima2-pwrc";
 800                                 reg = <0x3000 0x1000>;
 801                                 interrupts = <32>;
 802                         };
 803                 };
 804
 805                 uus-iobg {
 806                         compatible = "simple-bus";
 807                         #address-cells = <1>;
 808                         #size-cells = <1>;
 809                         ranges = <0xb8000000 0xb8000000 0x40000>;
 810
 811                         usb0: usb@b00e0000 {
 812                                 compatible = "chipidea,ci13611a-prima2";
 813                                 reg = <0xb8000000 0x10000>;
 814                                 interrupts = <10>;
 815                                 clocks = <&clks 40>;
 816                         };
 817
 818                         usb1: usb@b00f0000 {
 819                                 compatible = "chipidea,ci13611a-prima2";
 820                                 reg = <0xb8010000 0x10000>;
 821                                 interrupts = <11>;
 822                                 clocks = <&clks 41>;
 823                         };
 824
 825                         sata@b00f0000 {
 826                                 compatible = "synopsys,dwc-ahsata";
 827                                 reg = <0xb8020000 0x10000>;
 828                                 interrupts = <37>;
 829                         };
 830
 831                         security@b00f0000 {
 832                                 compatible = "sirf,prima2-security";
 833                                 reg = <0xb8030000 0x10000>;
 834                                 interrupts = <42>;
 835                                 clocks = <&clks 7>;
 836                         };
 837                 };
 838         };
 839 };