arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                         clocks = <&clks 12>;
  33                         operating-points = <
  34                                 /* kHz    uV */
  35                                 200000  1025000
  36                                 400000  1025000
  37                                 664000  1050000
  38                                 800000  1100000
  39                         >;
  40                         clock-latency = <150000>;
  41                 };
  42         };
  43
  44         axi {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x40000000 0x40000000 0x80000000>;
  49
  50                 l2-cache-controller@80040000 {
  51                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  52                         reg = <0x80040000 0x1000>;
  53                         interrupts = <59>;
  54                         arm,tag-latency = <1 1 1>;
  55                         arm,data-latency = <1 1 1>;
  56                         arm,filter-ranges = <0 0x40000000>;
  57                 };
  58
  59                 intc: interrupt-controller@80020000 {
  60                         #interrupt-cells = <1>;
  61                         interrupt-controller;
  62                         compatible = "sirf,prima2-intc";
  63                         reg = <0x80020000 0x1000>;
  64                 };
  65
  66                 sys-iobg {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges = <0x88000000 0x88000000 0x40000>;
  71
  72                         clks: clock-controller@88000000 {
  73                                 compatible = "sirf,prima2-clkc";
  74                                 reg = <0x88000000 0x1000>;
  75                                 interrupts = <3>;
  76                                 #clock-cells = <1>;
  77                         };
  78
  79                         rstc: reset-controller@88010000 {
  80                                 compatible = "sirf,prima2-rstc";
  81                                 reg = <0x88010000 0x1000>;
  82                                 #reset-cells = <1>;
  83                         };
  84
  85                         rsc-controller@88020000 {
  86                                 compatible = "sirf,prima2-rsc";
  87                                 reg = <0x88020000 0x1000>;
  88                         };
  89
  90                         cphifbg@88030000 {
  91                                 compatible = "sirf,prima2-cphifbg";
  92                                 reg = <0x88030000 0x1000>;
  93                                 clocks = <&clks 42>;
  94                         };
  95                 };
  96
  97                 mem-iobg {
  98                         compatible = "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0x90000000 0x90000000 0x10000>;
 102
 103                         memory-controller@90000000 {
 104                                 compatible = "sirf,prima2-memc";
 105                                 reg = <0x90000000 0x2000>;
 106                                 interrupts = <27>;
 107                                 clocks = <&clks 5>;
 108                         };
 109
 110                         memc-monitor {
 111                                 compatible = "sirf,prima2-memcmon";
 112                                 reg = <0x90002000 0x200>;
 113                                 interrupts = <4>;
 114                                 clocks = <&clks 32>;
 115                         };
 116                 };
 117
 118                 disp-iobg {
 119                         compatible = "simple-bus";
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         ranges = <0x90010000 0x90010000 0x30000>;
 123
 124                         display@90010000 {
 125                                 compatible = "sirf,prima2-lcd";
 126                                 reg = <0x90010000 0x20000>;
 127                                 interrupts = <30>;
 128                         };
 129
 130                         vpp@90020000 {
 131                                 compatible = "sirf,prima2-vpp";
 132                                 reg = <0x90020000 0x10000>;
 133                                 interrupts = <31>;
 134                                 clocks = <&clks 35>;
 135                         };
 136                 };
 137
 138                 graphics-iobg {
 139                         compatible = "simple-bus";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x98000000 0x98000000 0x8000000>;
 143
 144                         graphics@98000000 {
 145                                 compatible = "powervr,sgx531";
 146                                 reg = <0x98000000 0x8000000>;
 147                                 interrupts = <6>;
 148                                 clocks = <&clks 32>;
 149                         };
 150                 };
 151
 152                 multimedia-iobg {
 153                         compatible = "simple-bus";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 157
 158                         multimedia@a0000000 {
 159                                 compatible = "sirf,prima2-video-codec";
 160                                 reg = <0xa0000000 0x8000000>;
 161                                 interrupts = <5>;
 162                                 clocks = <&clks 33>;
 163                         };
 164                 };
 165
 166                 dsp-iobg {
 167                         compatible = "simple-bus";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 171
 172                         dspif@a8000000 {
 173                                 compatible = "sirf,prima2-dspif";
 174                                 reg = <0xa8000000 0x10000>;
 175                                 interrupts = <9>;
 176                         };
 177
 178                         gps@a8010000 {
 179                                 compatible = "sirf,prima2-gps";
 180                                 reg = <0xa8010000 0x10000>;
 181                                 interrupts = <7>;
 182                                 clocks = <&clks 9>;
 183                         };
 184
 185                         dsp@a9000000 {
 186                                 compatible = "sirf,prima2-dsp";
 187                                 reg = <0xa9000000 0x1000000>;
 188                                 interrupts = <8>;
 189                                 clocks = <&clks 8>;
 190                         };
 191                 };
 192
 193                 peri-iobg {
 194                         compatible = "simple-bus";
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges = <0xb0000000 0xb0000000 0x180000>,
 198                                <0x56000000 0x56000000 0x1b00000>;
 199
 200                         timer@b0020000 {
 201                                 compatible = "sirf,prima2-tick";
 202                                 reg = <0xb0020000 0x1000>;
 203                                 interrupts = <0>;
 204                         };
 205
 206                         nand@b0030000 {
 207                                 compatible = "sirf,prima2-nand";
 208                                 reg = <0xb0030000 0x10000>;
 209                                 interrupts = <41>;
 210                                 clocks = <&clks 26>;
 211                         };
 212
 213                         audio@b0040000 {
 214                                 compatible = "sirf,prima2-audio";
 215                                 reg = <0xb0040000 0x10000>;
 216                                 interrupts = <35>;
 217                                 clocks = <&clks 27>;
 218                         };
 219
 220                         uart0: uart@b0050000 {
 221                                 cell-index = <0>;
 222                                 compatible = "sirf,prima2-uart";
 223                                 reg = <0xb0050000 0x1000>;
 224                                 interrupts = <17>;
 225                                 fifosize = <128>;
 226                                 clocks = <&clks 13>;
 227                                 dmas = <&dmac1 5>, <&dmac0 2>;
 228                                 dma-names = "rx", "tx";
 229                         };
 230
 231                         uart1: uart@b0060000 {
 232                                 cell-index = <1>;
 233                                 compatible = "sirf,prima2-uart";
 234                                 reg = <0xb0060000 0x1000>;
 235                                 interrupts = <18>;
 236                                 fifosize = <32>;
 237                                 clocks = <&clks 14>;
 238                         };
 239
 240                         uart2: uart@b0070000 {
 241                                 cell-index = <2>;
 242                                 compatible = "sirf,prima2-uart";
 243                                 reg = <0xb0070000 0x1000>;
 244                                 interrupts = <19>;
 245                                 fifosize = <128>;
 246                                 clocks = <&clks 15>;
 247                                 dmas = <&dmac0 6>, <&dmac0 7>;
 248                                 dma-names = "rx", "tx";
 249                         };
 250
 251                         usp0: usp@b0080000 {
 252                                 cell-index = <0>;
 253                                 compatible = "sirf,prima2-usp";
 254                                 reg = <0xb0080000 0x10000>;
 255                                 interrupts = <20>;
 256                                 fifosize = <128>;
 257                                 clocks = <&clks 28>;
 258                                 dmas = <&dmac1 1>, <&dmac1 2>;
 259                                 dma-names = "rx", "tx";
 260                         };
 261
 262                         usp1: usp@b0090000 {
 263                                 cell-index = <1>;
 264                                 compatible = "sirf,prima2-usp";
 265                                 reg = <0xb0090000 0x10000>;
 266                                 interrupts = <21>;
 267                                 fifosize = <128>;
 268                                 clocks = <&clks 29>;
 269                                 dmas = <&dmac0 14>, <&dmac0 15>;
 270                                 dma-names = "rx", "tx";
 271                         };
 272
 273                         usp2: usp@b00a0000 {
 274                                 cell-index = <2>;
 275                                 compatible = "sirf,prima2-usp";
 276                                 reg = <0xb00a0000 0x10000>;
 277                                 interrupts = <22>;
 278                                 fifosize = <128>;
 279                                 clocks = <&clks 30>;
 280                                 dmas = <&dmac0 10>, <&dmac0 11>;
 281                                 dma-names = "rx", "tx";
 282                         };
 283
 284                         dmac0: dma-controller@b00b0000 {
 285                                 cell-index = <0>;
 286                                 compatible = "sirf,prima2-dmac";
 287                                 reg = <0xb00b0000 0x10000>;
 288                                 interrupts = <12>;
 289                                 clocks = <&clks 24>;
 290                                 #dma-cells = <1>;
 291                         };
 292
 293                         dmac1: dma-controller@b0160000 {
 294                                 cell-index = <1>;
 295                                 compatible = "sirf,prima2-dmac";
 296                                 reg = <0xb0160000 0x10000>;
 297                                 interrupts = <13>;
 298                                 clocks = <&clks 25>;
 299                                 #dma-cells = <1>;
 300                         };
 301
 302                         vip@b00C0000 {
 303                                 compatible = "sirf,prima2-vip";
 304                                 reg = <0xb00C0000 0x10000>;
 305                                 clocks = <&clks 31>;
 306                                 interrupts = <14>;
 307                                 sirf,vip-dma-rx-channel = <16>;
 308                         };
 309
 310                         spi0: spi@b00d0000 {
 311                                 cell-index = <0>;
 312                                 compatible = "sirf,prima2-spi";
 313                                 reg = <0xb00d0000 0x10000>;
 314                                 interrupts = <15>;
 315                                 sirf,spi-num-chipselects = <1>;
 316                                 sirf,spi-dma-rx-channel = <25>;
 317                                 sirf,spi-dma-tx-channel = <20>;
 318                                 #address-cells = <1>;
 319                                 #size-cells = <0>;
 320                                 clocks = <&clks 19>;
 321                                 status = "disabled";
 322                         };
 323
 324                         spi1: spi@b0170000 {
 325                                 cell-index = <1>;
 326                                 compatible = "sirf,prima2-spi";
 327                                 reg = <0xb0170000 0x10000>;
 328                                 interrupts = <16>;
 329                                 sirf,spi-num-chipselects = <1>;
 330                                 sirf,spi-dma-rx-channel = <12>;
 331                                 sirf,spi-dma-tx-channel = <13>;
 332                                 #address-cells = <1>;
 333                                 #size-cells = <0>;
 334                                 clocks = <&clks 20>;
 335                                 status = "disabled";
 336                         };
 337
 338                         i2c0: i2c@b00e0000 {
 339                                 cell-index = <0>;
 340                                 compatible = "sirf,prima2-i2c";
 341                                 reg = <0xb00e0000 0x10000>;
 342                                 interrupts = <24>;
 343                                 clocks = <&clks 17>;
 344                                 #address-cells = <1>;
 345                                 #size-cells = <0>;
 346                         };
 347
 348                         i2c1: i2c@b00f0000 {
 349                                 cell-index = <1>;
 350                                 compatible = "sirf,prima2-i2c";
 351                                 reg = <0xb00f0000 0x10000>;
 352                                 interrupts = <25>;
 353                                 clocks = <&clks 18>;
 354                                 #address-cells = <1>;
 355                                 #size-cells = <0>;
 356                         };
 357
 358                         tsc@b0110000 {
 359                                 compatible = "sirf,prima2-tsc";
 360                                 reg = <0xb0110000 0x10000>;
 361                                 interrupts = <33>;
 362                                 clocks = <&clks 16>;
 363                         };
 364
 365                         gpio: pinctrl@b0120000 {
 366                                 #gpio-cells = <2>;
 367                                 #interrupt-cells = <2>;
 368                                 compatible = "sirf,prima2-pinctrl";
 369                                 reg = <0xb0120000 0x10000>;
 370                                 interrupts = <43 44 45 46 47>;
 371                                 gpio-controller;
 372                                 interrupt-controller;
 373
 374                                 lcd_16pins_a: lcd0@0 {
 375                                         lcd {
 376                                                 sirf,pins = "lcd_16bitsgrp";
 377                                                 sirf,function = "lcd_16bits";
 378                                         };
 379                                 };
 380                                 lcd_18pins_a: lcd0@1 {
 381                                         lcd {
 382                                                 sirf,pins = "lcd_18bitsgrp";
 383                                                 sirf,function = "lcd_18bits";
 384                                         };
 385                                 };
 386                                 lcd_24pins_a: lcd0@2 {
 387                                         lcd {
 388                                                 sirf,pins = "lcd_24bitsgrp";
 389                                                 sirf,function = "lcd_24bits";
 390                                         };
 391                                 };
 392                                 lcdrom_pins_a: lcdrom0@0 {
 393                                         lcd {
 394                                                 sirf,pins = "lcdromgrp";
 395                                                 sirf,function = "lcdrom";
 396                                         };
 397                                 };
 398                                 uart0_pins_a: uart0@0 {
 399                                         uart {
 400                                                 sirf,pins = "uart0grp";
 401                                                 sirf,function = "uart0";
 402                                         };
 403                                 };
 404                                 uart0_noflow_pins_a: uart0@1 {
 405                                         uart {
 406                                                 sirf,pins = "uart0_nostreamctrlgrp";
 407                                                 sirf,function = "uart0_nostreamctrl";
 408                                         };
 409                                 };
 410                                 uart1_pins_a: uart1@0 {
 411                                         uart {
 412                                                 sirf,pins = "uart1grp";
 413                                                 sirf,function = "uart1";
 414                                         };
 415                                 };
 416                                 uart2_pins_a: uart2@0 {
 417                                         uart {
 418                                                 sirf,pins = "uart2grp";
 419                                                 sirf,function = "uart2";
 420                                         };
 421                                 };
 422                                 uart2_noflow_pins_a: uart2@1 {
 423                                         uart {
 424                                                 sirf,pins = "uart2_nostreamctrlgrp";
 425                                                 sirf,function = "uart2_nostreamctrl";
 426                                         };
 427                                 };
 428                                 spi0_pins_a: spi0@0 {
 429                                         spi {
 430                                                 sirf,pins = "spi0grp";
 431                                                 sirf,function = "spi0";
 432                                         };
 433                                 };
 434                                 spi1_pins_a: spi1@0 {
 435                                         spi {
 436                                                 sirf,pins = "spi1grp";
 437                                                 sirf,function = "spi1";
 438                                         };
 439                                 };
 440                                 i2c0_pins_a: i2c0@0 {
 441                                         i2c {
 442                                                 sirf,pins = "i2c0grp";
 443                                                 sirf,function = "i2c0";
 444                                         };
 445                                 };
 446                                 i2c1_pins_a: i2c1@0 {
 447                                         i2c {
 448                                                 sirf,pins = "i2c1grp";
 449                                                 sirf,function = "i2c1";
 450                                         };
 451                                 };
 452                                 pwm0_pins_a: pwm0@0 {
 453                                         pwm {
 454                                                 sirf,pins = "pwm0grp";
 455                                                 sirf,function = "pwm0";
 456                                         };
 457                                 };
 458                                 pwm1_pins_a: pwm1@0 {
 459                                         pwm {
 460                                                 sirf,pins = "pwm1grp";
 461                                                 sirf,function = "pwm1";
 462                                         };
 463                                 };
 464                                 pwm2_pins_a: pwm2@0 {
 465                                         pwm {
 466                                                 sirf,pins = "pwm2grp";
 467                                                 sirf,function = "pwm2";
 468                                         };
 469                                 };
 470                                 pwm3_pins_a: pwm3@0 {
 471                                         pwm {
 472                                                 sirf,pins = "pwm3grp";
 473                                                 sirf,function = "pwm3";
 474                                         };
 475                                 };
 476                                 gps_pins_a: gps@0 {
 477                                         gps {
 478                                                 sirf,pins = "gpsgrp";
 479                                                 sirf,function = "gps";
 480                                         };
 481                                 };
 482                                 vip_pins_a: vip@0 {
 483                                         vip {
 484                                                 sirf,pins = "vipgrp";
 485                                                 sirf,function = "vip";
 486                                         };
 487                                 };
 488                                 sdmmc0_pins_a: sdmmc0@0 {
 489                                         sdmmc0 {
 490                                                 sirf,pins = "sdmmc0grp";
 491                                                 sirf,function = "sdmmc0";
 492                                         };
 493                                 };
 494                                 sdmmc1_pins_a: sdmmc1@0 {
 495                                         sdmmc1 {
 496                                                 sirf,pins = "sdmmc1grp";
 497                                                 sirf,function = "sdmmc1";
 498                                         };
 499                                 };
 500                                 sdmmc2_pins_a: sdmmc2@0 {
 501                                         sdmmc2 {
 502                                                 sirf,pins = "sdmmc2grp";
 503                                                 sirf,function = "sdmmc2";
 504                                         };
 505                                 };
 506                                 sdmmc3_pins_a: sdmmc3@0 {
 507                                         sdmmc3 {
 508                                                 sirf,pins = "sdmmc3grp";
 509                                                 sirf,function = "sdmmc3";
 510                                         };
 511                                 };
 512                                 sdmmc4_pins_a: sdmmc4@0 {
 513                                         sdmmc4 {
 514                                                 sirf,pins = "sdmmc4grp";
 515                                                 sirf,function = "sdmmc4";
 516                                         };
 517                                 };
 518                                 sdmmc5_pins_a: sdmmc5@0 {
 519                                         sdmmc5 {
 520                                                 sirf,pins = "sdmmc5grp";
 521                                                 sirf,function = "sdmmc5";
 522                                         };
 523                                 };
 524                                 i2s_pins_a: i2s@0 {
 525                                         i2s {
 526                                                 sirf,pins = "i2sgrp";
 527                                                 sirf,function = "i2s";
 528                                         };
 529                                 };
 530                                 ac97_pins_a: ac97@0 {
 531                                         ac97 {
 532                                                 sirf,pins = "ac97grp";
 533                                                 sirf,function = "ac97";
 534                                         };
 535                                 };
 536                                 nand_pins_a: nand@0 {
 537                                         nand {
 538                                                 sirf,pins = "nandgrp";
 539                                                 sirf,function = "nand";
 540                                         };
 541                                 };
 542                                 usp0_pins_a: usp0@0 {
 543                                         usp0 {
 544                                                 sirf,pins = "usp0grp";
 545                                                 sirf,function = "usp0";
 546                                         };
 547                                 };
 548                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 549                                         usp0 {
 550                                                 sirf,pins =
 551                                                         "usp0_uart_nostreamctrl_grp";
 552                                                 sirf,function =
 553                                                         "usp0_uart_nostreamctrl";
 554                                         };
 555                                 };
 556                                 usp0_only_utfs_pins_a: usp0@2 {
 557                                         usp0 {
 558                                                 sirf,pins = "usp0_only_utfs_grp";
 559                                                 sirf,function = "usp0_only_utfs";
 560                                         };
 561                                 };
 562                                 usp0_only_urfs_pins_a: usp0@3 {
 563                                         usp0 {
 564                                                 sirf,pins = "usp0_only_urfs_grp";
 565                                                 sirf,function = "usp0_only_urfs";
 566                                         };
 567                                 };
 568                                 usp1_pins_a: usp1@0 {
 569                                         usp1 {
 570                                                 sirf,pins = "usp1grp";
 571                                                 sirf,function = "usp1";
 572                                         };
 573                                 };
 574                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 575                                         usp1 {
 576                                                 sirf,pins =
 577                                                         "usp1_uart_nostreamctrl_grp";
 578                                                 sirf,function =
 579                                                         "usp1_uart_nostreamctrl";
 580                                         };
 581                                 };
 582                                 usp2_pins_a: usp2@0 {
 583                                         usp2 {
 584                                                 sirf,pins = "usp2grp";
 585                                                 sirf,function = "usp2";
 586                                         };
 587                                 };
 588                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 589                                         usp2 {
 590                                                 sirf,pins =
 591                                                         "usp2_uart_nostreamctrl_grp";
 592                                                 sirf,function =
 593                                                         "usp2_uart_nostreamctrl";
 594                                         };
 595                                 };
 596                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 597                                         usb0_utmi_drvbus {
 598                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 599                                                 sirf,function = "usb0_utmi_drvbus";
 600                                         };
 601                                 };
 602                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 603                                         usb1_utmi_drvbus {
 604                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 605                                                 sirf,function = "usb1_utmi_drvbus";
 606                                         };
 607                                 };
 608                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 609                                         usb1_dp_dn {
 610                                                 sirf,pins = "usb1_dp_dngrp";
 611                                                 sirf,function = "usb1_dp_dn";
 612                                         };
 613                                 };
 614                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 615                                         uart1_route_io_usb1 {
 616                                                 sirf,pins = "uart1_route_io_usb1grp";
 617                                                 sirf,function = "uart1_route_io_usb1";
 618                                         };
 619                                 };
 620                                 warm_rst_pins_a: warm_rst@0 {
 621                                         warm_rst {
 622                                                 sirf,pins = "warm_rstgrp";
 623                                                 sirf,function = "warm_rst";
 624                                         };
 625                                 };
 626                                 pulse_count_pins_a: pulse_count@0 {
 627                                         pulse_count {
 628                                                 sirf,pins = "pulse_countgrp";
 629                                                 sirf,function = "pulse_count";
 630                                         };
 631                                 };
 632                                 cko0_pins_a: cko0@0 {
 633                                         cko0 {
 634                                                 sirf,pins = "cko0grp";
 635                                                 sirf,function = "cko0";
 636                                         };
 637                                 };
 638                                 cko1_pins_a: cko1@0 {
 639                                         cko1 {
 640                                                 sirf,pins = "cko1grp";
 641                                                 sirf,function = "cko1";
 642                                         };
 643                                 };
 644                         };
 645
 646                         pwm@b0130000 {
 647                                 compatible = "sirf,prima2-pwm";
 648                                 reg = <0xb0130000 0x10000>;
 649                                 clocks = <&clks 21>;
 650                         };
 651
 652                         efusesys@b0140000 {
 653                                 compatible = "sirf,prima2-efuse";
 654                                 reg = <0xb0140000 0x10000>;
 655                                 clocks = <&clks 22>;
 656                         };
 657
 658                         pulsec@b0150000 {
 659                                 compatible = "sirf,prima2-pulsec";
 660                                 reg = <0xb0150000 0x10000>;
 661                                 interrupts = <48>;
 662                                 clocks = <&clks 23>;
 663                         };
 664
 665                         pci-iobg {
 666                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 667                                 #address-cells = <1>;
 668                                 #size-cells = <1>;
 669                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 670
 671                                 sd0: sdhci@56000000 {
 672                                         cell-index = <0>;
 673                                         compatible = "sirf,prima2-sdhc";
 674                                         reg = <0x56000000 0x100000>;
 675                                         interrupts = <38>;
 676                                         status = "disabled";
 677                                         bus-width = <8>;
 678                                         clocks = <&clks 36>;
 679                                 };
 680
 681                                 sd1: sdhci@56100000 {
 682                                         cell-index = <1>;
 683                                         compatible = "sirf,prima2-sdhc";
 684                                         reg = <0x56100000 0x100000>;
 685                                         interrupts = <38>;
 686                                         status = "disabled";
 687                                         bus-width = <4>;
 688                                         clocks = <&clks 36>;
 689                                 };
 690
 691                                 sd2: sdhci@56200000 {
 692                                         cell-index = <2>;
 693                                         compatible = "sirf,prima2-sdhc";
 694                                         reg = <0x56200000 0x100000>;
 695                                         interrupts = <23>;
 696                                         status = "disabled";
 697                                         clocks = <&clks 37>;
 698                                 };
 699
 700                                 sd3: sdhci@56300000 {
 701                                         cell-index = <3>;
 702                                         compatible = "sirf,prima2-sdhc";
 703                                         reg = <0x56300000 0x100000>;
 704                                         interrupts = <23>;
 705                                         status = "disabled";
 706                                         clocks = <&clks 37>;
 707                                 };
 708
 709                                 sd4: sdhci@56400000 {
 710                                         cell-index = <4>;
 711                                         compatible = "sirf,prima2-sdhc";
 712                                         reg = <0x56400000 0x100000>;
 713                                         interrupts = <39>;
 714                                         status = "disabled";
 715                                         clocks = <&clks 38>;
 716                                 };
 717
 718                                 sd5: sdhci@56500000 {
 719                                         cell-index = <5>;
 720                                         compatible = "sirf,prima2-sdhc";
 721                                         reg = <0x56500000 0x100000>;
 722                                         interrupts = <39>;
 723                                         clocks = <&clks 38>;
 724                                 };
 725
 726                                 pci-copy@57900000 {
 727                                         compatible = "sirf,prima2-pcicp";
 728                                         reg = <0x57900000 0x100000>;
 729                                         interrupts = <40>;
 730                                 };
 731
 732                                 rom-interface@57a00000 {
 733                                         compatible = "sirf,prima2-romif";
 734                                         reg = <0x57a00000 0x100000>;
 735                                 };
 736                         };
 737                 };
 738
 739                 rtc-iobg {
 740                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 741                         #address-cells = <1>;
 742                         #size-cells = <1>;
 743                         reg = <0x80030000 0x10000>;
 744
 745                         gpsrtc@1000 {
 746                                 compatible = "sirf,prima2-gpsrtc";
 747                                 reg = <0x1000 0x1000>;
 748                                 interrupts = <55 56 57>;
 749                         };
 750
 751                         sysrtc@2000 {
 752                                 compatible = "sirf,prima2-sysrtc";
 753                                 reg = <0x2000 0x1000>;
 754                                 interrupts = <52 53 54>;
 755                         };
 756
 757                         minigpsrtc@2000 {
 758                                 compatible = "sirf,prima2-minigpsrtc";
 759                                 reg = <0x2000 0x1000>;
 760                                 interrupts = <54>;
 761                         };
 762
 763                         pwrc@3000 {
 764                                 compatible = "sirf,prima2-pwrc";
 765                                 reg = <0x3000 0x1000>;
 766                                 interrupts = <32>;
 767                         };
 768                 };
 769
 770                 uus-iobg {
 771                         compatible = "simple-bus";
 772                         #address-cells = <1>;
 773                         #size-cells = <1>;
 774                         ranges = <0xb8000000 0xb8000000 0x40000>;
 775
 776                         usb0: usb@b00e0000 {
 777                                 compatible = "chipidea,ci13611a-prima2";
 778                                 reg = <0xb8000000 0x10000>;
 779                                 interrupts = <10>;
 780                                 clocks = <&clks 40>;
 781                         };
 782
 783                         usb1: usb@b00f0000 {
 784                                 compatible = "chipidea,ci13611a-prima2";
 785                                 reg = <0xb8010000 0x10000>;
 786                                 interrupts = <11>;
 787                                 clocks = <&clks 41>;
 788                         };
 789
 790                         sata@b00f0000 {
 791                                 compatible = "synopsys,dwc-ahsata";
 792                                 reg = <0xb8020000 0x10000>;
 793                                 interrupts = <37>;
 794                         };
 795
 796                         security@b00f0000 {
 797                                 compatible = "sirf,prima2-security";
 798                                 reg = <0xb8030000 0x10000>;
 799                                 interrupts = <42>;
 800                                 clocks = <&clks 7>;
 801                         };
 802                 };
 803         };
 804 };