arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                 };
  31         };
  32
  33         axi {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges = <0x40000000 0x40000000 0x80000000>;
  38
  39                 l2-cache-controller@80040000 {
  40                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  41                         reg = <0x80040000 0x1000>;
  42                         interrupts = <59>;
  43                         arm,tag-latency = <1 1 1>;
  44                         arm,data-latency = <1 1 1>;
  45                         arm,filter-ranges = <0 0x40000000>;
  46                 };
  47
  48                 intc: interrupt-controller@80020000 {
  49                         #interrupt-cells = <1>;
  50                         interrupt-controller;
  51                         compatible = "sirf,prima2-intc";
  52                         reg = <0x80020000 0x1000>;
  53                 };
  54
  55                 sys-iobg {
  56                         compatible = "simple-bus";
  57                         #address-cells = <1>;
  58                         #size-cells = <1>;
  59                         ranges = <0x88000000 0x88000000 0x40000>;
  60
  61                         clock-controller@88000000 {
  62                                 compatible = "sirf,prima2-clkc";
  63                                 reg = <0x88000000 0x1000>;
  64                                 interrupts = <3>;
  65                         };
  66
  67                         reset-controller@88010000 {
  68                                 compatible = "sirf,prima2-rstc";
  69                                 reg = <0x88010000 0x1000>;
  70                         };
  71
  72                         rsc-controller@88020000 {
  73                                 compatible = "sirf,prima2-rsc";
  74                                 reg = <0x88020000 0x1000>;
  75                         };
  76                 };
  77
  78                 mem-iobg {
  79                         compatible = "simple-bus";
  80                         #address-cells = <1>;
  81                         #size-cells = <1>;
  82                         ranges = <0x90000000 0x90000000 0x10000>;
  83
  84                         memory-controller@90000000 {
  85                                 compatible = "sirf,prima2-memc";
  86                                 reg = <0x90000000 0x10000>;
  87                                 interrupts = <27>;
  88                         };
  89                 };
  90
  91                 disp-iobg {
  92                         compatible = "simple-bus";
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         ranges = <0x90010000 0x90010000 0x30000>;
  96
  97                         display@90010000 {
  98                                 compatible = "sirf,prima2-lcd";
  99                                 reg = <0x90010000 0x20000>;
 100                                 interrupts = <30>;
 101                         };
 102
 103                         vpp@90020000 {
 104                                 compatible = "sirf,prima2-vpp";
 105                                 reg = <0x90020000 0x10000>;
 106                                 interrupts = <31>;
 107                         };
 108                 };
 109
 110                 graphics-iobg {
 111                         compatible = "simple-bus";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         ranges = <0x98000000 0x98000000 0x8000000>;
 115
 116                         graphics@98000000 {
 117                                 compatible = "powervr,sgx531";
 118                                 reg = <0x98000000 0x8000000>;
 119                                 interrupts = <6>;
 120                         };
 121                 };
 122
 123                 multimedia-iobg {
 124                         compatible = "simple-bus";
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 128
 129                         multimedia@a0000000 {
 130                                 compatible = "sirf,prima2-video-codec";
 131                                 reg = <0xa0000000 0x8000000>;
 132                                 interrupts = <5>;
 133                         };
 134                 };
 135
 136                 dsp-iobg {
 137                         compatible = "simple-bus";
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 141
 142                         dspif@a8000000 {
 143                                 compatible = "sirf,prima2-dspif";
 144                                 reg = <0xa8000000 0x10000>;
 145                                 interrupts = <9>;
 146                         };
 147
 148                         gps@a8010000 {
 149                                 compatible = "sirf,prima2-gps";
 150                                 reg = <0xa8010000 0x10000>;
 151                                 interrupts = <7>;
 152                         };
 153
 154                         dsp@a9000000 {
 155                                 compatible = "sirf,prima2-dsp";
 156                                 reg = <0xa9000000 0x1000000>;
 157                                 interrupts = <8>;
 158                         };
 159                 };
 160
 161                 peri-iobg {
 162                         compatible = "simple-bus";
 163                         #address-cells = <1>;
 164                         #size-cells = <1>;
 165                         ranges = <0xb0000000 0xb0000000 0x180000>;
 166
 167                         timer@b0020000 {
 168                                 compatible = "sirf,prima2-tick";
 169                                 reg = <0xb0020000 0x1000>;
 170                                 interrupts = <0>;
 171                         };
 172
 173                         nand@b0030000 {
 174                                 compatible = "sirf,prima2-nand";
 175                                 reg = <0xb0030000 0x10000>;
 176                                 interrupts = <41>;
 177                         };
 178
 179                         audio@b0040000 {
 180                                 compatible = "sirf,prima2-audio";
 181                                 reg = <0xb0040000 0x10000>;
 182                                 interrupts = <35>;
 183                         };
 184
 185                         uart0: uart@b0050000 {
 186                                 cell-index = <0>;
 187                                 compatible = "sirf,prima2-uart";
 188                                 reg = <0xb0050000 0x10000>;
 189                                 interrupts = <17>;
 190                         };
 191
 192                         uart1: uart@b0060000 {
 193                                 cell-index = <1>;
 194                                 compatible = "sirf,prima2-uart";
 195                                 reg = <0xb0060000 0x10000>;
 196                                 interrupts = <18>;
 197                         };
 198
 199                         uart2: uart@b0070000 {
 200                                 cell-index = <2>;
 201                                 compatible = "sirf,prima2-uart";
 202                                 reg = <0xb0070000 0x10000>;
 203                                 interrupts = <19>;
 204                         };
 205
 206                         usp0: usp@b0080000 {
 207                                 cell-index = <0>;
 208                                 compatible = "sirf,prima2-usp";
 209                                 reg = <0xb0080000 0x10000>;
 210                                 interrupts = <20>;
 211                         };
 212
 213                         usp1: usp@b0090000 {
 214                                 cell-index = <1>;
 215                                 compatible = "sirf,prima2-usp";
 216                                 reg = <0xb0090000 0x10000>;
 217                                 interrupts = <21>;
 218                         };
 219
 220                         usp2: usp@b00a0000 {
 221                                 cell-index = <2>;
 222                                 compatible = "sirf,prima2-usp";
 223                                 reg = <0xb00a0000 0x10000>;
 224                                 interrupts = <22>;
 225                         };
 226
 227                         dmac0: dma-controller@b00b0000 {
 228                                 cell-index = <0>;
 229                                 compatible = "sirf,prima2-dmac";
 230                                 reg = <0xb00b0000 0x10000>;
 231                                 interrupts = <12>;
 232                         };
 233
 234                         dmac1: dma-controller@b0160000 {
 235                                 cell-index = <1>;
 236                                 compatible = "sirf,prima2-dmac";
 237                                 reg = <0xb0160000 0x10000>;
 238                                 interrupts = <13>;
 239                         };
 240
 241                         vip@b00C0000 {
 242                                 compatible = "sirf,prima2-vip";
 243                                 reg = <0xb00C0000 0x10000>;
 244                         };
 245
 246                         spi0: spi@b00d0000 {
 247                                 cell-index = <0>;
 248                                 compatible = "sirf,prima2-spi";
 249                                 reg = <0xb00d0000 0x10000>;
 250                                 interrupts = <15>;
 251                         };
 252
 253                         spi1: spi@b0170000 {
 254                                 cell-index = <1>;
 255                                 compatible = "sirf,prima2-spi";
 256                                 reg = <0xb0170000 0x10000>;
 257                                 interrupts = <16>;
 258                         };
 259
 260                         i2c0: i2c@b00e0000 {
 261                                 cell-index = <0>;
 262                                 compatible = "sirf,prima2-i2c";
 263                                 reg = <0xb00e0000 0x10000>;
 264                                 interrupts = <24>;
 265                         };
 266
 267                         i2c1: i2c@b00f0000 {
 268                                 cell-index = <1>;
 269                                 compatible = "sirf,prima2-i2c";
 270                                 reg = <0xb00f0000 0x10000>;
 271                                 interrupts = <25>;
 272                         };
 273
 274                         tsc@b0110000 {
 275                                 compatible = "sirf,prima2-tsc";
 276                                 reg = <0xb0110000 0x10000>;
 277                                 interrupts = <33>;
 278                         };
 279
 280                         gpio: pinctrl@b0120000 {
 281                                 #gpio-cells = <2>;
 282                                 #interrupt-cells = <2>;
 283                                 compatible = "sirf,prima2-pinctrl";
 284                                 reg = <0xb0120000 0x10000>;
 285                                 interrupts = <43 44 45 46 47>;
 286                                 gpio-controller;
 287                                 interrupt-controller;
 288
 289                                 lcd_16pins_a: lcd0@0 {
 290                                         lcd {
 291                                                 sirf,pins = "lcd_16bitsgrp";
 292                                                 sirf,function = "lcd_16bits";
 293                                         };
 294                                 };
 295                                 lcd_18pins_a: lcd0@1 {
 296                                         lcd {
 297                                                 sirf,pins = "lcd_18bitsgrp";
 298                                                 sirf,function = "lcd_18bits";
 299                                         };
 300                                 };
 301                                 lcd_24pins_a: lcd0@2 {
 302                                         lcd {
 303                                                 sirf,pins = "lcd_24bitsgrp";
 304                                                 sirf,function = "lcd_24bits";
 305                                         };
 306                                 };
 307                                 lcdrom_pins_a: lcdrom0@0 {
 308                                         lcd {
 309                                                 sirf,pins = "lcdromgrp";
 310                                                 sirf,function = "lcdrom";
 311                                         };
 312                                 };
 313                                 uart0_pins_a: uart0@0 {
 314                                         uart {
 315                                                 sirf,pins = "uart0grp";
 316                                                 sirf,function = "uart0";
 317                                         };
 318                                 };
 319                                 uart1_pins_a: uart1@0 {
 320                                         uart {
 321                                                 sirf,pins = "uart1grp";
 322                                                 sirf,function = "uart1";
 323                                         };
 324                                 };
 325                                 uart2_pins_a: uart2@0 {
 326                                         uart {
 327                                                 sirf,pins = "uart2grp";
 328                                                 sirf,function = "uart2";
 329                                         };
 330                                 };
 331                                 uart2_noflow_pins_a: uart2@1 {
 332                                         uart {
 333                                                 sirf,pins = "uart2_nostreamctrlgrp";
 334                                                 sirf,function = "uart2_nostreamctrl";
 335                                         };
 336                                 };
 337                                 spi0_pins_a: spi0@0 {
 338                                         spi {
 339                                                 sirf,pins = "spi0grp";
 340                                                 sirf,function = "spi0";
 341                                         };
 342                                 };
 343                                 spi1_pins_a: spi1@0 {
 344                                         spi {
 345                                                 sirf,pins = "spi1grp";
 346                                                 sirf,function = "spi1";
 347                                         };
 348                                 };
 349                                 i2c0_pins_a: i2c0@0 {
 350                                         i2c {
 351                                                 sirf,pins = "i2c0grp";
 352                                                 sirf,function = "i2c0";
 353                                         };
 354                                 };
 355                                 i2c1_pins_a: i2c1@0 {
 356                                         i2c {
 357                                                 sirf,pins = "i2c1grp";
 358                                                 sirf,function = "i2c1";
 359                                         };
 360                                 };
 361                                 pwm0_pins_a: pwm0@0 {
 362                                         pwm {
 363                                                 sirf,pins = "pwm0grp";
 364                                                 sirf,function = "pwm0";
 365                                         };
 366                                 };
 367                                 pwm1_pins_a: pwm1@0 {
 368                                         pwm {
 369                                                 sirf,pins = "pwm1grp";
 370                                                 sirf,function = "pwm1";
 371                                         };
 372                                 };
 373                                 pwm2_pins_a: pwm2@0 {
 374                                         pwm {
 375                                                 sirf,pins = "pwm2grp";
 376                                                 sirf,function = "pwm2";
 377                                         };
 378                                 };
 379                                 pwm3_pins_a: pwm3@0 {
 380                                         pwm {
 381                                                 sirf,pins = "pwm3grp";
 382                                                 sirf,function = "pwm3";
 383                                         };
 384                                 };
 385                                 gps_pins_a: gps@0 {
 386                                         gps {
 387                                                 sirf,pins = "gpsgrp";
 388                                                 sirf,function = "gps";
 389                                         };
 390                                 };
 391                                 vip_pins_a: vip@0 {
 392                                         vip {
 393                                                 sirf,pins = "vipgrp";
 394                                                 sirf,function = "vip";
 395                                         };
 396                                 };
 397                                 sdmmc0_pins_a: sdmmc0@0 {
 398                                         sdmmc0 {
 399                                                 sirf,pins = "sdmmc0grp";
 400                                                 sirf,function = "sdmmc0";
 401                                         };
 402                                 };
 403                                 sdmmc1_pins_a: sdmmc1@0 {
 404                                         sdmmc1 {
 405                                                 sirf,pins = "sdmmc1grp";
 406                                                 sirf,function = "sdmmc1";
 407                                         };
 408                                 };
 409                                 sdmmc2_pins_a: sdmmc2@0 {
 410                                         sdmmc2 {
 411                                                 sirf,pins = "sdmmc2grp";
 412                                                 sirf,function = "sdmmc2";
 413                                         };
 414                                 };
 415                                 sdmmc3_pins_a: sdmmc3@0 {
 416                                         sdmmc3 {
 417                                                 sirf,pins = "sdmmc3grp";
 418                                                 sirf,function = "sdmmc3";
 419                                         };
 420                                 };
 421                                 sdmmc4_pins_a: sdmmc4@0 {
 422                                         sdmmc4 {
 423                                                 sirf,pins = "sdmmc4grp";
 424                                                 sirf,function = "sdmmc4";
 425                                         };
 426                                 };
 427                                 sdmmc5_pins_a: sdmmc5@0 {
 428                                         sdmmc5 {
 429                                                 sirf,pins = "sdmmc5grp";
 430                                                 sirf,function = "sdmmc5";
 431                                         };
 432                                 };
 433                                 i2s_pins_a: i2s@0 {
 434                                         i2s {
 435                                                 sirf,pins = "i2sgrp";
 436                                                 sirf,function = "i2s";
 437                                         };
 438                                 };
 439                                 ac97_pins_a: ac97@0 {
 440                                         ac97 {
 441                                                 sirf,pins = "ac97grp";
 442                                                 sirf,function = "ac97";
 443                                         };
 444                                 };
 445                                 nand_pins_a: nand@0 {
 446                                         nand {
 447                                                 sirf,pins = "nandgrp";
 448                                                 sirf,function = "nand";
 449                                         };
 450                                 };
 451                                 usp0_pins_a: usp0@0 {
 452                                         usp0 {
 453                                                 sirf,pins = "usp0grp";
 454                                                 sirf,function = "usp0";
 455                                         };
 456                                 };
 457                                 usp1_pins_a: usp1@0 {
 458                                         usp1 {
 459                                                 sirf,pins = "usp1grp";
 460                                                 sirf,function = "usp1";
 461                                         };
 462                                 };
 463                                 usp2_pins_a: usp2@0 {
 464                                         usp2 {
 465                                                 sirf,pins = "usp2grp";
 466                                                 sirf,function = "usp2";
 467                                         };
 468                                 };
 469                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 470                                         usb0_utmi_drvbus {
 471                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 472                                                 sirf,function = "usb0_utmi_drvbus";
 473                                         };
 474                                 };
 475                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 476                                         usb1_utmi_drvbus {
 477                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 478                                                 sirf,function = "usb1_utmi_drvbus";
 479                                         };
 480                                 };
 481                                 warm_rst_pins_a: warm_rst@0 {
 482                                         warm_rst {
 483                                                 sirf,pins = "warm_rstgrp";
 484                                                 sirf,function = "warm_rst";
 485                                         };
 486                                 };
 487                                 pulse_count_pins_a: pulse_count@0 {
 488                                         pulse_count {
 489                                                 sirf,pins = "pulse_countgrp";
 490                                                 sirf,function = "pulse_count";
 491                                         };
 492                                 };
 493                                 cko0_rst_pins_a: cko0_rst@0 {
 494                                         cko0_rst {
 495                                                 sirf,pins = "cko0_rstgrp";
 496                                                 sirf,function = "cko0_rst";
 497                                         };
 498                                 };
 499                                 cko1_rst_pins_a: cko1_rst@0 {
 500                                         cko1_rst {
 501                                                 sirf,pins = "cko1_rstgrp";
 502                                                 sirf,function = "cko1_rst";
 503                                         };
 504                                 };
 505                         };
 506
 507                         pwm@b0130000 {
 508                                 compatible = "sirf,prima2-pwm";
 509                                 reg = <0xb0130000 0x10000>;
 510                         };
 511
 512                         efusesys@b0140000 {
 513                                 compatible = "sirf,prima2-efuse";
 514                                 reg = <0xb0140000 0x10000>;
 515                         };
 516
 517                         pulsec@b0150000 {
 518                                 compatible = "sirf,prima2-pulsec";
 519                                 reg = <0xb0150000 0x10000>;
 520                                 interrupts = <48>;
 521                         };
 522
 523                         pci-iobg {
 524                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 525                                 #address-cells = <1>;
 526                                 #size-cells = <1>;
 527                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 528
 529                                 sd0: sdhci@56000000 {
 530                                         cell-index = <0>;
 531                                         compatible = "sirf,prima2-sdhc";
 532                                         reg = <0x56000000 0x100000>;
 533                                         interrupts = <38>;
 534                                 };
 535
 536                                 sd1: sdhci@56100000 {
 537                                         cell-index = <1>;
 538                                         compatible = "sirf,prima2-sdhc";
 539                                         reg = <0x56100000 0x100000>;
 540                                         interrupts = <38>;
 541                                 };
 542
 543                                 sd2: sdhci@56200000 {
 544                                         cell-index = <2>;
 545                                         compatible = "sirf,prima2-sdhc";
 546                                         reg = <0x56200000 0x100000>;
 547                                         interrupts = <23>;
 548                                 };
 549
 550                                 sd3: sdhci@56300000 {
 551                                         cell-index = <3>;
 552                                         compatible = "sirf,prima2-sdhc";
 553                                         reg = <0x56300000 0x100000>;
 554                                         interrupts = <23>;
 555                                 };
 556
 557                                 sd4: sdhci@56400000 {
 558                                         cell-index = <4>;
 559                                         compatible = "sirf,prima2-sdhc";
 560                                         reg = <0x56400000 0x100000>;
 561                                         interrupts = <39>;
 562                                 };
 563
 564                                 sd5: sdhci@56500000 {
 565                                         cell-index = <5>;
 566                                         compatible = "sirf,prima2-sdhc";
 567                                         reg = <0x56500000 0x100000>;
 568                                         interrupts = <39>;
 569                                 };
 570
 571                                 pci-copy@57900000 {
 572                                         compatible = "sirf,prima2-pcicp";
 573                                         reg = <0x57900000 0x100000>;
 574                                         interrupts = <40>;
 575                                 };
 576
 577                                 rom-interface@57a00000 {
 578                                         compatible = "sirf,prima2-romif";
 579                                         reg = <0x57a00000 0x100000>;
 580                                 };
 581                         };
 582                 };
 583
 584                 rtc-iobg {
 585                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
 586                         #address-cells = <1>;
 587                         #size-cells = <1>;
 588                         reg = <0x80030000 0x10000>;
 589
 590                         gpsrtc@1000 {
 591                                 compatible = "sirf,prima2-gpsrtc";
 592                                 reg = <0x1000 0x1000>;
 593                                 interrupts = <55 56 57>;
 594                         };
 595
 596                         sysrtc@2000 {
 597                                 compatible = "sirf,prima2-sysrtc";
 598                                 reg = <0x2000 0x1000>;
 599                                 interrupts = <52 53 54>;
 600                         };
 601
 602                         pwrc@3000 {
 603                                 compatible = "sirf,prima2-pwrc";
 604                                 reg = <0x3000 0x1000>;
 605                                 interrupts = <32>;
 606                         };
 607                 };
 608
 609                 uus-iobg {
 610                         compatible = "simple-bus";
 611                         #address-cells = <1>;
 612                         #size-cells = <1>;
 613                         ranges = <0xb8000000 0xb8000000 0x40000>;
 614
 615                         usb0: usb@b00e0000 {
 616                                 compatible = "chipidea,ci13611a-prima2";
 617                                 reg = <0xb8000000 0x10000>;
 618                                 interrupts = <10>;
 619                         };
 620
 621                         usb1: usb@b00f0000 {
 622                                 compatible = "chipidea,ci13611a-prima2";
 623                                 reg = <0xb8010000 0x10000>;
 624                                 interrupts = <11>;
 625                         };
 626
 627                         sata@b00f0000 {
 628                                 compatible = "synopsys,dwc-ahsata";
 629                                 reg = <0xb8020000 0x10000>;
 630                                 interrupts = <37>;
 631                         };
 632
 633                         security@b00f0000 {
 634                                 compatible = "sirf,prima2-security";
 635                                 reg = <0xb8030000 0x10000>;
 636                                 interrupts = <42>;
 637                         };
 638                 };
 639         };
 640 };