arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&wakeupgen>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,cortex-a15-pmu";
  87                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  89         };
  90
  91         gic: interrupt-controller@48211000 {
  92                 compatible = "arm,cortex-a15-gic";
  93                 interrupt-controller;
  94                 #interrupt-cells = <3>;
  95                 reg = <0x48211000 0x1000>,
  96                       <0x48212000 0x1000>,
  97                       <0x48214000 0x2000>,
  98                       <0x48216000 0x2000>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         wakeupgen: interrupt-controller@48281000 {
 103                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0x48281000 0x1000>;
 107                 interrupt-parent = <&gic>;
 108         };
 109
 110         /*
 111          * The soc node represents the soc top level view. It is used for IPs
 112          * that are not memory mapped in the MPU view or for the MPU itself.
 113          */
 114         soc {
 115                 compatible = "ti,omap-infra";
 116                 mpu {
 117                         compatible = "ti,omap4-mpu";
 118                         ti,hwmods = "mpu";
 119                         sram = <&ocmcram>;
 120                 };
 121         };
 122
 123         /*
 124          * XXX: Use a flat representation of the OMAP3 interconnect.
 125          * The real OMAP interconnect network is quite complex.
 126          * Since it will not bring real advantage to represent that in DT for
 127          * the moment, just use a fake OCP bus entry to represent the whole bus
 128          * hierarchy.
 129          */
 130         ocp {
 131                 compatible = "ti,omap5-l3-noc", "simple-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 136                 reg = <0x44000000 0x2000>,
 137                       <0x44800000 0x3000>,
 138                       <0x45000000 0x4000>;
 139                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 141
 142                 l4_cfg: l4@4a000000 {
 143                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0 0x4a000000 0x22a000>;
 147
 148                         scm_core: scm@2000 {
 149                                 compatible = "ti,omap5-scm-core", "simple-bus";
 150                                 reg = <0x2000 0x1000>;
 151                                 #address-cells = <1>;
 152                                 #size-cells = <1>;
 153                                 ranges = <0 0x2000 0x800>;
 154
 155                                 scm_conf: scm_conf@0 {
 156                                         compatible = "syscon";
 157                                         reg = <0x0 0x800>;
 158                                         #address-cells = <1>;
 159                                         #size-cells = <1>;
 160                                 };
 161                         };
 162
 163                         scm_padconf_core: scm@2800 {
 164                                 compatible = "ti,omap5-scm-padconf-core",
 165                                              "simple-bus";
 166                                 #address-cells = <1>;
 167                                 #size-cells = <1>;
 168                                 ranges = <0 0x2800 0x800>;
 169
 170                                 omap5_pmx_core: pinmux@40 {
 171                                         compatible = "ti,omap5-padconf",
 172                                                      "pinctrl-single";
 173                                         reg = <0x40 0x01b6>;
 174                                         #address-cells = <1>;
 175                                         #size-cells = <0>;
 176                                         #interrupt-cells = <1>;
 177                                         interrupt-controller;
 178                                         pinctrl-single,register-width = <16>;
 179                                         pinctrl-single,function-mask = <0x7fff>;
 180                                 };
 181
 182                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 183                                         compatible = "syscon",
 184                                                      "simple-bus";
 185                                         reg = <0x5a0 0xec>;
 186                                         #address-cells = <1>;
 187                                         #size-cells = <1>;
 188                                         ranges = <0 0x5a0 0xec>;
 189
 190                                         pbias_regulator: pbias_regulator@60 {
 191                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 192                                                 reg = <0x60 0x4>;
 193                                                 syscon = <&omap5_padconf_global>;
 194                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 195                                                         regulator-name = "pbias_mmc_omap5";
 196                                                         regulator-min-microvolt = <1800000>;
 197                                                         regulator-max-microvolt = <3000000>;
 198                                                 };
 199                                         };
 200                                 };
 201                         };
 202
 203                         cm_core_aon: cm_core_aon@4000 {
 204                                 compatible = "ti,omap5-cm-core-aon";
 205                                 reg = <0x4000 0x2000>;
 206
 207                                 cm_core_aon_clocks: clocks {
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210                                 };
 211
 212                                 cm_core_aon_clockdomains: clockdomains {
 213                                 };
 214                         };
 215
 216                         cm_core: cm_core@8000 {
 217                                 compatible = "ti,omap5-cm-core";
 218                                 reg = <0x8000 0x3000>;
 219
 220                                 cm_core_clocks: clocks {
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                 };
 224
 225                                 cm_core_clockdomains: clockdomains {
 226                                 };
 227                         };
 228                 };
 229
 230                 l4_wkup: l4@4ae00000 {
 231                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         ranges = <0 0x4ae00000 0x2b000>;
 235
 236                         counter32k: counter@4000 {
 237                                 compatible = "ti,omap-counter32k";
 238                                 reg = <0x4000 0x40>;
 239                                 ti,hwmods = "counter_32k";
 240                         };
 241
 242                         prm: prm@6000 {
 243                                 compatible = "ti,omap5-prm";
 244                                 reg = <0x6000 0x3000>;
 245                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 246
 247                                 prm_clocks: clocks {
 248                                         #address-cells = <1>;
 249                                         #size-cells = <0>;
 250                                 };
 251
 252                                 prm_clockdomains: clockdomains {
 253                                 };
 254                         };
 255
 256                         scrm: scrm@a000 {
 257                                 compatible = "ti,omap5-scrm";
 258                                 reg = <0xa000 0x2000>;
 259
 260                                 scrm_clocks: clocks {
 261                                         #address-cells = <1>;
 262                                         #size-cells = <0>;
 263                                 };
 264
 265                                 scrm_clockdomains: clockdomains {
 266                                 };
 267                         };
 268
 269                         omap5_pmx_wkup: pinmux@c840 {
 270                                 compatible = "ti,omap5-padconf",
 271                                              "pinctrl-single";
 272                                 reg = <0xc840 0x0038>;
 273                                 #address-cells = <1>;
 274                                 #size-cells = <0>;
 275                                 #interrupt-cells = <1>;
 276                                 interrupt-controller;
 277                                 pinctrl-single,register-width = <16>;
 278                                 pinctrl-single,function-mask = <0x7fff>;
 279                         };
 280                 };
 281
 282                 ocmcram: ocmcram@40300000 {
 283                         compatible = "mmio-sram";
 284                         reg = <0x40300000 0x20000>; /* 128k */
 285                 };
 286
 287                 sdma: dma-controller@4a056000 {
 288                         compatible = "ti,omap4430-sdma";
 289                         reg = <0x4a056000 0x1000>;
 290                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 294                         #dma-cells = <1>;
 295                         dma-channels = <32>;
 296                         dma-requests = <127>;
 297                 };
 298
 299                 gpio1: gpio@4ae10000 {
 300                         compatible = "ti,omap4-gpio";
 301                         reg = <0x4ae10000 0x200>;
 302                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 303                         ti,hwmods = "gpio1";
 304                         ti,gpio-always-on;
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                         interrupt-controller;
 308                         #interrupt-cells = <2>;
 309                 };
 310
 311                 gpio2: gpio@48055000 {
 312                         compatible = "ti,omap4-gpio";
 313                         reg = <0x48055000 0x200>;
 314                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 315                         ti,hwmods = "gpio2";
 316                         gpio-controller;
 317                         #gpio-cells = <2>;
 318                         interrupt-controller;
 319                         #interrupt-cells = <2>;
 320                 };
 321
 322                 gpio3: gpio@48057000 {
 323                         compatible = "ti,omap4-gpio";
 324                         reg = <0x48057000 0x200>;
 325                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 326                         ti,hwmods = "gpio3";
 327                         gpio-controller;
 328                         #gpio-cells = <2>;
 329                         interrupt-controller;
 330                         #interrupt-cells = <2>;
 331                 };
 332
 333                 gpio4: gpio@48059000 {
 334                         compatible = "ti,omap4-gpio";
 335                         reg = <0x48059000 0x200>;
 336                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 337                         ti,hwmods = "gpio4";
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343
 344                 gpio5: gpio@4805b000 {
 345                         compatible = "ti,omap4-gpio";
 346                         reg = <0x4805b000 0x200>;
 347                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 348                         ti,hwmods = "gpio5";
 349                         gpio-controller;
 350                         #gpio-cells = <2>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                 };
 354
 355                 gpio6: gpio@4805d000 {
 356                         compatible = "ti,omap4-gpio";
 357                         reg = <0x4805d000 0x200>;
 358                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 359                         ti,hwmods = "gpio6";
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         interrupt-controller;
 363                         #interrupt-cells = <2>;
 364                 };
 365
 366                 gpio7: gpio@48051000 {
 367                         compatible = "ti,omap4-gpio";
 368                         reg = <0x48051000 0x200>;
 369                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 370                         ti,hwmods = "gpio7";
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                 };
 376
 377                 gpio8: gpio@48053000 {
 378                         compatible = "ti,omap4-gpio";
 379                         reg = <0x48053000 0x200>;
 380                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 381                         ti,hwmods = "gpio8";
 382                         gpio-controller;
 383                         #gpio-cells = <2>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                 };
 387
 388                 gpmc: gpmc@50000000 {
 389                         compatible = "ti,omap4430-gpmc";
 390                         reg = <0x50000000 0x1000>;
 391                         #address-cells = <2>;
 392                         #size-cells = <1>;
 393                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 394                         dmas = <&sdma 4>;
 395                         dma-names = "rxtx";
 396                         gpmc,num-cs = <8>;
 397                         gpmc,num-waitpins = <4>;
 398                         ti,hwmods = "gpmc";
 399                         clocks = <&l3_iclk_div>;
 400                         clock-names = "fck";
 401                         interrupt-controller;
 402                         #interrupt-cells = <2>;
 403                         gpio-controller;
 404                         #gpio-cells = <2>;
 405                 };
 406
 407                 i2c1: i2c@48070000 {
 408                         compatible = "ti,omap4-i2c";
 409                         reg = <0x48070000 0x100>;
 410                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         ti,hwmods = "i2c1";
 414                 };
 415
 416                 i2c2: i2c@48072000 {
 417                         compatible = "ti,omap4-i2c";
 418                         reg = <0x48072000 0x100>;
 419                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         ti,hwmods = "i2c2";
 423                 };
 424
 425                 i2c3: i2c@48060000 {
 426                         compatible = "ti,omap4-i2c";
 427                         reg = <0x48060000 0x100>;
 428                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         ti,hwmods = "i2c3";
 432                 };
 433
 434                 i2c4: i2c@4807a000 {
 435                         compatible = "ti,omap4-i2c";
 436                         reg = <0x4807a000 0x100>;
 437                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         ti,hwmods = "i2c4";
 441                 };
 442
 443                 i2c5: i2c@4807c000 {
 444                         compatible = "ti,omap4-i2c";
 445                         reg = <0x4807c000 0x100>;
 446                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         ti,hwmods = "i2c5";
 450                 };
 451
 452                 hwspinlock: spinlock@4a0f6000 {
 453                         compatible = "ti,omap4-hwspinlock";
 454                         reg = <0x4a0f6000 0x1000>;
 455                         ti,hwmods = "spinlock";
 456                         #hwlock-cells = <1>;
 457                 };
 458
 459                 mcspi1: spi@48098000 {
 460                         compatible = "ti,omap4-mcspi";
 461                         reg = <0x48098000 0x200>;
 462                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         ti,hwmods = "mcspi1";
 466                         ti,spi-num-cs = <4>;
 467                         dmas = <&sdma 35>,
 468                                <&sdma 36>,
 469                                <&sdma 37>,
 470                                <&sdma 38>,
 471                                <&sdma 39>,
 472                                <&sdma 40>,
 473                                <&sdma 41>,
 474                                <&sdma 42>;
 475                         dma-names = "tx0", "rx0", "tx1", "rx1",
 476                                     "tx2", "rx2", "tx3", "rx3";
 477                 };
 478
 479                 mcspi2: spi@4809a000 {
 480                         compatible = "ti,omap4-mcspi";
 481                         reg = <0x4809a000 0x200>;
 482                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         ti,hwmods = "mcspi2";
 486                         ti,spi-num-cs = <2>;
 487                         dmas = <&sdma 43>,
 488                                <&sdma 44>,
 489                                <&sdma 45>,
 490                                <&sdma 46>;
 491                         dma-names = "tx0", "rx0", "tx1", "rx1";
 492                 };
 493
 494                 mcspi3: spi@480b8000 {
 495                         compatible = "ti,omap4-mcspi";
 496                         reg = <0x480b8000 0x200>;
 497                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         ti,hwmods = "mcspi3";
 501                         ti,spi-num-cs = <2>;
 502                         dmas = <&sdma 15>, <&sdma 16>;
 503                         dma-names = "tx0", "rx0";
 504                 };
 505
 506                 mcspi4: spi@480ba000 {
 507                         compatible = "ti,omap4-mcspi";
 508                         reg = <0x480ba000 0x200>;
 509                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         ti,hwmods = "mcspi4";
 513                         ti,spi-num-cs = <1>;
 514                         dmas = <&sdma 70>, <&sdma 71>;
 515                         dma-names = "tx0", "rx0";
 516                 };
 517
 518                 uart1: serial@4806a000 {
 519                         compatible = "ti,omap4-uart";
 520                         reg = <0x4806a000 0x100>;
 521                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 522                         ti,hwmods = "uart1";
 523                         clock-frequency = <48000000>;
 524                 };
 525
 526                 uart2: serial@4806c000 {
 527                         compatible = "ti,omap4-uart";
 528                         reg = <0x4806c000 0x100>;
 529                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 530                         ti,hwmods = "uart2";
 531                         clock-frequency = <48000000>;
 532                 };
 533
 534                 uart3: serial@48020000 {
 535                         compatible = "ti,omap4-uart";
 536                         reg = <0x48020000 0x100>;
 537                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 538                         ti,hwmods = "uart3";
 539                         clock-frequency = <48000000>;
 540                 };
 541
 542                 uart4: serial@4806e000 {
 543                         compatible = "ti,omap4-uart";
 544                         reg = <0x4806e000 0x100>;
 545                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 546                         ti,hwmods = "uart4";
 547                         clock-frequency = <48000000>;
 548                 };
 549
 550                 uart5: serial@48066000 {
 551                         compatible = "ti,omap4-uart";
 552                         reg = <0x48066000 0x100>;
 553                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 554                         ti,hwmods = "uart5";
 555                         clock-frequency = <48000000>;
 556                 };
 557
 558                 uart6: serial@48068000 {
 559                         compatible = "ti,omap4-uart";
 560                         reg = <0x48068000 0x100>;
 561                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "uart6";
 563                         clock-frequency = <48000000>;
 564                 };
 565
 566                 mmc1: mmc@4809c000 {
 567                         compatible = "ti,omap4-hsmmc";
 568                         reg = <0x4809c000 0x400>;
 569                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 570                         ti,hwmods = "mmc1";
 571                         ti,dual-volt;
 572                         ti,needs-special-reset;
 573                         dmas = <&sdma 61>, <&sdma 62>;
 574                         dma-names = "tx", "rx";
 575                         pbias-supply = <&pbias_mmc_reg>;
 576                 };
 577
 578                 mmc2: mmc@480b4000 {
 579                         compatible = "ti,omap4-hsmmc";
 580                         reg = <0x480b4000 0x400>;
 581                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 582                         ti,hwmods = "mmc2";
 583                         ti,needs-special-reset;
 584                         dmas = <&sdma 47>, <&sdma 48>;
 585                         dma-names = "tx", "rx";
 586                 };
 587
 588                 mmc3: mmc@480ad000 {
 589                         compatible = "ti,omap4-hsmmc";
 590                         reg = <0x480ad000 0x400>;
 591                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 592                         ti,hwmods = "mmc3";
 593                         ti,needs-special-reset;
 594                         dmas = <&sdma 77>, <&sdma 78>;
 595                         dma-names = "tx", "rx";
 596                 };
 597
 598                 mmc4: mmc@480d1000 {
 599                         compatible = "ti,omap4-hsmmc";
 600                         reg = <0x480d1000 0x400>;
 601                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 602                         ti,hwmods = "mmc4";
 603                         ti,needs-special-reset;
 604                         dmas = <&sdma 57>, <&sdma 58>;
 605                         dma-names = "tx", "rx";
 606                 };
 607
 608                 mmc5: mmc@480d5000 {
 609                         compatible = "ti,omap4-hsmmc";
 610                         reg = <0x480d5000 0x400>;
 611                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 612                         ti,hwmods = "mmc5";
 613                         ti,needs-special-reset;
 614                         dmas = <&sdma 59>, <&sdma 60>;
 615                         dma-names = "tx", "rx";
 616                 };
 617
 618                 mmu_dsp: mmu@4a066000 {
 619                         compatible = "ti,omap4-iommu";
 620                         reg = <0x4a066000 0x100>;
 621                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 622                         ti,hwmods = "mmu_dsp";
 623                         #iommu-cells = <0>;
 624                 };
 625
 626                 mmu_ipu: mmu@55082000 {
 627                         compatible = "ti,omap4-iommu";
 628                         reg = <0x55082000 0x100>;
 629                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 630                         ti,hwmods = "mmu_ipu";
 631                         #iommu-cells = <0>;
 632                         ti,iommu-bus-err-back;
 633                 };
 634
 635                 keypad: keypad@4ae1c000 {
 636                         compatible = "ti,omap4-keypad";
 637                         reg = <0x4ae1c000 0x400>;
 638                         ti,hwmods = "kbd";
 639                 };
 640
 641                 mcpdm: mcpdm@40132000 {
 642                         compatible = "ti,omap4-mcpdm";
 643                         reg = <0x40132000 0x7f>, /* MPU private access */
 644                               <0x49032000 0x7f>; /* L3 Interconnect */
 645                         reg-names = "mpu", "dma";
 646                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 647                         ti,hwmods = "mcpdm";
 648                         dmas = <&sdma 65>,
 649                                <&sdma 66>;
 650                         dma-names = "up_link", "dn_link";
 651                         status = "disabled";
 652                 };
 653
 654                 dmic: dmic@4012e000 {
 655                         compatible = "ti,omap4-dmic";
 656                         reg = <0x4012e000 0x7f>, /* MPU private access */
 657                               <0x4902e000 0x7f>; /* L3 Interconnect */
 658                         reg-names = "mpu", "dma";
 659                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "dmic";
 661                         dmas = <&sdma 67>;
 662                         dma-names = "up_link";
 663                         status = "disabled";
 664                 };
 665
 666                 mcbsp1: mcbsp@40122000 {
 667                         compatible = "ti,omap4-mcbsp";
 668                         reg = <0x40122000 0xff>, /* MPU private access */
 669                               <0x49022000 0xff>; /* L3 Interconnect */
 670                         reg-names = "mpu", "dma";
 671                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 672                         interrupt-names = "common";
 673                         ti,buffer-size = <128>;
 674                         ti,hwmods = "mcbsp1";
 675                         dmas = <&sdma 33>,
 676                                <&sdma 34>;
 677                         dma-names = "tx", "rx";
 678                         status = "disabled";
 679                 };
 680
 681                 mcbsp2: mcbsp@40124000 {
 682                         compatible = "ti,omap4-mcbsp";
 683                         reg = <0x40124000 0xff>, /* MPU private access */
 684                               <0x49024000 0xff>; /* L3 Interconnect */
 685                         reg-names = "mpu", "dma";
 686                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 687                         interrupt-names = "common";
 688                         ti,buffer-size = <128>;
 689                         ti,hwmods = "mcbsp2";
 690                         dmas = <&sdma 17>,
 691                                <&sdma 18>;
 692                         dma-names = "tx", "rx";
 693                         status = "disabled";
 694                 };
 695
 696                 mcbsp3: mcbsp@40126000 {
 697                         compatible = "ti,omap4-mcbsp";
 698                         reg = <0x40126000 0xff>, /* MPU private access */
 699                               <0x49026000 0xff>; /* L3 Interconnect */
 700                         reg-names = "mpu", "dma";
 701                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 702                         interrupt-names = "common";
 703                         ti,buffer-size = <128>;
 704                         ti,hwmods = "mcbsp3";
 705                         dmas = <&sdma 19>,
 706                                <&sdma 20>;
 707                         dma-names = "tx", "rx";
 708                         status = "disabled";
 709                 };
 710
 711                 mailbox: mailbox@4a0f4000 {
 712                         compatible = "ti,omap4-mailbox";
 713                         reg = <0x4a0f4000 0x200>;
 714                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 715                         ti,hwmods = "mailbox";
 716                         #mbox-cells = <1>;
 717                         ti,mbox-num-users = <3>;
 718                         ti,mbox-num-fifos = <8>;
 719                         mbox_ipu: mbox_ipu {
 720                                 ti,mbox-tx = <0 0 0>;
 721                                 ti,mbox-rx = <1 0 0>;
 722                         };
 723                         mbox_dsp: mbox_dsp {
 724                                 ti,mbox-tx = <3 0 0>;
 725                                 ti,mbox-rx = <2 0 0>;
 726                         };
 727                 };
 728
 729                 timer1: timer@4ae18000 {
 730                         compatible = "ti,omap5430-timer";
 731                         reg = <0x4ae18000 0x80>;
 732                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 733                         ti,hwmods = "timer1";
 734                         ti,timer-alwon;
 735                 };
 736
 737                 timer2: timer@48032000 {
 738                         compatible = "ti,omap5430-timer";
 739                         reg = <0x48032000 0x80>;
 740                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 741                         ti,hwmods = "timer2";
 742                 };
 743
 744                 timer3: timer@48034000 {
 745                         compatible = "ti,omap5430-timer";
 746                         reg = <0x48034000 0x80>;
 747                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "timer3";
 749                 };
 750
 751                 timer4: timer@48036000 {
 752                         compatible = "ti,omap5430-timer";
 753                         reg = <0x48036000 0x80>;
 754                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 755                         ti,hwmods = "timer4";
 756                 };
 757
 758                 timer5: timer@40138000 {
 759                         compatible = "ti,omap5430-timer";
 760                         reg = <0x40138000 0x80>,
 761                               <0x49038000 0x80>;
 762                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "timer5";
 764                         ti,timer-dsp;
 765                         ti,timer-pwm;
 766                 };
 767
 768                 timer6: timer@4013a000 {
 769                         compatible = "ti,omap5430-timer";
 770                         reg = <0x4013a000 0x80>,
 771                               <0x4903a000 0x80>;
 772                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 773                         ti,hwmods = "timer6";
 774                         ti,timer-dsp;
 775                         ti,timer-pwm;
 776                 };
 777
 778                 timer7: timer@4013c000 {
 779                         compatible = "ti,omap5430-timer";
 780                         reg = <0x4013c000 0x80>,
 781                               <0x4903c000 0x80>;
 782                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 783                         ti,hwmods = "timer7";
 784                         ti,timer-dsp;
 785                 };
 786
 787                 timer8: timer@4013e000 {
 788                         compatible = "ti,omap5430-timer";
 789                         reg = <0x4013e000 0x80>,
 790                               <0x4903e000 0x80>;
 791                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 792                         ti,hwmods = "timer8";
 793                         ti,timer-dsp;
 794                         ti,timer-pwm;
 795                 };
 796
 797                 timer9: timer@4803e000 {
 798                         compatible = "ti,omap5430-timer";
 799                         reg = <0x4803e000 0x80>;
 800                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 801                         ti,hwmods = "timer9";
 802                         ti,timer-pwm;
 803                 };
 804
 805                 timer10: timer@48086000 {
 806                         compatible = "ti,omap5430-timer";
 807                         reg = <0x48086000 0x80>;
 808                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 809                         ti,hwmods = "timer10";
 810                         ti,timer-pwm;
 811                 };
 812
 813                 timer11: timer@48088000 {
 814                         compatible = "ti,omap5430-timer";
 815                         reg = <0x48088000 0x80>;
 816                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 817                         ti,hwmods = "timer11";
 818                         ti,timer-pwm;
 819                 };
 820
 821                 wdt2: wdt@4ae14000 {
 822                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 823                         reg = <0x4ae14000 0x80>;
 824                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 825                         ti,hwmods = "wd_timer2";
 826                 };
 827
 828                 dmm@4e000000 {
 829                         compatible = "ti,omap5-dmm";
 830                         reg = <0x4e000000 0x800>;
 831                         interrupts = <0 113 0x4>;
 832                         ti,hwmods = "dmm";
 833                 };
 834
 835                 emif1: emif@4c000000 {
 836                         compatible      = "ti,emif-4d5";
 837                         ti,hwmods       = "emif1";
 838                         ti,no-idle-on-init;
 839                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 840                         reg = <0x4c000000 0x400>;
 841                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 842                         hw-caps-read-idle-ctrl;
 843                         hw-caps-ll-interface;
 844                         hw-caps-temp-alert;
 845                 };
 846
 847                 emif2: emif@4d000000 {
 848                         compatible      = "ti,emif-4d5";
 849                         ti,hwmods       = "emif2";
 850                         ti,no-idle-on-init;
 851                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 852                         reg = <0x4d000000 0x400>;
 853                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 854                         hw-caps-read-idle-ctrl;
 855                         hw-caps-ll-interface;
 856                         hw-caps-temp-alert;
 857                 };
 858
 859                 usb3: omap_dwc3@4a020000 {
 860                         compatible = "ti,dwc3";
 861                         ti,hwmods = "usb_otg_ss";
 862                         reg = <0x4a020000 0x10000>;
 863                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 864                         #address-cells = <1>;
 865                         #size-cells = <1>;
 866                         utmi-mode = <2>;
 867                         ranges;
 868                         dwc3@4a030000 {
 869                                 compatible = "snps,dwc3";
 870                                 reg = <0x4a030000 0x10000>;
 871                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 872                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 873                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 874                                 interrupt-names = "peripheral",
 875                                                   "host",
 876                                                   "otg";
 877                                 phys = <&usb2_phy>, <&usb3_phy>;
 878                                 phy-names = "usb2-phy", "usb3-phy";
 879                                 dr_mode = "peripheral";
 880                         };
 881                 };
 882
 883                 ocp2scp@4a080000 {
 884                         compatible = "ti,omap-ocp2scp";
 885                         #address-cells = <1>;
 886                         #size-cells = <1>;
 887                         reg = <0x4a080000 0x20>;
 888                         ranges;
 889                         ti,hwmods = "ocp2scp1";
 890                         usb2_phy: usb2phy@4a084000 {
 891                                 compatible = "ti,omap-usb2";
 892                                 reg = <0x4a084000 0x7c>;
 893                                 syscon-phy-power = <&scm_conf 0x300>;
 894                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 895                                 clock-names = "wkupclk", "refclk";
 896                                 #phy-cells = <0>;
 897                         };
 898
 899                         usb3_phy: usb3phy@4a084400 {
 900                                 compatible = "ti,omap-usb3";
 901                                 reg = <0x4a084400 0x80>,
 902                                       <0x4a084800 0x64>,
 903                                       <0x4a084c00 0x40>;
 904                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 905                                 syscon-phy-power = <&scm_conf 0x370>;
 906                                 clocks = <&usb_phy_cm_clk32k>,
 907                                          <&sys_clkin>,
 908                                          <&usb_otg_ss_refclk960m>;
 909                                 clock-names =   "wkupclk",
 910                                                 "sysclk",
 911                                                 "refclk";
 912                                 #phy-cells = <0>;
 913                         };
 914                 };
 915
 916                 usbhstll: usbhstll@4a062000 {
 917                         compatible = "ti,usbhs-tll";
 918                         reg = <0x4a062000 0x1000>;
 919                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 920                         ti,hwmods = "usb_tll_hs";
 921                 };
 922
 923                 usbhshost: usbhshost@4a064000 {
 924                         compatible = "ti,usbhs-host";
 925                         reg = <0x4a064000 0x800>;
 926                         ti,hwmods = "usb_host_hs";
 927                         #address-cells = <1>;
 928                         #size-cells = <1>;
 929                         ranges;
 930                         clocks = <&l3init_60m_fclk>,
 931                                  <&xclk60mhsp1_ck>,
 932                                  <&xclk60mhsp2_ck>;
 933                         clock-names = "refclk_60m_int",
 934                                       "refclk_60m_ext_p1",
 935                                       "refclk_60m_ext_p2";
 936
 937                         usbhsohci: ohci@4a064800 {
 938                                 compatible = "ti,ohci-omap3";
 939                                 reg = <0x4a064800 0x400>;
 940                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 941                         };
 942
 943                         usbhsehci: ehci@4a064c00 {
 944                                 compatible = "ti,ehci-omap";
 945                                 reg = <0x4a064c00 0x400>;
 946                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 947                         };
 948                 };
 949
 950                 bandgap: bandgap@4a0021e0 {
 951                         reg = <0x4a0021e0 0xc
 952                                0x4a00232c 0xc
 953                                0x4a002380 0x2c
 954                                0x4a0023C0 0x3c>;
 955                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 956                         compatible = "ti,omap5430-bandgap";
 957
 958                         #thermal-sensor-cells = <1>;
 959                 };
 960
 961                 /* OCP2SCP3 */
 962                 ocp2scp@4a090000 {
 963                         compatible = "ti,omap-ocp2scp";
 964                         #address-cells = <1>;
 965                         #size-cells = <1>;
 966                         reg = <0x4a090000 0x20>;
 967                         ranges;
 968                         ti,hwmods = "ocp2scp3";
 969                         sata_phy: phy@4a096000 {
 970                                 compatible = "ti,phy-pipe3-sata";
 971                                 reg = <0x4A096000 0x80>, /* phy_rx */
 972                                       <0x4A096400 0x64>, /* phy_tx */
 973                                       <0x4A096800 0x40>; /* pll_ctrl */
 974                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 975                                 syscon-phy-power = <&scm_conf 0x374>;
 976                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 977                                 clock-names = "sysclk", "refclk";
 978                                 #phy-cells = <0>;
 979                         };
 980                 };
 981
 982                 sata: sata@4a141100 {
 983                         compatible = "snps,dwc-ahci";
 984                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 985                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 986                         phys = <&sata_phy>;
 987                         phy-names = "sata-phy";
 988                         clocks = <&sata_ref_clk>;
 989                         ti,hwmods = "sata";
 990                 };
 991
 992                 dss: dss@58000000 {
 993                         compatible = "ti,omap5-dss";
 994                         reg = <0x58000000 0x80>;
 995                         status = "disabled";
 996                         ti,hwmods = "dss_core";
 997                         clocks = <&dss_dss_clk>;
 998                         clock-names = "fck";
 999                         #address-cells = <1>;
1000                         #size-cells = <1>;
1001                         ranges;
1002
1003                         dispc@58001000 {
1004                                 compatible = "ti,omap5-dispc";
1005                                 reg = <0x58001000 0x1000>;
1006                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1007                                 ti,hwmods = "dss_dispc";
1008                                 clocks = <&dss_dss_clk>;
1009                                 clock-names = "fck";
1010                         };
1011
1012                         rfbi: encoder@58002000  {
1013                                 compatible = "ti,omap5-rfbi";
1014                                 reg = <0x58002000 0x100>;
1015                                 status = "disabled";
1016                                 ti,hwmods = "dss_rfbi";
1017                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1018                                 clock-names = "fck", "ick";
1019                         };
1020
1021                         dsi1: encoder@58004000 {
1022                                 compatible = "ti,omap5-dsi";
1023                                 reg = <0x58004000 0x200>,
1024                                       <0x58004200 0x40>,
1025                                       <0x58004300 0x40>;
1026                                 reg-names = "proto", "phy", "pll";
1027                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1028                                 status = "disabled";
1029                                 ti,hwmods = "dss_dsi1";
1030                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1031                                 clock-names = "fck", "sys_clk";
1032                         };
1033
1034                         dsi2: encoder@58005000 {
1035                                 compatible = "ti,omap5-dsi";
1036                                 reg = <0x58009000 0x200>,
1037                                       <0x58009200 0x40>,
1038                                       <0x58009300 0x40>;
1039                                 reg-names = "proto", "phy", "pll";
1040                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1041                                 status = "disabled";
1042                                 ti,hwmods = "dss_dsi2";
1043                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1044                                 clock-names = "fck", "sys_clk";
1045                         };
1046
1047                         hdmi: encoder@58060000 {
1048                                 compatible = "ti,omap5-hdmi";
1049                                 reg = <0x58040000 0x200>,
1050                                       <0x58040200 0x80>,
1051                                       <0x58040300 0x80>,
1052                                       <0x58060000 0x19000>;
1053                                 reg-names = "wp", "pll", "phy", "core";
1054                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1055                                 status = "disabled";
1056                                 ti,hwmods = "dss_hdmi";
1057                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1058                                 clock-names = "fck", "sys_clk";
1059                                 dmas = <&sdma 76>;
1060                                 dma-names = "audio_tx";
1061                         };
1062                 };
1063
1064                 abb_mpu: regulator-abb-mpu {
1065                         compatible = "ti,abb-v2";
1066                         regulator-name = "abb_mpu";
1067                         #address-cells = <0>;
1068                         #size-cells = <0>;
1069                         clocks = <&sys_clkin>;
1070                         ti,settling-time = <50>;
1071                         ti,clock-cycles = <16>;
1072
1073                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1074                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1075                         reg-names = "base-address", "int-address",
1076                                     "efuse-address", "ldo-address";
1077                         ti,tranxdone-status-mask = <0x80>;
1078                         /* LDOVBBMPU_MUX_CTRL */
1079                         ti,ldovbb-override-mask = <0x400>;
1080                         /* LDOVBBMPU_VSET_OUT */
1081                         ti,ldovbb-vset-mask = <0x1F>;
1082
1083                         /*
1084                          * NOTE: only FBB mode used but actual vset will
1085                          * determine final biasing
1086                          */
1087                         ti,abb_info = <
1088                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1089                         1060000         0       0x0     0 0x02000000 0x01F00000
1090                         1250000         0       0x4     0 0x02000000 0x01F00000
1091                         >;
1092                 };
1093
1094                 abb_mm: regulator-abb-mm {
1095                         compatible = "ti,abb-v2";
1096                         regulator-name = "abb_mm";
1097                         #address-cells = <0>;
1098                         #size-cells = <0>;
1099                         clocks = <&sys_clkin>;
1100                         ti,settling-time = <50>;
1101                         ti,clock-cycles = <16>;
1102
1103                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1104                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1105                         reg-names = "base-address", "int-address",
1106                                     "efuse-address", "ldo-address";
1107                         ti,tranxdone-status-mask = <0x80000000>;
1108                         /* LDOVBBMM_MUX_CTRL */
1109                         ti,ldovbb-override-mask = <0x400>;
1110                         /* LDOVBBMM_VSET_OUT */
1111                         ti,ldovbb-vset-mask = <0x1F>;
1112
1113                         /*
1114                          * NOTE: only FBB mode used but actual vset will
1115                          * determine final biasing
1116                          */
1117                         ti,abb_info = <
1118                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1119                         1025000         0       0x0     0 0x02000000 0x01F00000
1120                         1120000         0       0x4     0 0x02000000 0x01F00000
1121                         >;
1122                 };
1123         };
1124 };
1125
1126 &cpu_thermal {
1127         polling-delay = <500>; /* milliseconds */
1128 };
1129
1130 /include/ "omap54xx-clocks.dtsi"