arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13 #include <dt-bindings/clock/omap5.h>
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,omap5";
  20         interrupt-parent = <&wakeupgen>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,cortex-a15-pmu";
  87                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  89         };
  90
  91         gic: interrupt-controller@48211000 {
  92                 compatible = "arm,cortex-a15-gic";
  93                 interrupt-controller;
  94                 #interrupt-cells = <3>;
  95                 reg = <0 0x48211000 0 0x1000>,
  96                       <0 0x48212000 0 0x2000>,
  97                       <0 0x48214000 0 0x2000>,
  98                       <0 0x48216000 0 0x2000>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         wakeupgen: interrupt-controller@48281000 {
 103                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0 0x48281000 0 0x1000>;
 107                 interrupt-parent = <&gic>;
 108         };
 109
 110         /*
 111          * The soc node represents the soc top level view. It is used for IPs
 112          * that are not memory mapped in the MPU view or for the MPU itself.
 113          */
 114         soc {
 115                 compatible = "ti,omap-infra";
 116                 mpu {
 117                         compatible = "ti,omap4-mpu";
 118                         ti,hwmods = "mpu";
 119                         sram = <&ocmcram>;
 120                 };
 121         };
 122
 123         /*
 124          * XXX: Use a flat representation of the OMAP3 interconnect.
 125          * The real OMAP interconnect network is quite complex.
 126          * Since it will not bring real advantage to represent that in DT for
 127          * the moment, just use a fake OCP bus entry to represent the whole bus
 128          * hierarchy.
 129          */
 130         ocp {
 131                 compatible = "ti,omap5-l3-noc", "simple-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges = <0 0 0 0xc0000000>;
 135                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 136                 reg = <0 0x44000000 0 0x2000>,
 137                       <0 0x44800000 0 0x3000>,
 138                       <0 0x45000000 0 0x4000>;
 139                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 141
 142                 l4_cfg: l4@4a000000 {
 143                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0 0x4a000000 0x22a000>;
 147
 148                         scm_core: scm@2000 {
 149                                 compatible = "ti,omap5-scm-core", "simple-bus";
 150                                 reg = <0x2000 0x1000>;
 151                                 #address-cells = <1>;
 152                                 #size-cells = <1>;
 153                                 ranges = <0 0x2000 0x800>;
 154
 155                                 scm_conf: scm_conf@0 {
 156                                         compatible = "syscon";
 157                                         reg = <0x0 0x800>;
 158                                         #address-cells = <1>;
 159                                         #size-cells = <1>;
 160                                 };
 161                         };
 162
 163                         scm_padconf_core: scm@2800 {
 164                                 compatible = "ti,omap5-scm-padconf-core",
 165                                              "simple-bus";
 166                                 #address-cells = <1>;
 167                                 #size-cells = <1>;
 168                                 ranges = <0 0x2800 0x800>;
 169
 170                                 omap5_pmx_core: pinmux@40 {
 171                                         compatible = "ti,omap5-padconf",
 172                                                      "pinctrl-single";
 173                                         reg = <0x40 0x01b6>;
 174                                         #address-cells = <1>;
 175                                         #size-cells = <0>;
 176                                         #pinctrl-cells = <1>;
 177                                         #interrupt-cells = <1>;
 178                                         interrupt-controller;
 179                                         pinctrl-single,register-width = <16>;
 180                                         pinctrl-single,function-mask = <0x7fff>;
 181                                 };
 182
 183                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 184                                         compatible = "syscon",
 185                                                      "simple-bus";
 186                                         reg = <0x5a0 0xec>;
 187                                         #address-cells = <1>;
 188                                         #size-cells = <1>;
 189                                         ranges = <0 0x5a0 0xec>;
 190
 191                                         pbias_regulator: pbias_regulator@60 {
 192                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 193                                                 reg = <0x60 0x4>;
 194                                                 syscon = <&omap5_padconf_global>;
 195                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 196                                                         regulator-name = "pbias_mmc_omap5";
 197                                                         regulator-min-microvolt = <1800000>;
 198                                                         regulator-max-microvolt = <3300000>;
 199                                                 };
 200                                         };
 201                                 };
 202                         };
 203
 204                         cm_core_aon: cm_core_aon@4000 {
 205                                 compatible = "ti,omap5-cm-core-aon",
 206                                              "simple-bus";
 207                                 reg = <0x4000 0x2000>;
 208                                 #address-cells = <1>;
 209                                 #size-cells = <1>;
 210                                 ranges = <0 0x4000 0x2000>;
 211
 212                                 cm_core_aon_clocks: clocks {
 213                                         #address-cells = <1>;
 214                                         #size-cells = <0>;
 215                                 };
 216
 217                                 cm_core_aon_clockdomains: clockdomains {
 218                                 };
 219                         };
 220
 221                         cm_core: cm_core@8000 {
 222                                 compatible = "ti,omap5-cm-core", "simple-bus";
 223                                 reg = <0x8000 0x3000>;
 224                                 #address-cells = <1>;
 225                                 #size-cells = <1>;
 226                                 ranges = <0 0x8000 0x3000>;
 227
 228                                 cm_core_clocks: clocks {
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                 };
 232
 233                                 cm_core_clockdomains: clockdomains {
 234                                 };
 235                         };
 236                 };
 237
 238                 l4_wkup: l4@4ae00000 {
 239                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         ranges = <0 0x4ae00000 0x2b000>;
 243
 244                         counter32k: counter@4000 {
 245                                 compatible = "ti,omap-counter32k";
 246                                 reg = <0x4000 0x40>;
 247                                 ti,hwmods = "counter_32k";
 248                         };
 249
 250                         prm: prm@6000 {
 251                                 compatible = "ti,omap5-prm", "simple-bus";
 252                                 reg = <0x6000 0x3000>;
 253                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 254                                 #address-cells = <1>;
 255                                 #size-cells = <1>;
 256                                 ranges = <0 0x6000 0x3000>;
 257
 258                                 prm_clocks: clocks {
 259                                         #address-cells = <1>;
 260                                         #size-cells = <0>;
 261                                 };
 262
 263                                 prm_clockdomains: clockdomains {
 264                                 };
 265                         };
 266
 267                         scrm: scrm@a000 {
 268                                 compatible = "ti,omap5-scrm";
 269                                 reg = <0xa000 0x2000>;
 270
 271                                 scrm_clocks: clocks {
 272                                         #address-cells = <1>;
 273                                         #size-cells = <0>;
 274                                 };
 275
 276                                 scrm_clockdomains: clockdomains {
 277                                 };
 278                         };
 279
 280                         omap5_pmx_wkup: pinmux@c840 {
 281                                 compatible = "ti,omap5-padconf",
 282                                              "pinctrl-single";
 283                                 reg = <0xc840 0x003c>;
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286                                 #pinctrl-cells = <1>;
 287                                 #interrupt-cells = <1>;
 288                                 interrupt-controller;
 289                                 pinctrl-single,register-width = <16>;
 290                                 pinctrl-single,function-mask = <0x7fff>;
 291                         };
 292                 };
 293
 294                 ocmcram: ocmcram@40300000 {
 295                         compatible = "mmio-sram";
 296                         reg = <0x40300000 0x20000>; /* 128k */
 297                 };
 298
 299                 sdma: dma-controller@4a056000 {
 300                         compatible = "ti,omap4430-sdma";
 301                         reg = <0x4a056000 0x1000>;
 302                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 306                         #dma-cells = <1>;
 307                         dma-channels = <32>;
 308                         dma-requests = <127>;
 309                         ti,hwmods = "dma_system";
 310                 };
 311
 312                 gpio1: gpio@4ae10000 {
 313                         compatible = "ti,omap4-gpio";
 314                         reg = <0x4ae10000 0x200>;
 315                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "gpio1";
 317                         ti,gpio-always-on;
 318                         gpio-controller;
 319                         #gpio-cells = <2>;
 320                         interrupt-controller;
 321                         #interrupt-cells = <2>;
 322                 };
 323
 324                 gpio2: gpio@48055000 {
 325                         compatible = "ti,omap4-gpio";
 326                         reg = <0x48055000 0x200>;
 327                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 328                         ti,hwmods = "gpio2";
 329                         gpio-controller;
 330                         #gpio-cells = <2>;
 331                         interrupt-controller;
 332                         #interrupt-cells = <2>;
 333                 };
 334
 335                 gpio3: gpio@48057000 {
 336                         compatible = "ti,omap4-gpio";
 337                         reg = <0x48057000 0x200>;
 338                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 339                         ti,hwmods = "gpio3";
 340                         gpio-controller;
 341                         #gpio-cells = <2>;
 342                         interrupt-controller;
 343                         #interrupt-cells = <2>;
 344                 };
 345
 346                 gpio4: gpio@48059000 {
 347                         compatible = "ti,omap4-gpio";
 348                         reg = <0x48059000 0x200>;
 349                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 350                         ti,hwmods = "gpio4";
 351                         gpio-controller;
 352                         #gpio-cells = <2>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                 };
 356
 357                 gpio5: gpio@4805b000 {
 358                         compatible = "ti,omap4-gpio";
 359                         reg = <0x4805b000 0x200>;
 360                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 361                         ti,hwmods = "gpio5";
 362                         gpio-controller;
 363                         #gpio-cells = <2>;
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                 };
 367
 368                 gpio6: gpio@4805d000 {
 369                         compatible = "ti,omap4-gpio";
 370                         reg = <0x4805d000 0x200>;
 371                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 372                         ti,hwmods = "gpio6";
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         interrupt-controller;
 376                         #interrupt-cells = <2>;
 377                 };
 378
 379                 gpio7: gpio@48051000 {
 380                         compatible = "ti,omap4-gpio";
 381                         reg = <0x48051000 0x200>;
 382                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 383                         ti,hwmods = "gpio7";
 384                         gpio-controller;
 385                         #gpio-cells = <2>;
 386                         interrupt-controller;
 387                         #interrupt-cells = <2>;
 388                 };
 389
 390                 gpio8: gpio@48053000 {
 391                         compatible = "ti,omap4-gpio";
 392                         reg = <0x48053000 0x200>;
 393                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 394                         ti,hwmods = "gpio8";
 395                         gpio-controller;
 396                         #gpio-cells = <2>;
 397                         interrupt-controller;
 398                         #interrupt-cells = <2>;
 399                 };
 400
 401                 gpmc: gpmc@50000000 {
 402                         compatible = "ti,omap4430-gpmc";
 403                         reg = <0x50000000 0x1000>;
 404                         #address-cells = <2>;
 405                         #size-cells = <1>;
 406                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 407                         dmas = <&sdma 4>;
 408                         dma-names = "rxtx";
 409                         gpmc,num-cs = <8>;
 410                         gpmc,num-waitpins = <4>;
 411                         ti,hwmods = "gpmc";
 412                         clocks = <&l3_iclk_div>;
 413                         clock-names = "fck";
 414                         interrupt-controller;
 415                         #interrupt-cells = <2>;
 416                         gpio-controller;
 417                         #gpio-cells = <2>;
 418                 };
 419
 420                 i2c1: i2c@48070000 {
 421                         compatible = "ti,omap4-i2c";
 422                         reg = <0x48070000 0x100>;
 423                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         ti,hwmods = "i2c1";
 427                 };
 428
 429                 i2c2: i2c@48072000 {
 430                         compatible = "ti,omap4-i2c";
 431                         reg = <0x48072000 0x100>;
 432                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         ti,hwmods = "i2c2";
 436                 };
 437
 438                 i2c3: i2c@48060000 {
 439                         compatible = "ti,omap4-i2c";
 440                         reg = <0x48060000 0x100>;
 441                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         ti,hwmods = "i2c3";
 445                 };
 446
 447                 i2c4: i2c@4807a000 {
 448                         compatible = "ti,omap4-i2c";
 449                         reg = <0x4807a000 0x100>;
 450                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         ti,hwmods = "i2c4";
 454                 };
 455
 456                 i2c5: i2c@4807c000 {
 457                         compatible = "ti,omap4-i2c";
 458                         reg = <0x4807c000 0x100>;
 459                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         ti,hwmods = "i2c5";
 463                 };
 464
 465                 hwspinlock: spinlock@4a0f6000 {
 466                         compatible = "ti,omap4-hwspinlock";
 467                         reg = <0x4a0f6000 0x1000>;
 468                         ti,hwmods = "spinlock";
 469                         #hwlock-cells = <1>;
 470                 };
 471
 472                 mcspi1: spi@48098000 {
 473                         compatible = "ti,omap4-mcspi";
 474                         reg = <0x48098000 0x200>;
 475                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         ti,hwmods = "mcspi1";
 479                         ti,spi-num-cs = <4>;
 480                         dmas = <&sdma 35>,
 481                                <&sdma 36>,
 482                                <&sdma 37>,
 483                                <&sdma 38>,
 484                                <&sdma 39>,
 485                                <&sdma 40>,
 486                                <&sdma 41>,
 487                                <&sdma 42>;
 488                         dma-names = "tx0", "rx0", "tx1", "rx1",
 489                                     "tx2", "rx2", "tx3", "rx3";
 490                 };
 491
 492                 mcspi2: spi@4809a000 {
 493                         compatible = "ti,omap4-mcspi";
 494                         reg = <0x4809a000 0x200>;
 495                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         ti,hwmods = "mcspi2";
 499                         ti,spi-num-cs = <2>;
 500                         dmas = <&sdma 43>,
 501                                <&sdma 44>,
 502                                <&sdma 45>,
 503                                <&sdma 46>;
 504                         dma-names = "tx0", "rx0", "tx1", "rx1";
 505                 };
 506
 507                 mcspi3: spi@480b8000 {
 508                         compatible = "ti,omap4-mcspi";
 509                         reg = <0x480b8000 0x200>;
 510                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         ti,hwmods = "mcspi3";
 514                         ti,spi-num-cs = <2>;
 515                         dmas = <&sdma 15>, <&sdma 16>;
 516                         dma-names = "tx0", "rx0";
 517                 };
 518
 519                 mcspi4: spi@480ba000 {
 520                         compatible = "ti,omap4-mcspi";
 521                         reg = <0x480ba000 0x200>;
 522                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         ti,hwmods = "mcspi4";
 526                         ti,spi-num-cs = <1>;
 527                         dmas = <&sdma 70>, <&sdma 71>;
 528                         dma-names = "tx0", "rx0";
 529                 };
 530
 531                 uart1: serial@4806a000 {
 532                         compatible = "ti,omap4-uart";
 533                         reg = <0x4806a000 0x100>;
 534                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 535                         ti,hwmods = "uart1";
 536                         clock-frequency = <48000000>;
 537                 };
 538
 539                 uart2: serial@4806c000 {
 540                         compatible = "ti,omap4-uart";
 541                         reg = <0x4806c000 0x100>;
 542                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 543                         ti,hwmods = "uart2";
 544                         clock-frequency = <48000000>;
 545                 };
 546
 547                 uart3: serial@48020000 {
 548                         compatible = "ti,omap4-uart";
 549                         reg = <0x48020000 0x100>;
 550                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 551                         ti,hwmods = "uart3";
 552                         clock-frequency = <48000000>;
 553                 };
 554
 555                 uart4: serial@4806e000 {
 556                         compatible = "ti,omap4-uart";
 557                         reg = <0x4806e000 0x100>;
 558                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 559                         ti,hwmods = "uart4";
 560                         clock-frequency = <48000000>;
 561                 };
 562
 563                 uart5: serial@48066000 {
 564                         compatible = "ti,omap4-uart";
 565                         reg = <0x48066000 0x100>;
 566                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 567                         ti,hwmods = "uart5";
 568                         clock-frequency = <48000000>;
 569                 };
 570
 571                 uart6: serial@48068000 {
 572                         compatible = "ti,omap4-uart";
 573                         reg = <0x48068000 0x100>;
 574                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "uart6";
 576                         clock-frequency = <48000000>;
 577                 };
 578
 579                 mmc1: mmc@4809c000 {
 580                         compatible = "ti,omap4-hsmmc";
 581                         reg = <0x4809c000 0x400>;
 582                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 583                         ti,hwmods = "mmc1";
 584                         ti,dual-volt;
 585                         ti,needs-special-reset;
 586                         dmas = <&sdma 61>, <&sdma 62>;
 587                         dma-names = "tx", "rx";
 588                         pbias-supply = <&pbias_mmc_reg>;
 589                 };
 590
 591                 mmc2: mmc@480b4000 {
 592                         compatible = "ti,omap4-hsmmc";
 593                         reg = <0x480b4000 0x400>;
 594                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "mmc2";
 596                         ti,needs-special-reset;
 597                         dmas = <&sdma 47>, <&sdma 48>;
 598                         dma-names = "tx", "rx";
 599                 };
 600
 601                 mmc3: mmc@480ad000 {
 602                         compatible = "ti,omap4-hsmmc";
 603                         reg = <0x480ad000 0x400>;
 604                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 605                         ti,hwmods = "mmc3";
 606                         ti,needs-special-reset;
 607                         dmas = <&sdma 77>, <&sdma 78>;
 608                         dma-names = "tx", "rx";
 609                 };
 610
 611                 mmc4: mmc@480d1000 {
 612                         compatible = "ti,omap4-hsmmc";
 613                         reg = <0x480d1000 0x400>;
 614                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "mmc4";
 616                         ti,needs-special-reset;
 617                         dmas = <&sdma 57>, <&sdma 58>;
 618                         dma-names = "tx", "rx";
 619                 };
 620
 621                 mmc5: mmc@480d5000 {
 622                         compatible = "ti,omap4-hsmmc";
 623                         reg = <0x480d5000 0x400>;
 624                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 625                         ti,hwmods = "mmc5";
 626                         ti,needs-special-reset;
 627                         dmas = <&sdma 59>, <&sdma 60>;
 628                         dma-names = "tx", "rx";
 629                 };
 630
 631                 mmu_dsp: mmu@4a066000 {
 632                         compatible = "ti,omap4-iommu";
 633                         reg = <0x4a066000 0x100>;
 634                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 635                         ti,hwmods = "mmu_dsp";
 636                         #iommu-cells = <0>;
 637                 };
 638
 639                 mmu_ipu: mmu@55082000 {
 640                         compatible = "ti,omap4-iommu";
 641                         reg = <0x55082000 0x100>;
 642                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 643                         ti,hwmods = "mmu_ipu";
 644                         #iommu-cells = <0>;
 645                         ti,iommu-bus-err-back;
 646                 };
 647
 648                 keypad: keypad@4ae1c000 {
 649                         compatible = "ti,omap4-keypad";
 650                         reg = <0x4ae1c000 0x400>;
 651                         ti,hwmods = "kbd";
 652                 };
 653
 654                 mcpdm: mcpdm@40132000 {
 655                         compatible = "ti,omap4-mcpdm";
 656                         reg = <0x40132000 0x7f>, /* MPU private access */
 657                               <0x49032000 0x7f>; /* L3 Interconnect */
 658                         reg-names = "mpu", "dma";
 659                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "mcpdm";
 661                         dmas = <&sdma 65>,
 662                                <&sdma 66>;
 663                         dma-names = "up_link", "dn_link";
 664                         status = "disabled";
 665                 };
 666
 667                 dmic: dmic@4012e000 {
 668                         compatible = "ti,omap4-dmic";
 669                         reg = <0x4012e000 0x7f>, /* MPU private access */
 670                               <0x4902e000 0x7f>; /* L3 Interconnect */
 671                         reg-names = "mpu", "dma";
 672                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "dmic";
 674                         dmas = <&sdma 67>;
 675                         dma-names = "up_link";
 676                         status = "disabled";
 677                 };
 678
 679                 mcbsp1: mcbsp@40122000 {
 680                         compatible = "ti,omap4-mcbsp";
 681                         reg = <0x40122000 0xff>, /* MPU private access */
 682                               <0x49022000 0xff>; /* L3 Interconnect */
 683                         reg-names = "mpu", "dma";
 684                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 685                         interrupt-names = "common";
 686                         ti,buffer-size = <128>;
 687                         ti,hwmods = "mcbsp1";
 688                         dmas = <&sdma 33>,
 689                                <&sdma 34>;
 690                         dma-names = "tx", "rx";
 691                         status = "disabled";
 692                 };
 693
 694                 mcbsp2: mcbsp@40124000 {
 695                         compatible = "ti,omap4-mcbsp";
 696                         reg = <0x40124000 0xff>, /* MPU private access */
 697                               <0x49024000 0xff>; /* L3 Interconnect */
 698                         reg-names = "mpu", "dma";
 699                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-names = "common";
 701                         ti,buffer-size = <128>;
 702                         ti,hwmods = "mcbsp2";
 703                         dmas = <&sdma 17>,
 704                                <&sdma 18>;
 705                         dma-names = "tx", "rx";
 706                         status = "disabled";
 707                 };
 708
 709                 mcbsp3: mcbsp@40126000 {
 710                         compatible = "ti,omap4-mcbsp";
 711                         reg = <0x40126000 0xff>, /* MPU private access */
 712                               <0x49026000 0xff>; /* L3 Interconnect */
 713                         reg-names = "mpu", "dma";
 714                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 715                         interrupt-names = "common";
 716                         ti,buffer-size = <128>;
 717                         ti,hwmods = "mcbsp3";
 718                         dmas = <&sdma 19>,
 719                                <&sdma 20>;
 720                         dma-names = "tx", "rx";
 721                         status = "disabled";
 722                 };
 723
 724                 mailbox: mailbox@4a0f4000 {
 725                         compatible = "ti,omap4-mailbox";
 726                         reg = <0x4a0f4000 0x200>;
 727                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "mailbox";
 729                         #mbox-cells = <1>;
 730                         ti,mbox-num-users = <3>;
 731                         ti,mbox-num-fifos = <8>;
 732                         mbox_ipu: mbox_ipu {
 733                                 ti,mbox-tx = <0 0 0>;
 734                                 ti,mbox-rx = <1 0 0>;
 735                         };
 736                         mbox_dsp: mbox_dsp {
 737                                 ti,mbox-tx = <3 0 0>;
 738                                 ti,mbox-rx = <2 0 0>;
 739                         };
 740                 };
 741
 742                 timer1: timer@4ae18000 {
 743                         compatible = "ti,omap5430-timer";
 744                         reg = <0x4ae18000 0x80>;
 745                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "timer1";
 747                         ti,timer-alwon;
 748                         clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
 749                         clock-names = "fck";
 750                 };
 751
 752                 timer2: timer@48032000 {
 753                         compatible = "ti,omap5430-timer";
 754                         reg = <0x48032000 0x80>;
 755                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 756                         ti,hwmods = "timer2";
 757                 };
 758
 759                 timer3: timer@48034000 {
 760                         compatible = "ti,omap5430-timer";
 761                         reg = <0x48034000 0x80>;
 762                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "timer3";
 764                 };
 765
 766                 timer4: timer@48036000 {
 767                         compatible = "ti,omap5430-timer";
 768                         reg = <0x48036000 0x80>;
 769                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 770                         ti,hwmods = "timer4";
 771                 };
 772
 773                 timer5: timer@40138000 {
 774                         compatible = "ti,omap5430-timer";
 775                         reg = <0x40138000 0x80>,
 776                               <0x49038000 0x80>;
 777                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 778                         ti,hwmods = "timer5";
 779                         ti,timer-dsp;
 780                         ti,timer-pwm;
 781                 };
 782
 783                 timer6: timer@4013a000 {
 784                         compatible = "ti,omap5430-timer";
 785                         reg = <0x4013a000 0x80>,
 786                               <0x4903a000 0x80>;
 787                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 788                         ti,hwmods = "timer6";
 789                         ti,timer-dsp;
 790                         ti,timer-pwm;
 791                 };
 792
 793                 timer7: timer@4013c000 {
 794                         compatible = "ti,omap5430-timer";
 795                         reg = <0x4013c000 0x80>,
 796                               <0x4903c000 0x80>;
 797                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 798                         ti,hwmods = "timer7";
 799                         ti,timer-dsp;
 800                 };
 801
 802                 timer8: timer@4013e000 {
 803                         compatible = "ti,omap5430-timer";
 804                         reg = <0x4013e000 0x80>,
 805                               <0x4903e000 0x80>;
 806                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 807                         ti,hwmods = "timer8";
 808                         ti,timer-dsp;
 809                         ti,timer-pwm;
 810                 };
 811
 812                 timer9: timer@4803e000 {
 813                         compatible = "ti,omap5430-timer";
 814                         reg = <0x4803e000 0x80>;
 815                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 816                         ti,hwmods = "timer9";
 817                         ti,timer-pwm;
 818                 };
 819
 820                 timer10: timer@48086000 {
 821                         compatible = "ti,omap5430-timer";
 822                         reg = <0x48086000 0x80>;
 823                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 824                         ti,hwmods = "timer10";
 825                         ti,timer-pwm;
 826                 };
 827
 828                 timer11: timer@48088000 {
 829                         compatible = "ti,omap5430-timer";
 830                         reg = <0x48088000 0x80>;
 831                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 832                         ti,hwmods = "timer11";
 833                         ti,timer-pwm;
 834                 };
 835
 836                 wdt2: wdt@4ae14000 {
 837                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 838                         reg = <0x4ae14000 0x80>;
 839                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 840                         ti,hwmods = "wd_timer2";
 841                 };
 842
 843                 dmm@4e000000 {
 844                         compatible = "ti,omap5-dmm";
 845                         reg = <0x4e000000 0x800>;
 846                         interrupts = <0 113 0x4>;
 847                         ti,hwmods = "dmm";
 848                 };
 849
 850                 emif1: emif@4c000000 {
 851                         compatible      = "ti,emif-4d5";
 852                         ti,hwmods       = "emif1";
 853                         ti,no-idle-on-init;
 854                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 855                         reg = <0x4c000000 0x400>;
 856                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 857                         hw-caps-read-idle-ctrl;
 858                         hw-caps-ll-interface;
 859                         hw-caps-temp-alert;
 860                 };
 861
 862                 emif2: emif@4d000000 {
 863                         compatible      = "ti,emif-4d5";
 864                         ti,hwmods       = "emif2";
 865                         ti,no-idle-on-init;
 866                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 867                         reg = <0x4d000000 0x400>;
 868                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 869                         hw-caps-read-idle-ctrl;
 870                         hw-caps-ll-interface;
 871                         hw-caps-temp-alert;
 872                 };
 873
 874                 usb3: omap_dwc3@4a020000 {
 875                         compatible = "ti,dwc3";
 876                         ti,hwmods = "usb_otg_ss";
 877                         reg = <0x4a020000 0x10000>;
 878                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 879                         #address-cells = <1>;
 880                         #size-cells = <1>;
 881                         utmi-mode = <2>;
 882                         ranges;
 883                         dwc3: dwc3@4a030000 {
 884                                 compatible = "snps,dwc3";
 885                                 reg = <0x4a030000 0x10000>;
 886                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 887                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 888                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 889                                 interrupt-names = "peripheral",
 890                                                   "host",
 891                                                   "otg";
 892                                 phys = <&usb2_phy>, <&usb3_phy>;
 893                                 phy-names = "usb2-phy", "usb3-phy";
 894                                 dr_mode = "peripheral";
 895                         };
 896                 };
 897
 898                 ocp2scp@4a080000 {
 899                         compatible = "ti,omap-ocp2scp";
 900                         #address-cells = <1>;
 901                         #size-cells = <1>;
 902                         reg = <0x4a080000 0x20>;
 903                         ranges;
 904                         ti,hwmods = "ocp2scp1";
 905                         usb2_phy: usb2phy@4a084000 {
 906                                 compatible = "ti,omap-usb2";
 907                                 reg = <0x4a084000 0x7c>;
 908                                 syscon-phy-power = <&scm_conf 0x300>;
 909                                 clocks = <&usb_phy_cm_clk32k>,
 910                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 911                                 clock-names = "wkupclk", "refclk";
 912                                 #phy-cells = <0>;
 913                         };
 914
 915                         usb3_phy: usb3phy@4a084400 {
 916                                 compatible = "ti,omap-usb3";
 917                                 reg = <0x4a084400 0x80>,
 918                                       <0x4a084800 0x64>,
 919                                       <0x4a084c00 0x40>;
 920                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 921                                 syscon-phy-power = <&scm_conf 0x370>;
 922                                 clocks = <&usb_phy_cm_clk32k>,
 923                                          <&sys_clkin>,
 924                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 925                                 clock-names =   "wkupclk",
 926                                                 "sysclk",
 927                                                 "refclk";
 928                                 #phy-cells = <0>;
 929                         };
 930                 };
 931
 932                 usbhstll: usbhstll@4a062000 {
 933                         compatible = "ti,usbhs-tll";
 934                         reg = <0x4a062000 0x1000>;
 935                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 936                         ti,hwmods = "usb_tll_hs";
 937                 };
 938
 939                 usbhshost: usbhshost@4a064000 {
 940                         compatible = "ti,usbhs-host";
 941                         reg = <0x4a064000 0x800>;
 942                         ti,hwmods = "usb_host_hs";
 943                         #address-cells = <1>;
 944                         #size-cells = <1>;
 945                         ranges;
 946                         clocks = <&l3init_60m_fclk>,
 947                                  <&xclk60mhsp1_ck>,
 948                                  <&xclk60mhsp2_ck>;
 949                         clock-names = "refclk_60m_int",
 950                                       "refclk_60m_ext_p1",
 951                                       "refclk_60m_ext_p2";
 952
 953                         usbhsohci: ohci@4a064800 {
 954                                 compatible = "ti,ohci-omap3";
 955                                 reg = <0x4a064800 0x400>;
 956                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 957                                 remote-wakeup-connected;
 958                         };
 959
 960                         usbhsehci: ehci@4a064c00 {
 961                                 compatible = "ti,ehci-omap";
 962                                 reg = <0x4a064c00 0x400>;
 963                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 964                         };
 965                 };
 966
 967                 bandgap: bandgap@4a0021e0 {
 968                         reg = <0x4a0021e0 0xc
 969                                0x4a00232c 0xc
 970                                0x4a002380 0x2c
 971                                0x4a0023C0 0x3c>;
 972                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 973                         compatible = "ti,omap5430-bandgap";
 974
 975                         #thermal-sensor-cells = <1>;
 976                 };
 977
 978                 /* OCP2SCP3 */
 979                 ocp2scp@4a090000 {
 980                         compatible = "ti,omap-ocp2scp";
 981                         #address-cells = <1>;
 982                         #size-cells = <1>;
 983                         reg = <0x4a090000 0x20>;
 984                         ranges;
 985                         ti,hwmods = "ocp2scp3";
 986                         sata_phy: phy@4a096000 {
 987                                 compatible = "ti,phy-pipe3-sata";
 988                                 reg = <0x4A096000 0x80>, /* phy_rx */
 989                                       <0x4A096400 0x64>, /* phy_tx */
 990                                       <0x4A096800 0x40>; /* pll_ctrl */
 991                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 992                                 syscon-phy-power = <&scm_conf 0x374>;
 993                                 clocks = <&sys_clkin>,
 994                                          <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
 995                                 clock-names = "sysclk", "refclk";
 996                                 #phy-cells = <0>;
 997                         };
 998                 };
 999
1000                 sata: sata@4a141100 {
1001                         compatible = "snps,dwc-ahci";
1002                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1003                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1004                         phys = <&sata_phy>;
1005                         phy-names = "sata-phy";
1006                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1007                         ti,hwmods = "sata";
1008                         ports-implemented = <0x1>;
1009                 };
1010
1011                 dss: dss@58000000 {
1012                         compatible = "ti,omap5-dss";
1013                         reg = <0x58000000 0x80>;
1014                         status = "disabled";
1015                         ti,hwmods = "dss_core";
1016                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1017                         clock-names = "fck";
1018                         #address-cells = <1>;
1019                         #size-cells = <1>;
1020                         ranges;
1021
1022                         dispc@58001000 {
1023                                 compatible = "ti,omap5-dispc";
1024                                 reg = <0x58001000 0x1000>;
1025                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1026                                 ti,hwmods = "dss_dispc";
1027                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1028                                 clock-names = "fck";
1029                         };
1030
1031                         rfbi: encoder@58002000  {
1032                                 compatible = "ti,omap5-rfbi";
1033                                 reg = <0x58002000 0x100>;
1034                                 status = "disabled";
1035                                 ti,hwmods = "dss_rfbi";
1036                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1037                                 clock-names = "fck", "ick";
1038                         };
1039
1040                         dsi1: encoder@58004000 {
1041                                 compatible = "ti,omap5-dsi";
1042                                 reg = <0x58004000 0x200>,
1043                                       <0x58004200 0x40>,
1044                                       <0x58004300 0x40>;
1045                                 reg-names = "proto", "phy", "pll";
1046                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1047                                 status = "disabled";
1048                                 ti,hwmods = "dss_dsi1";
1049                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1050                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1051                                 clock-names = "fck", "sys_clk";
1052                         };
1053
1054                         dsi2: encoder@58005000 {
1055                                 compatible = "ti,omap5-dsi";
1056                                 reg = <0x58009000 0x200>,
1057                                       <0x58009200 0x40>,
1058                                       <0x58009300 0x40>;
1059                                 reg-names = "proto", "phy", "pll";
1060                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1061                                 status = "disabled";
1062                                 ti,hwmods = "dss_dsi2";
1063                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1064                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1065                                 clock-names = "fck", "sys_clk";
1066                         };
1067
1068                         hdmi: encoder@58060000 {
1069                                 compatible = "ti,omap5-hdmi";
1070                                 reg = <0x58040000 0x200>,
1071                                       <0x58040200 0x80>,
1072                                       <0x58040300 0x80>,
1073                                       <0x58060000 0x19000>;
1074                                 reg-names = "wp", "pll", "phy", "core";
1075                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1076                                 status = "disabled";
1077                                 ti,hwmods = "dss_hdmi";
1078                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1079                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1080                                 clock-names = "fck", "sys_clk";
1081                                 dmas = <&sdma 76>;
1082                                 dma-names = "audio_tx";
1083                         };
1084                 };
1085
1086                 abb_mpu: regulator-abb-mpu {
1087                         compatible = "ti,abb-v2";
1088                         regulator-name = "abb_mpu";
1089                         #address-cells = <0>;
1090                         #size-cells = <0>;
1091                         clocks = <&sys_clkin>;
1092                         ti,settling-time = <50>;
1093                         ti,clock-cycles = <16>;
1094
1095                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1096                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1097                         reg-names = "base-address", "int-address",
1098                                     "efuse-address", "ldo-address";
1099                         ti,tranxdone-status-mask = <0x80>;
1100                         /* LDOVBBMPU_MUX_CTRL */
1101                         ti,ldovbb-override-mask = <0x400>;
1102                         /* LDOVBBMPU_VSET_OUT */
1103                         ti,ldovbb-vset-mask = <0x1F>;
1104
1105                         /*
1106                          * NOTE: only FBB mode used but actual vset will
1107                          * determine final biasing
1108                          */
1109                         ti,abb_info = <
1110                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1111                         1060000         0       0x0     0 0x02000000 0x01F00000
1112                         1250000         0       0x4     0 0x02000000 0x01F00000
1113                         >;
1114                 };
1115
1116                 abb_mm: regulator-abb-mm {
1117                         compatible = "ti,abb-v2";
1118                         regulator-name = "abb_mm";
1119                         #address-cells = <0>;
1120                         #size-cells = <0>;
1121                         clocks = <&sys_clkin>;
1122                         ti,settling-time = <50>;
1123                         ti,clock-cycles = <16>;
1124
1125                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1126                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1127                         reg-names = "base-address", "int-address",
1128                                     "efuse-address", "ldo-address";
1129                         ti,tranxdone-status-mask = <0x80000000>;
1130                         /* LDOVBBMM_MUX_CTRL */
1131                         ti,ldovbb-override-mask = <0x400>;
1132                         /* LDOVBBMM_VSET_OUT */
1133                         ti,ldovbb-vset-mask = <0x1F>;
1134
1135                         /*
1136                          * NOTE: only FBB mode used but actual vset will
1137                          * determine final biasing
1138                          */
1139                         ti,abb_info = <
1140                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1141                         1025000         0       0x0     0 0x02000000 0x01F00000
1142                         1120000         0       0x4     0 0x02000000 0x01F00000
1143                         >;
1144                 };
1145         };
1146 };
1147
1148 &cpu_thermal {
1149         polling-delay = <500>; /* milliseconds */
1150         coefficients = <65 (-1791)>;
1151 };
1152
1153 #include "omap54xx-clocks.dtsi"
1154
1155 &gpu_thermal {
1156         coefficients = <117 (-2992)>;
1157 };
1158
1159 &core_thermal {
1160         coefficients = <0 2000>;
1161 };