arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a9";
  37                         device_type = "cpu";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x0>;
  40
  41                         clocks = <&dpll_mpu_ck>;
  42                         clock-names = "cpu";
  43
  44                         clock-latency = <300000>; /* From omap-cpufreq driver */
  45                 };
  46                 cpu@1 {
  47                         compatible = "arm,cortex-a9";
  48                         device_type = "cpu";
  49                         next-level-cache = <&L2>;
  50                         reg = <0x1>;
  51                 };
  52         };
  53
  54         gic: interrupt-controller@48241000 {
  55                 compatible = "arm,cortex-a9-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 reg = <0x48241000 0x1000>,
  59                       <0x48240100 0x0100>;
  60                 interrupt-parent = <&gic>;
  61         };
  62
  63         L2: l2-cache-controller@48242000 {
  64                 compatible = "arm,pl310-cache";
  65                 reg = <0x48242000 0x1000>;
  66                 cache-unified;
  67                 cache-level = <2>;
  68         };
  69
  70         local-timer@48240600 {
  71                 compatible = "arm,cortex-a9-twd-timer";
  72                 clocks = <&mpu_periphclk>;
  73                 reg = <0x48240600 0x20>;
  74                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  75                 interrupt-parent = <&gic>;
  76         };
  77
  78         wakeupgen: interrupt-controller@48281000 {
  79                 compatible = "ti,omap4-wugen-mpu";
  80                 interrupt-controller;
  81                 #interrupt-cells = <3>;
  82                 reg = <0x48281000 0x1000>;
  83                 interrupt-parent = <&gic>;
  84         };
  85
  86         /*
  87          * The soc node represents the soc top level view. It is used for IPs
  88          * that are not memory mapped in the MPU view or for the MPU itself.
  89          */
  90         soc {
  91                 compatible = "ti,omap-infra";
  92                 mpu {
  93                         compatible = "ti,omap4-mpu";
  94                         ti,hwmods = "mpu";
  95                         sram = <&ocmcram>;
  96                 };
  97
  98                 dsp {
  99                         compatible = "ti,omap3-c64";
 100                         ti,hwmods = "dsp";
 101                 };
 102
 103                 iva {
 104                         compatible = "ti,ivahd";
 105                         ti,hwmods = "iva";
 106                 };
 107         };
 108
 109         /*
 110          * XXX: Use a flat representation of the OMAP4 interconnect.
 111          * The real OMAP interconnect network is quite complex.
 112          * Since it will not bring real advantage to represent that in DT for
 113          * the moment, just use a fake OCP bus entry to represent the whole bus
 114          * hierarchy.
 115          */
 116         ocp {
 117                 compatible = "ti,omap4-l3-noc", "simple-bus";
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 ranges;
 121                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 122                 reg = <0x44000000 0x1000>,
 123                       <0x44800000 0x2000>,
 124                       <0x45000000 0x1000>;
 125                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 127
 128                 l4_cfg: l4@4a000000 {
 129                         compatible = "ti,omap4-l4-cfg", "simple-bus";
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         ranges = <0 0x4a000000 0x1000000>;
 133
 134                         cm1: cm1@4000 {
 135                                 compatible = "ti,omap4-cm1";
 136                                 reg = <0x4000 0x2000>;
 137
 138                                 cm1_clocks: clocks {
 139                                         #address-cells = <1>;
 140                                         #size-cells = <0>;
 141                                 };
 142
 143                                 cm1_clockdomains: clockdomains {
 144                                 };
 145                         };
 146
 147                         cm2: cm2@8000 {
 148                                 compatible = "ti,omap4-cm2";
 149                                 reg = <0x8000 0x3000>;
 150
 151                                 cm2_clocks: clocks {
 152                                         #address-cells = <1>;
 153                                         #size-cells = <0>;
 154                                 };
 155
 156                                 cm2_clockdomains: clockdomains {
 157                                 };
 158                         };
 159
 160                         omap4_scm_core: scm@2000 {
 161                                 compatible = "ti,omap4-scm-core", "simple-bus";
 162                                 reg = <0x2000 0x1000>;
 163                                 #address-cells = <1>;
 164                                 #size-cells = <1>;
 165                                 ranges = <0 0x2000 0x1000>;
 166
 167                                 scm_conf: scm_conf@0 {
 168                                         compatible = "syscon";
 169                                         reg = <0x0 0x800>;
 170                                         #address-cells = <1>;
 171                                         #size-cells = <1>;
 172                                 };
 173                         };
 174
 175                         omap4_padconf_core: scm@100000 {
 176                                 compatible = "ti,omap4-scm-padconf-core",
 177                                              "simple-bus";
 178                                 #address-cells = <1>;
 179                                 #size-cells = <1>;
 180                                 ranges = <0 0x100000 0x1000>;
 181
 182                                 omap4_pmx_core: pinmux@40 {
 183                                         compatible = "ti,omap4-padconf",
 184                                                      "pinctrl-single";
 185                                         reg = <0x40 0x0196>;
 186                                         #address-cells = <1>;
 187                                         #size-cells = <0>;
 188                                         #pinctrl-cells = <1>;
 189                                         #interrupt-cells = <1>;
 190                                         interrupt-controller;
 191                                         pinctrl-single,register-width = <16>;
 192                                         pinctrl-single,function-mask = <0x7fff>;
 193                                 };
 194
 195                                 omap4_padconf_global: omap4_padconf_global@5a0 {
 196                                         compatible = "syscon",
 197                                                      "simple-bus";
 198                                         reg = <0x5a0 0x170>;
 199                                         #address-cells = <1>;
 200                                         #size-cells = <1>;
 201                                         ranges = <0 0x5a0 0x170>;
 202
 203                                         pbias_regulator: pbias_regulator@60 {
 204                                                 compatible = "ti,pbias-omap4", "ti,pbias-omap";
 205                                                 reg = <0x60 0x4>;
 206                                                 syscon = <&omap4_padconf_global>;
 207                                                 pbias_mmc_reg: pbias_mmc_omap4 {
 208                                                         regulator-name = "pbias_mmc_omap4";
 209                                                         regulator-min-microvolt = <1800000>;
 210                                                         regulator-max-microvolt = <3000000>;
 211                                                 };
 212                                         };
 213                                 };
 214                         };
 215
 216                         l4_wkup: l4@300000 {
 217                                 compatible = "ti,omap4-l4-wkup", "simple-bus";
 218                                 #address-cells = <1>;
 219                                 #size-cells = <1>;
 220                                 ranges = <0 0x300000 0x40000>;
 221
 222                                 counter32k: counter@4000 {
 223                                         compatible = "ti,omap-counter32k";
 224                                         reg = <0x4000 0x20>;
 225                                         ti,hwmods = "counter_32k";
 226                                 };
 227
 228                                 prm: prm@6000 {
 229                                         compatible = "ti,omap4-prm";
 230                                         reg = <0x6000 0x3000>;
 231                                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 232
 233                                         prm_clocks: clocks {
 234                                                 #address-cells = <1>;
 235                                                 #size-cells = <0>;
 236                                         };
 237
 238                                         prm_clockdomains: clockdomains {
 239                                         };
 240                                 };
 241
 242                                 scrm: scrm@a000 {
 243                                         compatible = "ti,omap4-scrm";
 244                                         reg = <0xa000 0x2000>;
 245
 246                                         scrm_clocks: clocks {
 247                                                 #address-cells = <1>;
 248                                                 #size-cells = <0>;
 249                                         };
 250
 251                                         scrm_clockdomains: clockdomains {
 252                                         };
 253                                 };
 254
 255                                 omap4_pmx_wkup: pinmux@1e040 {
 256                                         compatible = "ti,omap4-padconf",
 257                                                      "pinctrl-single";
 258                                         reg = <0x1e040 0x0038>;
 259                                         #address-cells = <1>;
 260                                         #size-cells = <0>;
 261                                         #pinctrl-cells = <1>;
 262                                         #interrupt-cells = <1>;
 263                                         interrupt-controller;
 264                                         pinctrl-single,register-width = <16>;
 265                                         pinctrl-single,function-mask = <0x7fff>;
 266                                 };
 267                         };
 268                 };
 269
 270                 ocmcram: ocmcram@40304000 {
 271                         compatible = "mmio-sram";
 272                         reg = <0x40304000 0xa000>; /* 40k */
 273                 };
 274
 275                 sdma: dma-controller@4a056000 {
 276                         compatible = "ti,omap4430-sdma";
 277                         reg = <0x4a056000 0x1000>;
 278                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 282                         #dma-cells = <1>;
 283                         dma-channels = <32>;
 284                         dma-requests = <127>;
 285                 };
 286
 287                 gpio1: gpio@4a310000 {
 288                         compatible = "ti,omap4-gpio";
 289                         reg = <0x4a310000 0x200>;
 290                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 291                         ti,hwmods = "gpio1";
 292                         ti,gpio-always-on;
 293                         gpio-controller;
 294                         #gpio-cells = <2>;
 295                         interrupt-controller;
 296                         #interrupt-cells = <2>;
 297                 };
 298
 299                 gpio2: gpio@48055000 {
 300                         compatible = "ti,omap4-gpio";
 301                         reg = <0x48055000 0x200>;
 302                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 303                         ti,hwmods = "gpio2";
 304                         gpio-controller;
 305                         #gpio-cells = <2>;
 306                         interrupt-controller;
 307                         #interrupt-cells = <2>;
 308                 };
 309
 310                 gpio3: gpio@48057000 {
 311                         compatible = "ti,omap4-gpio";
 312                         reg = <0x48057000 0x200>;
 313                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 314                         ti,hwmods = "gpio3";
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320
 321                 gpio4: gpio@48059000 {
 322                         compatible = "ti,omap4-gpio";
 323                         reg = <0x48059000 0x200>;
 324                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 325                         ti,hwmods = "gpio4";
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 gpio5: gpio@4805b000 {
 333                         compatible = "ti,omap4-gpio";
 334                         reg = <0x4805b000 0x200>;
 335                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 336                         ti,hwmods = "gpio5";
 337                         gpio-controller;
 338                         #gpio-cells = <2>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                 };
 342
 343                 gpio6: gpio@4805d000 {
 344                         compatible = "ti,omap4-gpio";
 345                         reg = <0x4805d000 0x200>;
 346                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 347                         ti,hwmods = "gpio6";
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353
 354                 elm: elm@48078000 {
 355                         compatible = "ti,am3352-elm";
 356                         reg = <0x48078000 0x2000>;
 357                         interrupts = <4>;
 358                         ti,hwmods = "elm";
 359                         status = "disabled";
 360                 };
 361
 362                 gpmc: gpmc@50000000 {
 363                         compatible = "ti,omap4430-gpmc";
 364                         reg = <0x50000000 0x1000>;
 365                         #address-cells = <2>;
 366                         #size-cells = <1>;
 367                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 368                         dmas = <&sdma 4>;
 369                         dma-names = "rxtx";
 370                         gpmc,num-cs = <8>;
 371                         gpmc,num-waitpins = <4>;
 372                         ti,hwmods = "gpmc";
 373                         ti,no-idle-on-init;
 374                         clocks = <&l3_div_ck>;
 375                         clock-names = "fck";
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                 };
 381
 382                 uart1: serial@4806a000 {
 383                         compatible = "ti,omap4-uart";
 384                         reg = <0x4806a000 0x100>;
 385                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 386                         ti,hwmods = "uart1";
 387                         clock-frequency = <48000000>;
 388                 };
 389
 390                 uart2: serial@4806c000 {
 391                         compatible = "ti,omap4-uart";
 392                         reg = <0x4806c000 0x100>;
 393                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 394                         ti,hwmods = "uart2";
 395                         clock-frequency = <48000000>;
 396                 };
 397
 398                 uart3: serial@48020000 {
 399                         compatible = "ti,omap4-uart";
 400                         reg = <0x48020000 0x100>;
 401                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 402                         ti,hwmods = "uart3";
 403                         clock-frequency = <48000000>;
 404                 };
 405
 406                 uart4: serial@4806e000 {
 407                         compatible = "ti,omap4-uart";
 408                         reg = <0x4806e000 0x100>;
 409                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 410                         ti,hwmods = "uart4";
 411                         clock-frequency = <48000000>;
 412                 };
 413
 414                 hwspinlock: spinlock@4a0f6000 {
 415                         compatible = "ti,omap4-hwspinlock";
 416                         reg = <0x4a0f6000 0x1000>;
 417                         ti,hwmods = "spinlock";
 418                         #hwlock-cells = <1>;
 419                 };
 420
 421                 i2c1: i2c@48070000 {
 422                         compatible = "ti,omap4-i2c";
 423                         reg = <0x48070000 0x100>;
 424                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         ti,hwmods = "i2c1";
 428                 };
 429
 430                 i2c2: i2c@48072000 {
 431                         compatible = "ti,omap4-i2c";
 432                         reg = <0x48072000 0x100>;
 433                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         ti,hwmods = "i2c2";
 437                 };
 438
 439                 i2c3: i2c@48060000 {
 440                         compatible = "ti,omap4-i2c";
 441                         reg = <0x48060000 0x100>;
 442                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         ti,hwmods = "i2c3";
 446                 };
 447
 448                 i2c4: i2c@48350000 {
 449                         compatible = "ti,omap4-i2c";
 450                         reg = <0x48350000 0x100>;
 451                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         ti,hwmods = "i2c4";
 455                 };
 456
 457                 mcspi1: spi@48098000 {
 458                         compatible = "ti,omap4-mcspi";
 459                         reg = <0x48098000 0x200>;
 460                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         ti,hwmods = "mcspi1";
 464                         ti,spi-num-cs = <4>;
 465                         dmas = <&sdma 35>,
 466                                <&sdma 36>,
 467                                <&sdma 37>,
 468                                <&sdma 38>,
 469                                <&sdma 39>,
 470                                <&sdma 40>,
 471                                <&sdma 41>,
 472                                <&sdma 42>;
 473                         dma-names = "tx0", "rx0", "tx1", "rx1",
 474                                     "tx2", "rx2", "tx3", "rx3";
 475                 };
 476
 477                 mcspi2: spi@4809a000 {
 478                         compatible = "ti,omap4-mcspi";
 479                         reg = <0x4809a000 0x200>;
 480                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         ti,hwmods = "mcspi2";
 484                         ti,spi-num-cs = <2>;
 485                         dmas = <&sdma 43>,
 486                                <&sdma 44>,
 487                                <&sdma 45>,
 488                                <&sdma 46>;
 489                         dma-names = "tx0", "rx0", "tx1", "rx1";
 490                 };
 491
 492                 mcspi3: spi@480b8000 {
 493                         compatible = "ti,omap4-mcspi";
 494                         reg = <0x480b8000 0x200>;
 495                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         ti,hwmods = "mcspi3";
 499                         ti,spi-num-cs = <2>;
 500                         dmas = <&sdma 15>, <&sdma 16>;
 501                         dma-names = "tx0", "rx0";
 502                 };
 503
 504                 mcspi4: spi@480ba000 {
 505                         compatible = "ti,omap4-mcspi";
 506                         reg = <0x480ba000 0x200>;
 507                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         ti,hwmods = "mcspi4";
 511                         ti,spi-num-cs = <1>;
 512                         dmas = <&sdma 70>, <&sdma 71>;
 513                         dma-names = "tx0", "rx0";
 514                 };
 515
 516                 mmc1: mmc@4809c000 {
 517                         compatible = "ti,omap4-hsmmc";
 518                         reg = <0x4809c000 0x400>;
 519                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mmc1";
 521                         ti,dual-volt;
 522                         ti,needs-special-reset;
 523                         dmas = <&sdma 61>, <&sdma 62>;
 524                         dma-names = "tx", "rx";
 525                         pbias-supply = <&pbias_mmc_reg>;
 526                 };
 527
 528                 mmc2: mmc@480b4000 {
 529                         compatible = "ti,omap4-hsmmc";
 530                         reg = <0x480b4000 0x400>;
 531                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 532                         ti,hwmods = "mmc2";
 533                         ti,needs-special-reset;
 534                         dmas = <&sdma 47>, <&sdma 48>;
 535                         dma-names = "tx", "rx";
 536                 };
 537
 538                 mmc3: mmc@480ad000 {
 539                         compatible = "ti,omap4-hsmmc";
 540                         reg = <0x480ad000 0x400>;
 541                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 542                         ti,hwmods = "mmc3";
 543                         ti,needs-special-reset;
 544                         dmas = <&sdma 77>, <&sdma 78>;
 545                         dma-names = "tx", "rx";
 546                 };
 547
 548                 mmc4: mmc@480d1000 {
 549                         compatible = "ti,omap4-hsmmc";
 550                         reg = <0x480d1000 0x400>;
 551                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "mmc4";
 553                         ti,needs-special-reset;
 554                         dmas = <&sdma 57>, <&sdma 58>;
 555                         dma-names = "tx", "rx";
 556                 };
 557
 558                 mmc5: mmc@480d5000 {
 559                         compatible = "ti,omap4-hsmmc";
 560                         reg = <0x480d5000 0x400>;
 561                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "mmc5";
 563                         ti,needs-special-reset;
 564                         dmas = <&sdma 59>, <&sdma 60>;
 565                         dma-names = "tx", "rx";
 566                 };
 567
 568                 mmu_dsp: mmu@4a066000 {
 569                         compatible = "ti,omap4-iommu";
 570                         reg = <0x4a066000 0x100>;
 571                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 572                         ti,hwmods = "mmu_dsp";
 573                         #iommu-cells = <0>;
 574                 };
 575
 576                 mmu_ipu: mmu@55082000 {
 577                         compatible = "ti,omap4-iommu";
 578                         reg = <0x55082000 0x100>;
 579                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 580                         ti,hwmods = "mmu_ipu";
 581                         #iommu-cells = <0>;
 582                         ti,iommu-bus-err-back;
 583                 };
 584
 585                 wdt2: wdt@4a314000 {
 586                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 587                         reg = <0x4a314000 0x80>;
 588                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 589                         ti,hwmods = "wd_timer2";
 590                 };
 591
 592                 mcpdm: mcpdm@40132000 {
 593                         compatible = "ti,omap4-mcpdm";
 594                         reg = <0x40132000 0x7f>, /* MPU private access */
 595                               <0x49032000 0x7f>; /* L3 Interconnect */
 596                         reg-names = "mpu", "dma";
 597                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 598                         ti,hwmods = "mcpdm";
 599                         dmas = <&sdma 65>,
 600                                <&sdma 66>;
 601                         dma-names = "up_link", "dn_link";
 602                         status = "disabled";
 603                 };
 604
 605                 dmic: dmic@4012e000 {
 606                         compatible = "ti,omap4-dmic";
 607                         reg = <0x4012e000 0x7f>, /* MPU private access */
 608                               <0x4902e000 0x7f>; /* L3 Interconnect */
 609                         reg-names = "mpu", "dma";
 610                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 611                         ti,hwmods = "dmic";
 612                         dmas = <&sdma 67>;
 613                         dma-names = "up_link";
 614                         status = "disabled";
 615                 };
 616
 617                 mcbsp1: mcbsp@40122000 {
 618                         compatible = "ti,omap4-mcbsp";
 619                         reg = <0x40122000 0xff>, /* MPU private access */
 620                               <0x49022000 0xff>; /* L3 Interconnect */
 621                         reg-names = "mpu", "dma";
 622                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 623                         interrupt-names = "common";
 624                         ti,buffer-size = <128>;
 625                         ti,hwmods = "mcbsp1";
 626                         dmas = <&sdma 33>,
 627                                <&sdma 34>;
 628                         dma-names = "tx", "rx";
 629                         status = "disabled";
 630                 };
 631
 632                 mcbsp2: mcbsp@40124000 {
 633                         compatible = "ti,omap4-mcbsp";
 634                         reg = <0x40124000 0xff>, /* MPU private access */
 635                               <0x49024000 0xff>; /* L3 Interconnect */
 636                         reg-names = "mpu", "dma";
 637                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 638                         interrupt-names = "common";
 639                         ti,buffer-size = <128>;
 640                         ti,hwmods = "mcbsp2";
 641                         dmas = <&sdma 17>,
 642                                <&sdma 18>;
 643                         dma-names = "tx", "rx";
 644                         status = "disabled";
 645                 };
 646
 647                 mcbsp3: mcbsp@40126000 {
 648                         compatible = "ti,omap4-mcbsp";
 649                         reg = <0x40126000 0xff>, /* MPU private access */
 650                               <0x49026000 0xff>; /* L3 Interconnect */
 651                         reg-names = "mpu", "dma";
 652                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 653                         interrupt-names = "common";
 654                         ti,buffer-size = <128>;
 655                         ti,hwmods = "mcbsp3";
 656                         dmas = <&sdma 19>,
 657                                <&sdma 20>;
 658                         dma-names = "tx", "rx";
 659                         status = "disabled";
 660                 };
 661
 662                 mcbsp4: mcbsp@48096000 {
 663                         compatible = "ti,omap4-mcbsp";
 664                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 665                         reg-names = "mpu";
 666                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 667                         interrupt-names = "common";
 668                         ti,buffer-size = <128>;
 669                         ti,hwmods = "mcbsp4";
 670                         dmas = <&sdma 31>,
 671                                <&sdma 32>;
 672                         dma-names = "tx", "rx";
 673                         status = "disabled";
 674                 };
 675
 676                 keypad: keypad@4a31c000 {
 677                         compatible = "ti,omap4-keypad";
 678                         reg = <0x4a31c000 0x80>;
 679                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 680                         reg-names = "mpu";
 681                         ti,hwmods = "kbd";
 682                 };
 683
 684                 dmm@4e000000 {
 685                         compatible = "ti,omap4-dmm";
 686                         reg = <0x4e000000 0x800>;
 687                         interrupts = <0 113 0x4>;
 688                         ti,hwmods = "dmm";
 689                 };
 690
 691                 emif1: emif@4c000000 {
 692                         compatible = "ti,emif-4d";
 693                         reg = <0x4c000000 0x100>;
 694                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "emif1";
 696                         ti,no-idle-on-init;
 697                         phy-type = <1>;
 698                         hw-caps-read-idle-ctrl;
 699                         hw-caps-ll-interface;
 700                         hw-caps-temp-alert;
 701                 };
 702
 703                 emif2: emif@4d000000 {
 704                         compatible = "ti,emif-4d";
 705                         reg = <0x4d000000 0x100>;
 706                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 707                         ti,hwmods = "emif2";
 708                         ti,no-idle-on-init;
 709                         phy-type = <1>;
 710                         hw-caps-read-idle-ctrl;
 711                         hw-caps-ll-interface;
 712                         hw-caps-temp-alert;
 713                 };
 714
 715                 ocp2scp@4a0ad000 {
 716                         compatible = "ti,omap-ocp2scp";
 717                         reg = <0x4a0ad000 0x1f>;
 718                         #address-cells = <1>;
 719                         #size-cells = <1>;
 720                         ranges;
 721                         ti,hwmods = "ocp2scp_usb_phy";
 722                         usb2_phy: usb2phy@4a0ad080 {
 723                                 compatible = "ti,omap-usb2";
 724                                 reg = <0x4a0ad080 0x58>;
 725                                 ctrl-module = <&omap_control_usb2phy>;
 726                                 clocks = <&usb_phy_cm_clk32k>;
 727                                 clock-names = "wkupclk";
 728                                 #phy-cells = <0>;
 729                         };
 730                 };
 731
 732                 mailbox: mailbox@4a0f4000 {
 733                         compatible = "ti,omap4-mailbox";
 734                         reg = <0x4a0f4000 0x200>;
 735                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 736                         ti,hwmods = "mailbox";
 737                         #mbox-cells = <1>;
 738                         ti,mbox-num-users = <3>;
 739                         ti,mbox-num-fifos = <8>;
 740                         mbox_ipu: mbox_ipu {
 741                                 ti,mbox-tx = <0 0 0>;
 742                                 ti,mbox-rx = <1 0 0>;
 743                         };
 744                         mbox_dsp: mbox_dsp {
 745                                 ti,mbox-tx = <3 0 0>;
 746                                 ti,mbox-rx = <2 0 0>;
 747                         };
 748                 };
 749
 750                 timer1: timer@4a318000 {
 751                         compatible = "ti,omap3430-timer";
 752                         reg = <0x4a318000 0x80>;
 753                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 754                         ti,hwmods = "timer1";
 755                         ti,timer-alwon;
 756                 };
 757
 758                 timer2: timer@48032000 {
 759                         compatible = "ti,omap3430-timer";
 760                         reg = <0x48032000 0x80>;
 761                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "timer2";
 763                 };
 764
 765                 timer3: timer@48034000 {
 766                         compatible = "ti,omap4430-timer";
 767                         reg = <0x48034000 0x80>;
 768                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 769                         ti,hwmods = "timer3";
 770                 };
 771
 772                 timer4: timer@48036000 {
 773                         compatible = "ti,omap4430-timer";
 774                         reg = <0x48036000 0x80>;
 775                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "timer4";
 777                 };
 778
 779                 timer5: timer@40138000 {
 780                         compatible = "ti,omap4430-timer";
 781                         reg = <0x40138000 0x80>,
 782                               <0x49038000 0x80>;
 783                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 784                         ti,hwmods = "timer5";
 785                         ti,timer-dsp;
 786                 };
 787
 788                 timer6: timer@4013a000 {
 789                         compatible = "ti,omap4430-timer";
 790                         reg = <0x4013a000 0x80>,
 791                               <0x4903a000 0x80>;
 792                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 793                         ti,hwmods = "timer6";
 794                         ti,timer-dsp;
 795                 };
 796
 797                 timer7: timer@4013c000 {
 798                         compatible = "ti,omap4430-timer";
 799                         reg = <0x4013c000 0x80>,
 800                               <0x4903c000 0x80>;
 801                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 802                         ti,hwmods = "timer7";
 803                         ti,timer-dsp;
 804                 };
 805
 806                 timer8: timer@4013e000 {
 807                         compatible = "ti,omap4430-timer";
 808                         reg = <0x4013e000 0x80>,
 809                               <0x4903e000 0x80>;
 810                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 811                         ti,hwmods = "timer8";
 812                         ti,timer-pwm;
 813                         ti,timer-dsp;
 814                 };
 815
 816                 timer9: timer@4803e000 {
 817                         compatible = "ti,omap4430-timer";
 818                         reg = <0x4803e000 0x80>;
 819                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 820                         ti,hwmods = "timer9";
 821                         ti,timer-pwm;
 822                 };
 823
 824                 timer10: timer@48086000 {
 825                         compatible = "ti,omap3430-timer";
 826                         reg = <0x48086000 0x80>;
 827                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 828                         ti,hwmods = "timer10";
 829                         ti,timer-pwm;
 830                 };
 831
 832                 timer11: timer@48088000 {
 833                         compatible = "ti,omap4430-timer";
 834                         reg = <0x48088000 0x80>;
 835                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 836                         ti,hwmods = "timer11";
 837                         ti,timer-pwm;
 838                 };
 839
 840                 usbhstll: usbhstll@4a062000 {
 841                         compatible = "ti,usbhs-tll";
 842                         reg = <0x4a062000 0x1000>;
 843                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 844                         ti,hwmods = "usb_tll_hs";
 845                 };
 846
 847                 usbhshost: usbhshost@4a064000 {
 848                         compatible = "ti,usbhs-host";
 849                         reg = <0x4a064000 0x800>;
 850                         ti,hwmods = "usb_host_hs";
 851                         #address-cells = <1>;
 852                         #size-cells = <1>;
 853                         ranges;
 854                         clocks = <&init_60m_fclk>,
 855                                  <&xclk60mhsp1_ck>,
 856                                  <&xclk60mhsp2_ck>;
 857                         clock-names = "refclk_60m_int",
 858                                       "refclk_60m_ext_p1",
 859                                       "refclk_60m_ext_p2";
 860
 861                         usbhsohci: ohci@4a064800 {
 862                                 compatible = "ti,ohci-omap3";
 863                                 reg = <0x4a064800 0x400>;
 864                                 interrupt-parent = <&gic>;
 865                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 866                         };
 867
 868                         usbhsehci: ehci@4a064c00 {
 869                                 compatible = "ti,ehci-omap";
 870                                 reg = <0x4a064c00 0x400>;
 871                                 interrupt-parent = <&gic>;
 872                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 873                         };
 874                 };
 875
 876                 omap_control_usb2phy: control-phy@4a002300 {
 877                         compatible = "ti,control-phy-usb2";
 878                         reg = <0x4a002300 0x4>;
 879                         reg-names = "power";
 880                 };
 881
 882                 omap_control_usbotg: control-phy@4a00233c {
 883                         compatible = "ti,control-phy-otghs";
 884                         reg = <0x4a00233c 0x4>;
 885                         reg-names = "otghs_control";
 886                 };
 887
 888                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 889                         compatible = "ti,omap4-musb";
 890                         reg = <0x4a0ab000 0x7ff>;
 891                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 892                         interrupt-names = "mc", "dma";
 893                         ti,hwmods = "usb_otg_hs";
 894                         usb-phy = <&usb2_phy>;
 895                         phys = <&usb2_phy>;
 896                         phy-names = "usb2-phy";
 897                         multipoint = <1>;
 898                         num-eps = <16>;
 899                         ram-bits = <12>;
 900                         ctrl-module = <&omap_control_usbotg>;
 901                 };
 902
 903                 aes1: aes@4b501000 {
 904                         compatible = "ti,omap4-aes";
 905                         ti,hwmods = "aes1";
 906                         reg = <0x4b501000 0xa0>;
 907                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 908                         dmas = <&sdma 111>, <&sdma 110>;
 909                         dma-names = "tx", "rx";
 910                 };
 911
 912                 aes2: aes@4b701000 {
 913                         compatible = "ti,omap4-aes";
 914                         ti,hwmods = "aes2";
 915                         reg = <0x4b701000 0xa0>;
 916                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 917                         dmas = <&sdma 114>, <&sdma 113>;
 918                         dma-names = "tx", "rx";
 919                 };
 920
 921                 des: des@480a5000 {
 922                         compatible = "ti,omap4-des";
 923                         ti,hwmods = "des";
 924                         reg = <0x480a5000 0xa0>;
 925                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 926                         dmas = <&sdma 117>, <&sdma 116>;
 927                         dma-names = "tx", "rx";
 928                 };
 929
 930                 sham: sham@4b100000 {
 931                         compatible = "ti,omap4-sham";
 932                         ti,hwmods = "sham";
 933                         reg = <0x4b100000 0x300>;
 934                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 935                         dmas = <&sdma 119>;
 936                         dma-names = "rx";
 937                 };
 938
 939                 abb_mpu: regulator-abb-mpu {
 940                         compatible = "ti,abb-v2";
 941                         regulator-name = "abb_mpu";
 942                         #address-cells = <0>;
 943                         #size-cells = <0>;
 944                         ti,tranxdone-status-mask = <0x80>;
 945                         clocks = <&sys_clkin_ck>;
 946                         ti,settling-time = <50>;
 947                         ti,clock-cycles = <16>;
 948
 949                         status = "disabled";
 950                 };
 951
 952                 abb_iva: regulator-abb-iva {
 953                         compatible = "ti,abb-v2";
 954                         regulator-name = "abb_iva";
 955                         #address-cells = <0>;
 956                         #size-cells = <0>;
 957                         ti,tranxdone-status-mask = <0x80000000>;
 958                         clocks = <&sys_clkin_ck>;
 959                         ti,settling-time = <50>;
 960                         ti,clock-cycles = <16>;
 961
 962                         status = "disabled";
 963                 };
 964
 965                 dss: dss@58000000 {
 966                         compatible = "ti,omap4-dss";
 967                         reg = <0x58000000 0x80>;
 968                         status = "disabled";
 969                         ti,hwmods = "dss_core";
 970                         clocks = <&dss_dss_clk>;
 971                         clock-names = "fck";
 972                         #address-cells = <1>;
 973                         #size-cells = <1>;
 974                         ranges;
 975
 976                         dispc@58001000 {
 977                                 compatible = "ti,omap4-dispc";
 978                                 reg = <0x58001000 0x1000>;
 979                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 980                                 ti,hwmods = "dss_dispc";
 981                                 clocks = <&dss_dss_clk>;
 982                                 clock-names = "fck";
 983                         };
 984
 985                         rfbi: encoder@58002000  {
 986                                 compatible = "ti,omap4-rfbi";
 987                                 reg = <0x58002000 0x1000>;
 988                                 status = "disabled";
 989                                 ti,hwmods = "dss_rfbi";
 990                                 clocks = <&dss_dss_clk>, <&l3_div_ck>;
 991                                 clock-names = "fck", "ick";
 992                         };
 993
 994                         venc: encoder@58003000 {
 995                                 compatible = "ti,omap4-venc";
 996                                 reg = <0x58003000 0x1000>;
 997                                 status = "disabled";
 998                                 ti,hwmods = "dss_venc";
 999                                 clocks = <&dss_tv_clk>;
1000                                 clock-names = "fck";
1001                         };
1002
1003                         dsi1: encoder@58004000 {
1004                                 compatible = "ti,omap4-dsi";
1005                                 reg = <0x58004000 0x200>,
1006                                       <0x58004200 0x40>,
1007                                       <0x58004300 0x20>;
1008                                 reg-names = "proto", "phy", "pll";
1009                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1010                                 status = "disabled";
1011                                 ti,hwmods = "dss_dsi1";
1012                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1013                                 clock-names = "fck", "sys_clk";
1014                         };
1015
1016                         dsi2: encoder@58005000 {
1017                                 compatible = "ti,omap4-dsi";
1018                                 reg = <0x58005000 0x200>,
1019                                       <0x58005200 0x40>,
1020                                       <0x58005300 0x20>;
1021                                 reg-names = "proto", "phy", "pll";
1022                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1023                                 status = "disabled";
1024                                 ti,hwmods = "dss_dsi2";
1025                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1026                                 clock-names = "fck", "sys_clk";
1027                         };
1028
1029                         hdmi: encoder@58006000 {
1030                                 compatible = "ti,omap4-hdmi";
1031                                 reg = <0x58006000 0x200>,
1032                                       <0x58006200 0x100>,
1033                                       <0x58006300 0x100>,
1034                                       <0x58006400 0x1000>;
1035                                 reg-names = "wp", "pll", "phy", "core";
1036                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1037                                 status = "disabled";
1038                                 ti,hwmods = "dss_hdmi";
1039                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1040                                 clock-names = "fck", "sys_clk";
1041                                 dmas = <&sdma 76>;
1042                                 dma-names = "audio_tx";
1043                         };
1044                 };
1045         };
1046 };
1047
1048 /include/ "omap44xx-clocks.dtsi"