arch/arm/boot/dts/omap3xxx-clocks.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &prm_clocks {
  11         virt_16_8m_ck: virt_16_8m_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <16800000>;
  15         };
  16
  17         osc_sys_ck: osc_sys_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,mux-clock";
  20                 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
  21                 reg = <0x0d40>;
  22         };
  23
  24         sys_ck: sys_ck {
  25                 #clock-cells = <0>;
  26                 compatible = "ti,divider-clock";
  27                 clocks = <&osc_sys_ck>;
  28                 ti,bit-shift = <6>;
  29                 ti,max-div = <3>;
  30                 reg = <0x1270>;
  31                 ti,index-starts-at-one;
  32         };
  33
  34         sys_clkout1: sys_clkout1 {
  35                 #clock-cells = <0>;
  36                 compatible = "ti,gate-clock";
  37                 clocks = <&osc_sys_ck>;
  38                 reg = <0x0d70>;
  39                 ti,bit-shift = <7>;
  40         };
  41
  42         dpll3_x2_ck: dpll3_x2_ck {
  43                 #clock-cells = <0>;
  44                 compatible = "fixed-factor-clock";
  45                 clocks = <&dpll3_ck>;
  46                 clock-mult = <2>;
  47                 clock-div = <1>;
  48         };
  49
  50         dpll3_m2x2_ck: dpll3_m2x2_ck {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-factor-clock";
  53                 clocks = <&dpll3_m2_ck>;
  54                 clock-mult = <2>;
  55                 clock-div = <1>;
  56         };
  57
  58         dpll4_x2_ck: dpll4_x2_ck {
  59                 #clock-cells = <0>;
  60                 compatible = "fixed-factor-clock";
  61                 clocks = <&dpll4_ck>;
  62                 clock-mult = <2>;
  63                 clock-div = <1>;
  64         };
  65
  66         corex2_fck: corex2_fck {
  67                 #clock-cells = <0>;
  68                 compatible = "fixed-factor-clock";
  69                 clocks = <&dpll3_m2x2_ck>;
  70                 clock-mult = <1>;
  71                 clock-div = <1>;
  72         };
  73
  74         wkup_l4_ick: wkup_l4_ick {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-factor-clock";
  77                 clocks = <&sys_ck>;
  78                 clock-mult = <1>;
  79                 clock-div = <1>;
  80         };
  81 };
  82 &scrm_clocks {
  83         mcbsp5_mux_fck: mcbsp5_mux_fck {
  84                 #clock-cells = <0>;
  85                 compatible = "ti,composite-mux-clock";
  86                 clocks = <&core_96m_fck>, <&mcbsp_clks>;
  87                 ti,bit-shift = <4>;
  88                 reg = <0x02d8>;
  89         };
  90
  91         mcbsp5_fck: mcbsp5_fck {
  92                 #clock-cells = <0>;
  93                 compatible = "ti,composite-clock";
  94                 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
  95         };
  96
  97         mcbsp1_mux_fck: mcbsp1_mux_fck {
  98                 #clock-cells = <0>;
  99                 compatible = "ti,composite-mux-clock";
 100                 clocks = <&core_96m_fck>, <&mcbsp_clks>;
 101                 ti,bit-shift = <2>;
 102                 reg = <0x0274>;
 103         };
 104
 105         mcbsp1_fck: mcbsp1_fck {
 106                 #clock-cells = <0>;
 107                 compatible = "ti,composite-clock";
 108                 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
 109         };
 110
 111         mcbsp2_mux_fck: mcbsp2_mux_fck {
 112                 #clock-cells = <0>;
 113                 compatible = "ti,composite-mux-clock";
 114                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
 115                 ti,bit-shift = <6>;
 116                 reg = <0x0274>;
 117         };
 118
 119         mcbsp2_fck: mcbsp2_fck {
 120                 #clock-cells = <0>;
 121                 compatible = "ti,composite-clock";
 122                 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
 123         };
 124
 125         mcbsp3_mux_fck: mcbsp3_mux_fck {
 126                 #clock-cells = <0>;
 127                 compatible = "ti,composite-mux-clock";
 128                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
 129                 reg = <0x02d8>;
 130         };
 131
 132         mcbsp3_fck: mcbsp3_fck {
 133                 #clock-cells = <0>;
 134                 compatible = "ti,composite-clock";
 135                 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
 136         };
 137
 138         mcbsp4_mux_fck: mcbsp4_mux_fck {
 139                 #clock-cells = <0>;
 140                 compatible = "ti,composite-mux-clock";
 141                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
 142                 ti,bit-shift = <2>;
 143                 reg = <0x02d8>;
 144         };
 145
 146         mcbsp4_fck: mcbsp4_fck {
 147                 #clock-cells = <0>;
 148                 compatible = "ti,composite-clock";
 149                 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
 150         };
 151 };
 152 &cm_clocks {
 153         dummy_apb_pclk: dummy_apb_pclk {
 154                 #clock-cells = <0>;
 155                 compatible = "fixed-clock";
 156                 clock-frequency = <0x0>;
 157         };
 158
 159         omap_32k_fck: omap_32k_fck {
 160                 #clock-cells = <0>;
 161                 compatible = "fixed-clock";
 162                 clock-frequency = <32768>;
 163         };
 164
 165         virt_12m_ck: virt_12m_ck {
 166                 #clock-cells = <0>;
 167                 compatible = "fixed-clock";
 168                 clock-frequency = <12000000>;
 169         };
 170
 171         virt_13m_ck: virt_13m_ck {
 172                 #clock-cells = <0>;
 173                 compatible = "fixed-clock";
 174                 clock-frequency = <13000000>;
 175         };
 176
 177         virt_19200000_ck: virt_19200000_ck {
 178                 #clock-cells = <0>;
 179                 compatible = "fixed-clock";
 180                 clock-frequency = <19200000>;
 181         };
 182
 183         virt_26000000_ck: virt_26000000_ck {
 184                 #clock-cells = <0>;
 185                 compatible = "fixed-clock";
 186                 clock-frequency = <26000000>;
 187         };
 188
 189         virt_38_4m_ck: virt_38_4m_ck {
 190                 #clock-cells = <0>;
 191                 compatible = "fixed-clock";
 192                 clock-frequency = <38400000>;
 193         };
 194
 195         dpll4_ck: dpll4_ck {
 196                 #clock-cells = <0>;
 197                 compatible = "ti,omap3-dpll-per-clock";
 198                 clocks = <&sys_ck>, <&sys_ck>;
 199                 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
 200         };
 201
 202         dpll4_m2_ck: dpll4_m2_ck {
 203                 #clock-cells = <0>;
 204                 compatible = "ti,divider-clock";
 205                 clocks = <&dpll4_ck>;
 206                 ti,max-div = <63>;
 207                 reg = <0x0d48>;
 208                 ti,index-starts-at-one;
 209         };
 210
 211         dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
 212                 #clock-cells = <0>;
 213                 compatible = "fixed-factor-clock";
 214                 clocks = <&dpll4_m2_ck>;
 215                 clock-mult = <2>;
 216                 clock-div = <1>;
 217         };
 218
 219         dpll4_m2x2_ck: dpll4_m2x2_ck {
 220                 #clock-cells = <0>;
 221                 compatible = "ti,gate-clock";
 222                 clocks = <&dpll4_m2x2_mul_ck>;
 223                 ti,bit-shift = <0x1b>;
 224                 reg = <0x0d00>;
 225                 ti,set-bit-to-disable;
 226         };
 227
 228         omap_96m_alwon_fck: omap_96m_alwon_fck {
 229                 #clock-cells = <0>;
 230                 compatible = "fixed-factor-clock";
 231                 clocks = <&dpll4_m2x2_ck>;
 232                 clock-mult = <1>;
 233                 clock-div = <1>;
 234         };
 235
 236         dpll3_ck: dpll3_ck {
 237                 #clock-cells = <0>;
 238                 compatible = "ti,omap3-dpll-core-clock";
 239                 clocks = <&sys_ck>, <&sys_ck>;
 240                 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
 241         };
 242
 243         dpll3_m3_ck: dpll3_m3_ck {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,divider-clock";
 246                 clocks = <&dpll3_ck>;
 247                 ti,bit-shift = <16>;
 248                 ti,max-div = <31>;
 249                 reg = <0x1140>;
 250                 ti,index-starts-at-one;
 251         };
 252
 253         dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
 254                 #clock-cells = <0>;
 255                 compatible = "fixed-factor-clock";
 256                 clocks = <&dpll3_m3_ck>;
 257                 clock-mult = <2>;
 258                 clock-div = <1>;
 259         };
 260
 261         dpll3_m3x2_ck: dpll3_m3x2_ck {
 262                 #clock-cells = <0>;
 263                 compatible = "ti,gate-clock";
 264                 clocks = <&dpll3_m3x2_mul_ck>;
 265                 ti,bit-shift = <0xc>;
 266                 reg = <0x0d00>;
 267                 ti,set-bit-to-disable;
 268         };
 269
 270         emu_core_alwon_ck: emu_core_alwon_ck {
 271                 #clock-cells = <0>;
 272                 compatible = "fixed-factor-clock";
 273                 clocks = <&dpll3_m3x2_ck>;
 274                 clock-mult = <1>;
 275                 clock-div = <1>;
 276         };
 277
 278         sys_altclk: sys_altclk {
 279                 #clock-cells = <0>;
 280                 compatible = "fixed-clock";
 281                 clock-frequency = <0x0>;
 282         };
 283
 284         mcbsp_clks: mcbsp_clks {
 285                 #clock-cells = <0>;
 286                 compatible = "fixed-clock";
 287                 clock-frequency = <0x0>;
 288         };
 289
 290         dpll3_m2_ck: dpll3_m2_ck {
 291                 #clock-cells = <0>;
 292                 compatible = "ti,divider-clock";
 293                 clocks = <&dpll3_ck>;
 294                 ti,bit-shift = <27>;
 295                 ti,max-div = <31>;
 296                 reg = <0x0d40>;
 297                 ti,index-starts-at-one;
 298         };
 299
 300         core_ck: core_ck {
 301                 #clock-cells = <0>;
 302                 compatible = "fixed-factor-clock";
 303                 clocks = <&dpll3_m2_ck>;
 304                 clock-mult = <1>;
 305                 clock-div = <1>;
 306         };
 307
 308         dpll1_fck: dpll1_fck {
 309                 #clock-cells = <0>;
 310                 compatible = "ti,divider-clock";
 311                 clocks = <&core_ck>;
 312                 ti,bit-shift = <19>;
 313                 ti,max-div = <7>;
 314                 reg = <0x0940>;
 315                 ti,index-starts-at-one;
 316         };
 317
 318         dpll1_ck: dpll1_ck {
 319                 #clock-cells = <0>;
 320                 compatible = "ti,omap3-dpll-clock";
 321                 clocks = <&sys_ck>, <&dpll1_fck>;
 322                 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
 323         };
 324
 325         dpll1_x2_ck: dpll1_x2_ck {
 326                 #clock-cells = <0>;
 327                 compatible = "fixed-factor-clock";
 328                 clocks = <&dpll1_ck>;
 329                 clock-mult = <2>;
 330                 clock-div = <1>;
 331         };
 332
 333         dpll1_x2m2_ck: dpll1_x2m2_ck {
 334                 #clock-cells = <0>;
 335                 compatible = "ti,divider-clock";
 336                 clocks = <&dpll1_x2_ck>;
 337                 ti,max-div = <31>;
 338                 reg = <0x0944>;
 339                 ti,index-starts-at-one;
 340         };
 341
 342         cm_96m_fck: cm_96m_fck {
 343                 #clock-cells = <0>;
 344                 compatible = "fixed-factor-clock";
 345                 clocks = <&omap_96m_alwon_fck>;
 346                 clock-mult = <1>;
 347                 clock-div = <1>;
 348         };
 349
 350         omap_96m_fck: omap_96m_fck {
 351                 #clock-cells = <0>;
 352                 compatible = "ti,mux-clock";
 353                 clocks = <&cm_96m_fck>, <&sys_ck>;
 354                 ti,bit-shift = <6>;
 355                 reg = <0x0d40>;
 356         };
 357
 358         dpll4_m3_ck: dpll4_m3_ck {
 359                 #clock-cells = <0>;
 360                 compatible = "ti,divider-clock";
 361                 clocks = <&dpll4_ck>;
 362                 ti,bit-shift = <8>;
 363                 ti,max-div = <32>;
 364                 reg = <0x0e40>;
 365                 ti,index-starts-at-one;
 366         };
 367
 368         dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
 369                 #clock-cells = <0>;
 370                 compatible = "fixed-factor-clock";
 371                 clocks = <&dpll4_m3_ck>;
 372                 clock-mult = <2>;
 373                 clock-div = <1>;
 374         };
 375
 376         dpll4_m3x2_ck: dpll4_m3x2_ck {
 377                 #clock-cells = <0>;
 378                 compatible = "ti,gate-clock";
 379                 clocks = <&dpll4_m3x2_mul_ck>;
 380                 ti,bit-shift = <0x1c>;
 381                 reg = <0x0d00>;
 382                 ti,set-bit-to-disable;
 383         };
 384
 385         omap_54m_fck: omap_54m_fck {
 386                 #clock-cells = <0>;
 387                 compatible = "ti,mux-clock";
 388                 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
 389                 ti,bit-shift = <5>;
 390                 reg = <0x0d40>;
 391         };
 392
 393         cm_96m_d2_fck: cm_96m_d2_fck {
 394                 #clock-cells = <0>;
 395                 compatible = "fixed-factor-clock";
 396                 clocks = <&cm_96m_fck>;
 397                 clock-mult = <1>;
 398                 clock-div = <2>;
 399         };
 400
 401         omap_48m_fck: omap_48m_fck {
 402                 #clock-cells = <0>;
 403                 compatible = "ti,mux-clock";
 404                 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
 405                 ti,bit-shift = <3>;
 406                 reg = <0x0d40>;
 407         };
 408
 409         omap_12m_fck: omap_12m_fck {
 410                 #clock-cells = <0>;
 411                 compatible = "fixed-factor-clock";
 412                 clocks = <&omap_48m_fck>;
 413                 clock-mult = <1>;
 414                 clock-div = <4>;
 415         };
 416
 417         dpll4_m4_ck: dpll4_m4_ck {
 418                 #clock-cells = <0>;
 419                 compatible = "ti,divider-clock";
 420                 clocks = <&dpll4_ck>;
 421                 ti,max-div = <32>;
 422                 reg = <0x0e40>;
 423                 ti,index-starts-at-one;
 424         };
 425
 426         dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
 427                 #clock-cells = <0>;
 428                 compatible = "ti,fixed-factor-clock";
 429                 clocks = <&dpll4_m4_ck>;
 430                 ti,clock-mult = <2>;
 431                 ti,clock-div = <1>;
 432                 ti,set-rate-parent;
 433         };
 434
 435         dpll4_m4x2_ck: dpll4_m4x2_ck {
 436                 #clock-cells = <0>;
 437                 compatible = "ti,gate-clock";
 438                 clocks = <&dpll4_m4x2_mul_ck>;
 439                 ti,bit-shift = <0x1d>;
 440                 reg = <0x0d00>;
 441                 ti,set-bit-to-disable;
 442                 ti,set-rate-parent;
 443         };
 444
 445         dpll4_m5_ck: dpll4_m5_ck {
 446                 #clock-cells = <0>;
 447                 compatible = "ti,divider-clock";
 448                 clocks = <&dpll4_ck>;
 449                 ti,max-div = <63>;
 450                 reg = <0x0f40>;
 451                 ti,index-starts-at-one;
 452         };
 453
 454         dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
 455                 #clock-cells = <0>;
 456                 compatible = "fixed-factor-clock";
 457                 clocks = <&dpll4_m5_ck>;
 458                 clock-mult = <2>;
 459                 clock-div = <1>;
 460         };
 461
 462         dpll4_m5x2_ck: dpll4_m5x2_ck {
 463                 #clock-cells = <0>;
 464                 compatible = "ti,gate-clock";
 465                 clocks = <&dpll4_m5x2_mul_ck>;
 466                 ti,bit-shift = <0x1e>;
 467                 reg = <0x0d00>;
 468                 ti,set-bit-to-disable;
 469         };
 470
 471         dpll4_m6_ck: dpll4_m6_ck {
 472                 #clock-cells = <0>;
 473                 compatible = "ti,divider-clock";
 474                 clocks = <&dpll4_ck>;
 475                 ti,bit-shift = <24>;
 476                 ti,max-div = <63>;
 477                 reg = <0x1140>;
 478                 ti,index-starts-at-one;
 479         };
 480
 481         dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
 482                 #clock-cells = <0>;
 483                 compatible = "fixed-factor-clock";
 484                 clocks = <&dpll4_m6_ck>;
 485                 clock-mult = <2>;
 486                 clock-div = <1>;
 487         };
 488
 489         dpll4_m6x2_ck: dpll4_m6x2_ck {
 490                 #clock-cells = <0>;
 491                 compatible = "ti,gate-clock";
 492                 clocks = <&dpll4_m6x2_mul_ck>;
 493                 ti,bit-shift = <0x1f>;
 494                 reg = <0x0d00>;
 495                 ti,set-bit-to-disable;
 496         };
 497
 498         emu_per_alwon_ck: emu_per_alwon_ck {
 499                 #clock-cells = <0>;
 500                 compatible = "fixed-factor-clock";
 501                 clocks = <&dpll4_m6x2_ck>;
 502                 clock-mult = <1>;
 503                 clock-div = <1>;
 504         };
 505
 506         clkout2_src_gate_ck: clkout2_src_gate_ck {
 507                 #clock-cells = <0>;
 508                 compatible = "ti,composite-no-wait-gate-clock";
 509                 clocks = <&core_ck>;
 510                 ti,bit-shift = <7>;
 511                 reg = <0x0d70>;
 512         };
 513
 514         clkout2_src_mux_ck: clkout2_src_mux_ck {
 515                 #clock-cells = <0>;
 516                 compatible = "ti,composite-mux-clock";
 517                 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
 518                 reg = <0x0d70>;
 519         };
 520
 521         clkout2_src_ck: clkout2_src_ck {
 522                 #clock-cells = <0>;
 523                 compatible = "ti,composite-clock";
 524                 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
 525         };
 526
 527         sys_clkout2: sys_clkout2 {
 528                 #clock-cells = <0>;
 529                 compatible = "ti,divider-clock";
 530                 clocks = <&clkout2_src_ck>;
 531                 ti,bit-shift = <3>;
 532                 ti,max-div = <64>;
 533                 reg = <0x0d70>;
 534                 ti,index-power-of-two;
 535         };
 536
 537         mpu_ck: mpu_ck {
 538                 #clock-cells = <0>;
 539                 compatible = "fixed-factor-clock";
 540                 clocks = <&dpll1_x2m2_ck>;
 541                 clock-mult = <1>;
 542                 clock-div = <1>;
 543         };
 544
 545         arm_fck: arm_fck {
 546                 #clock-cells = <0>;
 547                 compatible = "ti,divider-clock";
 548                 clocks = <&mpu_ck>;
 549                 reg = <0x0924>;
 550                 ti,max-div = <2>;
 551         };
 552
 553         emu_mpu_alwon_ck: emu_mpu_alwon_ck {
 554                 #clock-cells = <0>;
 555                 compatible = "fixed-factor-clock";
 556                 clocks = <&mpu_ck>;
 557                 clock-mult = <1>;
 558                 clock-div = <1>;
 559         };
 560
 561         l3_ick: l3_ick {
 562                 #clock-cells = <0>;
 563                 compatible = "ti,divider-clock";
 564                 clocks = <&core_ck>;
 565                 ti,max-div = <3>;
 566                 reg = <0x0a40>;
 567                 ti,index-starts-at-one;
 568         };
 569
 570         l4_ick: l4_ick {
 571                 #clock-cells = <0>;
 572                 compatible = "ti,divider-clock";
 573                 clocks = <&l3_ick>;
 574                 ti,bit-shift = <2>;
 575                 ti,max-div = <3>;
 576                 reg = <0x0a40>;
 577                 ti,index-starts-at-one;
 578         };
 579
 580         rm_ick: rm_ick {
 581                 #clock-cells = <0>;
 582                 compatible = "ti,divider-clock";
 583                 clocks = <&l4_ick>;
 584                 ti,bit-shift = <1>;
 585                 ti,max-div = <3>;
 586                 reg = <0x0c40>;
 587                 ti,index-starts-at-one;
 588         };
 589
 590         gpt10_gate_fck: gpt10_gate_fck {
 591                 #clock-cells = <0>;
 592                 compatible = "ti,composite-gate-clock";
 593                 clocks = <&sys_ck>;
 594                 ti,bit-shift = <11>;
 595                 reg = <0x0a00>;
 596         };
 597
 598         gpt10_mux_fck: gpt10_mux_fck {
 599                 #clock-cells = <0>;
 600                 compatible = "ti,composite-mux-clock";
 601                 clocks = <&omap_32k_fck>, <&sys_ck>;
 602                 ti,bit-shift = <6>;
 603                 reg = <0x0a40>;
 604         };
 605
 606         gpt10_fck: gpt10_fck {
 607                 #clock-cells = <0>;
 608                 compatible = "ti,composite-clock";
 609                 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
 610         };
 611
 612         gpt11_gate_fck: gpt11_gate_fck {
 613                 #clock-cells = <0>;
 614                 compatible = "ti,composite-gate-clock";
 615                 clocks = <&sys_ck>;
 616                 ti,bit-shift = <12>;
 617                 reg = <0x0a00>;
 618         };
 619
 620         gpt11_mux_fck: gpt11_mux_fck {
 621                 #clock-cells = <0>;
 622                 compatible = "ti,composite-mux-clock";
 623                 clocks = <&omap_32k_fck>, <&sys_ck>;
 624                 ti,bit-shift = <7>;
 625                 reg = <0x0a40>;
 626         };
 627
 628         gpt11_fck: gpt11_fck {
 629                 #clock-cells = <0>;
 630                 compatible = "ti,composite-clock";
 631                 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
 632         };
 633
 634         core_96m_fck: core_96m_fck {
 635                 #clock-cells = <0>;
 636                 compatible = "fixed-factor-clock";
 637                 clocks = <&omap_96m_fck>;
 638                 clock-mult = <1>;
 639                 clock-div = <1>;
 640         };
 641
 642         mmchs2_fck: mmchs2_fck {
 643                 #clock-cells = <0>;
 644                 compatible = "ti,wait-gate-clock";
 645                 clocks = <&core_96m_fck>;
 646                 reg = <0x0a00>;
 647                 ti,bit-shift = <25>;
 648         };
 649
 650         mmchs1_fck: mmchs1_fck {
 651                 #clock-cells = <0>;
 652                 compatible = "ti,wait-gate-clock";
 653                 clocks = <&core_96m_fck>;
 654                 reg = <0x0a00>;
 655                 ti,bit-shift = <24>;
 656         };
 657
 658         i2c3_fck: i2c3_fck {
 659                 #clock-cells = <0>;
 660                 compatible = "ti,wait-gate-clock";
 661                 clocks = <&core_96m_fck>;
 662                 reg = <0x0a00>;
 663                 ti,bit-shift = <17>;
 664         };
 665
 666         i2c2_fck: i2c2_fck {
 667                 #clock-cells = <0>;
 668                 compatible = "ti,wait-gate-clock";
 669                 clocks = <&core_96m_fck>;
 670                 reg = <0x0a00>;
 671                 ti,bit-shift = <16>;
 672         };
 673
 674         i2c1_fck: i2c1_fck {
 675                 #clock-cells = <0>;
 676                 compatible = "ti,wait-gate-clock";
 677                 clocks = <&core_96m_fck>;
 678                 reg = <0x0a00>;
 679                 ti,bit-shift = <15>;
 680         };
 681
 682         mcbsp5_gate_fck: mcbsp5_gate_fck {
 683                 #clock-cells = <0>;
 684                 compatible = "ti,composite-gate-clock";
 685                 clocks = <&mcbsp_clks>;
 686                 ti,bit-shift = <10>;
 687                 reg = <0x0a00>;
 688         };
 689
 690         mcbsp1_gate_fck: mcbsp1_gate_fck {
 691                 #clock-cells = <0>;
 692                 compatible = "ti,composite-gate-clock";
 693                 clocks = <&mcbsp_clks>;
 694                 ti,bit-shift = <9>;
 695                 reg = <0x0a00>;
 696         };
 697
 698         core_48m_fck: core_48m_fck {
 699                 #clock-cells = <0>;
 700                 compatible = "fixed-factor-clock";
 701                 clocks = <&omap_48m_fck>;
 702                 clock-mult = <1>;
 703                 clock-div = <1>;
 704         };
 705
 706         mcspi4_fck: mcspi4_fck {
 707                 #clock-cells = <0>;
 708                 compatible = "ti,wait-gate-clock";
 709                 clocks = <&core_48m_fck>;
 710                 reg = <0x0a00>;
 711                 ti,bit-shift = <21>;
 712         };
 713
 714         mcspi3_fck: mcspi3_fck {
 715                 #clock-cells = <0>;
 716                 compatible = "ti,wait-gate-clock";
 717                 clocks = <&core_48m_fck>;
 718                 reg = <0x0a00>;
 719                 ti,bit-shift = <20>;
 720         };
 721
 722         mcspi2_fck: mcspi2_fck {
 723                 #clock-cells = <0>;
 724                 compatible = "ti,wait-gate-clock";
 725                 clocks = <&core_48m_fck>;
 726                 reg = <0x0a00>;
 727                 ti,bit-shift = <19>;
 728         };
 729
 730         mcspi1_fck: mcspi1_fck {
 731                 #clock-cells = <0>;
 732                 compatible = "ti,wait-gate-clock";
 733                 clocks = <&core_48m_fck>;
 734                 reg = <0x0a00>;
 735                 ti,bit-shift = <18>;
 736         };
 737
 738         uart2_fck: uart2_fck {
 739                 #clock-cells = <0>;
 740                 compatible = "ti,wait-gate-clock";
 741                 clocks = <&core_48m_fck>;
 742                 reg = <0x0a00>;
 743                 ti,bit-shift = <14>;
 744         };
 745
 746         uart1_fck: uart1_fck {
 747                 #clock-cells = <0>;
 748                 compatible = "ti,wait-gate-clock";
 749                 clocks = <&core_48m_fck>;
 750                 reg = <0x0a00>;
 751                 ti,bit-shift = <13>;
 752         };
 753
 754         core_12m_fck: core_12m_fck {
 755                 #clock-cells = <0>;
 756                 compatible = "fixed-factor-clock";
 757                 clocks = <&omap_12m_fck>;
 758                 clock-mult = <1>;
 759                 clock-div = <1>;
 760         };
 761
 762         hdq_fck: hdq_fck {
 763                 #clock-cells = <0>;
 764                 compatible = "ti,wait-gate-clock";
 765                 clocks = <&core_12m_fck>;
 766                 reg = <0x0a00>;
 767                 ti,bit-shift = <22>;
 768         };
 769
 770         core_l3_ick: core_l3_ick {
 771                 #clock-cells = <0>;
 772                 compatible = "fixed-factor-clock";
 773                 clocks = <&l3_ick>;
 774                 clock-mult = <1>;
 775                 clock-div = <1>;
 776         };
 777
 778         sdrc_ick: sdrc_ick {
 779                 #clock-cells = <0>;
 780                 compatible = "ti,wait-gate-clock";
 781                 clocks = <&core_l3_ick>;
 782                 reg = <0x0a10>;
 783                 ti,bit-shift = <1>;
 784         };
 785
 786         gpmc_fck: gpmc_fck {
 787                 #clock-cells = <0>;
 788                 compatible = "fixed-factor-clock";
 789                 clocks = <&core_l3_ick>;
 790                 clock-mult = <1>;
 791                 clock-div = <1>;
 792         };
 793
 794         core_l4_ick: core_l4_ick {
 795                 #clock-cells = <0>;
 796                 compatible = "fixed-factor-clock";
 797                 clocks = <&l4_ick>;
 798                 clock-mult = <1>;
 799                 clock-div = <1>;
 800         };
 801
 802         mmchs2_ick: mmchs2_ick {
 803                 #clock-cells = <0>;
 804                 compatible = "ti,omap3-interface-clock";
 805                 clocks = <&core_l4_ick>;
 806                 reg = <0x0a10>;
 807                 ti,bit-shift = <25>;
 808         };
 809
 810         mmchs1_ick: mmchs1_ick {
 811                 #clock-cells = <0>;
 812                 compatible = "ti,omap3-interface-clock";
 813                 clocks = <&core_l4_ick>;
 814                 reg = <0x0a10>;
 815                 ti,bit-shift = <24>;
 816         };
 817
 818         hdq_ick: hdq_ick {
 819                 #clock-cells = <0>;
 820                 compatible = "ti,omap3-interface-clock";
 821                 clocks = <&core_l4_ick>;
 822                 reg = <0x0a10>;
 823                 ti,bit-shift = <22>;
 824         };
 825
 826         mcspi4_ick: mcspi4_ick {
 827                 #clock-cells = <0>;
 828                 compatible = "ti,omap3-interface-clock";
 829                 clocks = <&core_l4_ick>;
 830                 reg = <0x0a10>;
 831                 ti,bit-shift = <21>;
 832         };
 833
 834         mcspi3_ick: mcspi3_ick {
 835                 #clock-cells = <0>;
 836                 compatible = "ti,omap3-interface-clock";
 837                 clocks = <&core_l4_ick>;
 838                 reg = <0x0a10>;
 839                 ti,bit-shift = <20>;
 840         };
 841
 842         mcspi2_ick: mcspi2_ick {
 843                 #clock-cells = <0>;
 844                 compatible = "ti,omap3-interface-clock";
 845                 clocks = <&core_l4_ick>;
 846                 reg = <0x0a10>;
 847                 ti,bit-shift = <19>;
 848         };
 849
 850         mcspi1_ick: mcspi1_ick {
 851                 #clock-cells = <0>;
 852                 compatible = "ti,omap3-interface-clock";
 853                 clocks = <&core_l4_ick>;
 854                 reg = <0x0a10>;
 855                 ti,bit-shift = <18>;
 856         };
 857
 858         i2c3_ick: i2c3_ick {
 859                 #clock-cells = <0>;
 860                 compatible = "ti,omap3-interface-clock";
 861                 clocks = <&core_l4_ick>;
 862                 reg = <0x0a10>;
 863                 ti,bit-shift = <17>;
 864         };
 865
 866         i2c2_ick: i2c2_ick {
 867                 #clock-cells = <0>;
 868                 compatible = "ti,omap3-interface-clock";
 869                 clocks = <&core_l4_ick>;
 870                 reg = <0x0a10>;
 871                 ti,bit-shift = <16>;
 872         };
 873
 874         i2c1_ick: i2c1_ick {
 875                 #clock-cells = <0>;
 876                 compatible = "ti,omap3-interface-clock";
 877                 clocks = <&core_l4_ick>;
 878                 reg = <0x0a10>;
 879                 ti,bit-shift = <15>;
 880         };
 881
 882         uart2_ick: uart2_ick {
 883                 #clock-cells = <0>;
 884                 compatible = "ti,omap3-interface-clock";
 885                 clocks = <&core_l4_ick>;
 886                 reg = <0x0a10>;
 887                 ti,bit-shift = <14>;
 888         };
 889
 890         uart1_ick: uart1_ick {
 891                 #clock-cells = <0>;
 892                 compatible = "ti,omap3-interface-clock";
 893                 clocks = <&core_l4_ick>;
 894                 reg = <0x0a10>;
 895                 ti,bit-shift = <13>;
 896         };
 897
 898         gpt11_ick: gpt11_ick {
 899                 #clock-cells = <0>;
 900                 compatible = "ti,omap3-interface-clock";
 901                 clocks = <&core_l4_ick>;
 902                 reg = <0x0a10>;
 903                 ti,bit-shift = <12>;
 904         };
 905
 906         gpt10_ick: gpt10_ick {
 907                 #clock-cells = <0>;
 908                 compatible = "ti,omap3-interface-clock";
 909                 clocks = <&core_l4_ick>;
 910                 reg = <0x0a10>;
 911                 ti,bit-shift = <11>;
 912         };
 913
 914         mcbsp5_ick: mcbsp5_ick {
 915                 #clock-cells = <0>;
 916                 compatible = "ti,omap3-interface-clock";
 917                 clocks = <&core_l4_ick>;
 918                 reg = <0x0a10>;
 919                 ti,bit-shift = <10>;
 920         };
 921
 922         mcbsp1_ick: mcbsp1_ick {
 923                 #clock-cells = <0>;
 924                 compatible = "ti,omap3-interface-clock";
 925                 clocks = <&core_l4_ick>;
 926                 reg = <0x0a10>;
 927                 ti,bit-shift = <9>;
 928         };
 929
 930         omapctrl_ick: omapctrl_ick {
 931                 #clock-cells = <0>;
 932                 compatible = "ti,omap3-interface-clock";
 933                 clocks = <&core_l4_ick>;
 934                 reg = <0x0a10>;
 935                 ti,bit-shift = <6>;
 936         };
 937
 938         dss_tv_fck: dss_tv_fck {
 939                 #clock-cells = <0>;
 940                 compatible = "ti,gate-clock";
 941                 clocks = <&omap_54m_fck>;
 942                 reg = <0x0e00>;
 943                 ti,bit-shift = <2>;
 944         };
 945
 946         dss_96m_fck: dss_96m_fck {
 947                 #clock-cells = <0>;
 948                 compatible = "ti,gate-clock";
 949                 clocks = <&omap_96m_fck>;
 950                 reg = <0x0e00>;
 951                 ti,bit-shift = <2>;
 952         };
 953
 954         dss2_alwon_fck: dss2_alwon_fck {
 955                 #clock-cells = <0>;
 956                 compatible = "ti,gate-clock";
 957                 clocks = <&sys_ck>;
 958                 reg = <0x0e00>;
 959                 ti,bit-shift = <1>;
 960         };
 961
 962         dummy_ck: dummy_ck {
 963                 #clock-cells = <0>;
 964                 compatible = "fixed-clock";
 965                 clock-frequency = <0>;
 966         };
 967
 968         gpt1_gate_fck: gpt1_gate_fck {
 969                 #clock-cells = <0>;
 970                 compatible = "ti,composite-gate-clock";
 971                 clocks = <&sys_ck>;
 972                 ti,bit-shift = <0>;
 973                 reg = <0x0c00>;
 974         };
 975
 976         gpt1_mux_fck: gpt1_mux_fck {
 977                 #clock-cells = <0>;
 978                 compatible = "ti,composite-mux-clock";
 979                 clocks = <&omap_32k_fck>, <&sys_ck>;
 980                 reg = <0x0c40>;
 981         };
 982
 983         gpt1_fck: gpt1_fck {
 984                 #clock-cells = <0>;
 985                 compatible = "ti,composite-clock";
 986                 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
 987         };
 988
 989         aes2_ick: aes2_ick {
 990                 #clock-cells = <0>;
 991                 compatible = "ti,omap3-interface-clock";
 992                 clocks = <&core_l4_ick>;
 993                 ti,bit-shift = <28>;
 994                 reg = <0x0a10>;
 995         };
 996
 997         wkup_32k_fck: wkup_32k_fck {
 998                 #clock-cells = <0>;
 999                 compatible = "fixed-factor-clock";
1000                 clocks = <&omap_32k_fck>;
1001                 clock-mult = <1>;
1002                 clock-div = <1>;
1003         };
1004
1005         gpio1_dbck: gpio1_dbck {
1006                 #clock-cells = <0>;
1007                 compatible = "ti,gate-clock";
1008                 clocks = <&wkup_32k_fck>;
1009                 reg = <0x0c00>;
1010                 ti,bit-shift = <3>;
1011         };
1012
1013         sha12_ick: sha12_ick {
1014                 #clock-cells = <0>;
1015                 compatible = "ti,omap3-interface-clock";
1016                 clocks = <&core_l4_ick>;
1017                 reg = <0x0a10>;
1018                 ti,bit-shift = <27>;
1019         };
1020
1021         wdt2_fck: wdt2_fck {
1022                 #clock-cells = <0>;
1023                 compatible = "ti,wait-gate-clock";
1024                 clocks = <&wkup_32k_fck>;
1025                 reg = <0x0c00>;
1026                 ti,bit-shift = <5>;
1027         };
1028
1029         wdt2_ick: wdt2_ick {
1030                 #clock-cells = <0>;
1031                 compatible = "ti,omap3-interface-clock";
1032                 clocks = <&wkup_l4_ick>;
1033                 reg = <0x0c10>;
1034                 ti,bit-shift = <5>;
1035         };
1036
1037         wdt1_ick: wdt1_ick {
1038                 #clock-cells = <0>;
1039                 compatible = "ti,omap3-interface-clock";
1040                 clocks = <&wkup_l4_ick>;
1041                 reg = <0x0c10>;
1042                 ti,bit-shift = <4>;
1043         };
1044
1045         gpio1_ick: gpio1_ick {
1046                 #clock-cells = <0>;
1047                 compatible = "ti,omap3-interface-clock";
1048                 clocks = <&wkup_l4_ick>;
1049                 reg = <0x0c10>;
1050                 ti,bit-shift = <3>;
1051         };
1052
1053         omap_32ksync_ick: omap_32ksync_ick {
1054                 #clock-cells = <0>;
1055                 compatible = "ti,omap3-interface-clock";
1056                 clocks = <&wkup_l4_ick>;
1057                 reg = <0x0c10>;
1058                 ti,bit-shift = <2>;
1059         };
1060
1061         gpt12_ick: gpt12_ick {
1062                 #clock-cells = <0>;
1063                 compatible = "ti,omap3-interface-clock";
1064                 clocks = <&wkup_l4_ick>;
1065                 reg = <0x0c10>;
1066                 ti,bit-shift = <1>;
1067         };
1068
1069         gpt1_ick: gpt1_ick {
1070                 #clock-cells = <0>;
1071                 compatible = "ti,omap3-interface-clock";
1072                 clocks = <&wkup_l4_ick>;
1073                 reg = <0x0c10>;
1074                 ti,bit-shift = <0>;
1075         };
1076
1077         per_96m_fck: per_96m_fck {
1078                 #clock-cells = <0>;
1079                 compatible = "fixed-factor-clock";
1080                 clocks = <&omap_96m_alwon_fck>;
1081                 clock-mult = <1>;
1082                 clock-div = <1>;
1083         };
1084
1085         per_48m_fck: per_48m_fck {
1086                 #clock-cells = <0>;
1087                 compatible = "fixed-factor-clock";
1088                 clocks = <&omap_48m_fck>;
1089                 clock-mult = <1>;
1090                 clock-div = <1>;
1091         };
1092
1093         uart3_fck: uart3_fck {
1094                 #clock-cells = <0>;
1095                 compatible = "ti,wait-gate-clock";
1096                 clocks = <&per_48m_fck>;
1097                 reg = <0x1000>;
1098                 ti,bit-shift = <11>;
1099         };
1100
1101         gpt2_gate_fck: gpt2_gate_fck {
1102                 #clock-cells = <0>;
1103                 compatible = "ti,composite-gate-clock";
1104                 clocks = <&sys_ck>;
1105                 ti,bit-shift = <3>;
1106                 reg = <0x1000>;
1107         };
1108
1109         gpt2_mux_fck: gpt2_mux_fck {
1110                 #clock-cells = <0>;
1111                 compatible = "ti,composite-mux-clock";
1112                 clocks = <&omap_32k_fck>, <&sys_ck>;
1113                 reg = <0x1040>;
1114         };
1115
1116         gpt2_fck: gpt2_fck {
1117                 #clock-cells = <0>;
1118                 compatible = "ti,composite-clock";
1119                 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1120         };
1121
1122         gpt3_gate_fck: gpt3_gate_fck {
1123                 #clock-cells = <0>;
1124                 compatible = "ti,composite-gate-clock";
1125                 clocks = <&sys_ck>;
1126                 ti,bit-shift = <4>;
1127                 reg = <0x1000>;
1128         };
1129
1130         gpt3_mux_fck: gpt3_mux_fck {
1131                 #clock-cells = <0>;
1132                 compatible = "ti,composite-mux-clock";
1133                 clocks = <&omap_32k_fck>, <&sys_ck>;
1134                 ti,bit-shift = <1>;
1135                 reg = <0x1040>;
1136         };
1137
1138         gpt3_fck: gpt3_fck {
1139                 #clock-cells = <0>;
1140                 compatible = "ti,composite-clock";
1141                 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1142         };
1143
1144         gpt4_gate_fck: gpt4_gate_fck {
1145                 #clock-cells = <0>;
1146                 compatible = "ti,composite-gate-clock";
1147                 clocks = <&sys_ck>;
1148                 ti,bit-shift = <5>;
1149                 reg = <0x1000>;
1150         };
1151
1152         gpt4_mux_fck: gpt4_mux_fck {
1153                 #clock-cells = <0>;
1154                 compatible = "ti,composite-mux-clock";
1155                 clocks = <&omap_32k_fck>, <&sys_ck>;
1156                 ti,bit-shift = <2>;
1157                 reg = <0x1040>;
1158         };
1159
1160         gpt4_fck: gpt4_fck {
1161                 #clock-cells = <0>;
1162                 compatible = "ti,composite-clock";
1163                 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1164         };
1165
1166         gpt5_gate_fck: gpt5_gate_fck {
1167                 #clock-cells = <0>;
1168                 compatible = "ti,composite-gate-clock";
1169                 clocks = <&sys_ck>;
1170                 ti,bit-shift = <6>;
1171                 reg = <0x1000>;
1172         };
1173
1174         gpt5_mux_fck: gpt5_mux_fck {
1175                 #clock-cells = <0>;
1176                 compatible = "ti,composite-mux-clock";
1177                 clocks = <&omap_32k_fck>, <&sys_ck>;
1178                 ti,bit-shift = <3>;
1179                 reg = <0x1040>;
1180         };
1181
1182         gpt5_fck: gpt5_fck {
1183                 #clock-cells = <0>;
1184                 compatible = "ti,composite-clock";
1185                 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1186         };
1187
1188         gpt6_gate_fck: gpt6_gate_fck {
1189                 #clock-cells = <0>;
1190                 compatible = "ti,composite-gate-clock";
1191                 clocks = <&sys_ck>;
1192                 ti,bit-shift = <7>;
1193                 reg = <0x1000>;
1194         };
1195
1196         gpt6_mux_fck: gpt6_mux_fck {
1197                 #clock-cells = <0>;
1198                 compatible = "ti,composite-mux-clock";
1199                 clocks = <&omap_32k_fck>, <&sys_ck>;
1200                 ti,bit-shift = <4>;
1201                 reg = <0x1040>;
1202         };
1203
1204         gpt6_fck: gpt6_fck {
1205                 #clock-cells = <0>;
1206                 compatible = "ti,composite-clock";
1207                 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1208         };
1209
1210         gpt7_gate_fck: gpt7_gate_fck {
1211                 #clock-cells = <0>;
1212                 compatible = "ti,composite-gate-clock";
1213                 clocks = <&sys_ck>;
1214                 ti,bit-shift = <8>;
1215                 reg = <0x1000>;
1216         };
1217
1218         gpt7_mux_fck: gpt7_mux_fck {
1219                 #clock-cells = <0>;
1220                 compatible = "ti,composite-mux-clock";
1221                 clocks = <&omap_32k_fck>, <&sys_ck>;
1222                 ti,bit-shift = <5>;
1223                 reg = <0x1040>;
1224         };
1225
1226         gpt7_fck: gpt7_fck {
1227                 #clock-cells = <0>;
1228                 compatible = "ti,composite-clock";
1229                 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1230         };
1231
1232         gpt8_gate_fck: gpt8_gate_fck {
1233                 #clock-cells = <0>;
1234                 compatible = "ti,composite-gate-clock";
1235                 clocks = <&sys_ck>;
1236                 ti,bit-shift = <9>;
1237                 reg = <0x1000>;
1238         };
1239
1240         gpt8_mux_fck: gpt8_mux_fck {
1241                 #clock-cells = <0>;
1242                 compatible = "ti,composite-mux-clock";
1243                 clocks = <&omap_32k_fck>, <&sys_ck>;
1244                 ti,bit-shift = <6>;
1245                 reg = <0x1040>;
1246         };
1247
1248         gpt8_fck: gpt8_fck {
1249                 #clock-cells = <0>;
1250                 compatible = "ti,composite-clock";
1251                 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1252         };
1253
1254         gpt9_gate_fck: gpt9_gate_fck {
1255                 #clock-cells = <0>;
1256                 compatible = "ti,composite-gate-clock";
1257                 clocks = <&sys_ck>;
1258                 ti,bit-shift = <10>;
1259                 reg = <0x1000>;
1260         };
1261
1262         gpt9_mux_fck: gpt9_mux_fck {
1263                 #clock-cells = <0>;
1264                 compatible = "ti,composite-mux-clock";
1265                 clocks = <&omap_32k_fck>, <&sys_ck>;
1266                 ti,bit-shift = <7>;
1267                 reg = <0x1040>;
1268         };
1269
1270         gpt9_fck: gpt9_fck {
1271                 #clock-cells = <0>;
1272                 compatible = "ti,composite-clock";
1273                 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1274         };
1275
1276         per_32k_alwon_fck: per_32k_alwon_fck {
1277                 #clock-cells = <0>;
1278                 compatible = "fixed-factor-clock";
1279                 clocks = <&omap_32k_fck>;
1280                 clock-mult = <1>;
1281                 clock-div = <1>;
1282         };
1283
1284         gpio6_dbck: gpio6_dbck {
1285                 #clock-cells = <0>;
1286                 compatible = "ti,gate-clock";
1287                 clocks = <&per_32k_alwon_fck>;
1288                 reg = <0x1000>;
1289                 ti,bit-shift = <17>;
1290         };
1291
1292         gpio5_dbck: gpio5_dbck {
1293                 #clock-cells = <0>;
1294                 compatible = "ti,gate-clock";
1295                 clocks = <&per_32k_alwon_fck>;
1296                 reg = <0x1000>;
1297                 ti,bit-shift = <16>;
1298         };
1299
1300         gpio4_dbck: gpio4_dbck {
1301                 #clock-cells = <0>;
1302                 compatible = "ti,gate-clock";
1303                 clocks = <&per_32k_alwon_fck>;
1304                 reg = <0x1000>;
1305                 ti,bit-shift = <15>;
1306         };
1307
1308         gpio3_dbck: gpio3_dbck {
1309                 #clock-cells = <0>;
1310                 compatible = "ti,gate-clock";
1311                 clocks = <&per_32k_alwon_fck>;
1312                 reg = <0x1000>;
1313                 ti,bit-shift = <14>;
1314         };
1315
1316         gpio2_dbck: gpio2_dbck {
1317                 #clock-cells = <0>;
1318                 compatible = "ti,gate-clock";
1319                 clocks = <&per_32k_alwon_fck>;
1320                 reg = <0x1000>;
1321                 ti,bit-shift = <13>;
1322         };
1323
1324         wdt3_fck: wdt3_fck {
1325                 #clock-cells = <0>;
1326                 compatible = "ti,wait-gate-clock";
1327                 clocks = <&per_32k_alwon_fck>;
1328                 reg = <0x1000>;
1329                 ti,bit-shift = <12>;
1330         };
1331
1332         per_l4_ick: per_l4_ick {
1333                 #clock-cells = <0>;
1334                 compatible = "fixed-factor-clock";
1335                 clocks = <&l4_ick>;
1336                 clock-mult = <1>;
1337                 clock-div = <1>;
1338         };
1339
1340         gpio6_ick: gpio6_ick {
1341                 #clock-cells = <0>;
1342                 compatible = "ti,omap3-interface-clock";
1343                 clocks = <&per_l4_ick>;
1344                 reg = <0x1010>;
1345                 ti,bit-shift = <17>;
1346         };
1347
1348         gpio5_ick: gpio5_ick {
1349                 #clock-cells = <0>;
1350                 compatible = "ti,omap3-interface-clock";
1351                 clocks = <&per_l4_ick>;
1352                 reg = <0x1010>;
1353                 ti,bit-shift = <16>;
1354         };
1355
1356         gpio4_ick: gpio4_ick {
1357                 #clock-cells = <0>;
1358                 compatible = "ti,omap3-interface-clock";
1359                 clocks = <&per_l4_ick>;
1360                 reg = <0x1010>;
1361                 ti,bit-shift = <15>;
1362         };
1363
1364         gpio3_ick: gpio3_ick {
1365                 #clock-cells = <0>;
1366                 compatible = "ti,omap3-interface-clock";
1367                 clocks = <&per_l4_ick>;
1368                 reg = <0x1010>;
1369                 ti,bit-shift = <14>;
1370         };
1371
1372         gpio2_ick: gpio2_ick {
1373                 #clock-cells = <0>;
1374                 compatible = "ti,omap3-interface-clock";
1375                 clocks = <&per_l4_ick>;
1376                 reg = <0x1010>;
1377                 ti,bit-shift = <13>;
1378         };
1379
1380         wdt3_ick: wdt3_ick {
1381                 #clock-cells = <0>;
1382                 compatible = "ti,omap3-interface-clock";
1383                 clocks = <&per_l4_ick>;
1384                 reg = <0x1010>;
1385                 ti,bit-shift = <12>;
1386         };
1387
1388         uart3_ick: uart3_ick {
1389                 #clock-cells = <0>;
1390                 compatible = "ti,omap3-interface-clock";
1391                 clocks = <&per_l4_ick>;
1392                 reg = <0x1010>;
1393                 ti,bit-shift = <11>;
1394         };
1395
1396         uart4_ick: uart4_ick {
1397                 #clock-cells = <0>;
1398                 compatible = "ti,omap3-interface-clock";
1399                 clocks = <&per_l4_ick>;
1400                 reg = <0x1010>;
1401                 ti,bit-shift = <18>;
1402         };
1403
1404         gpt9_ick: gpt9_ick {
1405                 #clock-cells = <0>;
1406                 compatible = "ti,omap3-interface-clock";
1407                 clocks = <&per_l4_ick>;
1408                 reg = <0x1010>;
1409                 ti,bit-shift = <10>;
1410         };
1411
1412         gpt8_ick: gpt8_ick {
1413                 #clock-cells = <0>;
1414                 compatible = "ti,omap3-interface-clock";
1415                 clocks = <&per_l4_ick>;
1416                 reg = <0x1010>;
1417                 ti,bit-shift = <9>;
1418         };
1419
1420         gpt7_ick: gpt7_ick {
1421                 #clock-cells = <0>;
1422                 compatible = "ti,omap3-interface-clock";
1423                 clocks = <&per_l4_ick>;
1424                 reg = <0x1010>;
1425                 ti,bit-shift = <8>;
1426         };
1427
1428         gpt6_ick: gpt6_ick {
1429                 #clock-cells = <0>;
1430                 compatible = "ti,omap3-interface-clock";
1431                 clocks = <&per_l4_ick>;
1432                 reg = <0x1010>;
1433                 ti,bit-shift = <7>;
1434         };
1435
1436         gpt5_ick: gpt5_ick {
1437                 #clock-cells = <0>;
1438                 compatible = "ti,omap3-interface-clock";
1439                 clocks = <&per_l4_ick>;
1440                 reg = <0x1010>;
1441                 ti,bit-shift = <6>;
1442         };
1443
1444         gpt4_ick: gpt4_ick {
1445                 #clock-cells = <0>;
1446                 compatible = "ti,omap3-interface-clock";
1447                 clocks = <&per_l4_ick>;
1448                 reg = <0x1010>;
1449                 ti,bit-shift = <5>;
1450         };
1451
1452         gpt3_ick: gpt3_ick {
1453                 #clock-cells = <0>;
1454                 compatible = "ti,omap3-interface-clock";
1455                 clocks = <&per_l4_ick>;
1456                 reg = <0x1010>;
1457                 ti,bit-shift = <4>;
1458         };
1459
1460         gpt2_ick: gpt2_ick {
1461                 #clock-cells = <0>;
1462                 compatible = "ti,omap3-interface-clock";
1463                 clocks = <&per_l4_ick>;
1464                 reg = <0x1010>;
1465                 ti,bit-shift = <3>;
1466         };
1467
1468         mcbsp2_ick: mcbsp2_ick {
1469                 #clock-cells = <0>;
1470                 compatible = "ti,omap3-interface-clock";
1471                 clocks = <&per_l4_ick>;
1472                 reg = <0x1010>;
1473                 ti,bit-shift = <0>;
1474         };
1475
1476         mcbsp3_ick: mcbsp3_ick {
1477                 #clock-cells = <0>;
1478                 compatible = "ti,omap3-interface-clock";
1479                 clocks = <&per_l4_ick>;
1480                 reg = <0x1010>;
1481                 ti,bit-shift = <1>;
1482         };
1483
1484         mcbsp4_ick: mcbsp4_ick {
1485                 #clock-cells = <0>;
1486                 compatible = "ti,omap3-interface-clock";
1487                 clocks = <&per_l4_ick>;
1488                 reg = <0x1010>;
1489                 ti,bit-shift = <2>;
1490         };
1491
1492         mcbsp2_gate_fck: mcbsp2_gate_fck {
1493                 #clock-cells = <0>;
1494                 compatible = "ti,composite-gate-clock";
1495                 clocks = <&mcbsp_clks>;
1496                 ti,bit-shift = <0>;
1497                 reg = <0x1000>;
1498         };
1499
1500         mcbsp3_gate_fck: mcbsp3_gate_fck {
1501                 #clock-cells = <0>;
1502                 compatible = "ti,composite-gate-clock";
1503                 clocks = <&mcbsp_clks>;
1504                 ti,bit-shift = <1>;
1505                 reg = <0x1000>;
1506         };
1507
1508         mcbsp4_gate_fck: mcbsp4_gate_fck {
1509                 #clock-cells = <0>;
1510                 compatible = "ti,composite-gate-clock";
1511                 clocks = <&mcbsp_clks>;
1512                 ti,bit-shift = <2>;
1513                 reg = <0x1000>;
1514         };
1515
1516         emu_src_mux_ck: emu_src_mux_ck {
1517                 #clock-cells = <0>;
1518                 compatible = "ti,mux-clock";
1519                 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1520                 reg = <0x1140>;
1521         };
1522
1523         emu_src_ck: emu_src_ck {
1524                 #clock-cells = <0>;
1525                 compatible = "ti,clkdm-gate-clock";
1526                 clocks = <&emu_src_mux_ck>;
1527         };
1528
1529         pclk_fck: pclk_fck {
1530                 #clock-cells = <0>;
1531                 compatible = "ti,divider-clock";
1532                 clocks = <&emu_src_ck>;
1533                 ti,bit-shift = <8>;
1534                 ti,max-div = <7>;
1535                 reg = <0x1140>;
1536                 ti,index-starts-at-one;
1537         };
1538
1539         pclkx2_fck: pclkx2_fck {
1540                 #clock-cells = <0>;
1541                 compatible = "ti,divider-clock";
1542                 clocks = <&emu_src_ck>;
1543                 ti,bit-shift = <6>;
1544                 ti,max-div = <3>;
1545                 reg = <0x1140>;
1546                 ti,index-starts-at-one;
1547         };
1548
1549         atclk_fck: atclk_fck {
1550                 #clock-cells = <0>;
1551                 compatible = "ti,divider-clock";
1552                 clocks = <&emu_src_ck>;
1553                 ti,bit-shift = <4>;
1554                 ti,max-div = <3>;
1555                 reg = <0x1140>;
1556                 ti,index-starts-at-one;
1557         };
1558
1559         traceclk_src_fck: traceclk_src_fck {
1560                 #clock-cells = <0>;
1561                 compatible = "ti,mux-clock";
1562                 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1563                 ti,bit-shift = <2>;
1564                 reg = <0x1140>;
1565         };
1566
1567         traceclk_fck: traceclk_fck {
1568                 #clock-cells = <0>;
1569                 compatible = "ti,divider-clock";
1570                 clocks = <&traceclk_src_fck>;
1571                 ti,bit-shift = <11>;
1572                 ti,max-div = <7>;
1573                 reg = <0x1140>;
1574                 ti,index-starts-at-one;
1575         };
1576
1577         secure_32k_fck: secure_32k_fck {
1578                 #clock-cells = <0>;
1579                 compatible = "fixed-clock";
1580                 clock-frequency = <32768>;
1581         };
1582
1583         gpt12_fck: gpt12_fck {
1584                 #clock-cells = <0>;
1585                 compatible = "fixed-factor-clock";
1586                 clocks = <&secure_32k_fck>;
1587                 clock-mult = <1>;
1588                 clock-div = <1>;
1589         };
1590
1591         wdt1_fck: wdt1_fck {
1592                 #clock-cells = <0>;
1593                 compatible = "fixed-factor-clock";
1594                 clocks = <&secure_32k_fck>;
1595                 clock-mult = <1>;
1596                 clock-div = <1>;
1597         };
1598 };
1599
1600 &cm_clockdomains {
1601         core_l3_clkdm: core_l3_clkdm {
1602                 compatible = "ti,clockdomain";
1603                 clocks = <&sdrc_ick>;
1604         };
1605
1606         dpll3_clkdm: dpll3_clkdm {
1607                 compatible = "ti,clockdomain";
1608                 clocks = <&dpll3_ck>;
1609         };
1610
1611         dpll1_clkdm: dpll1_clkdm {
1612                 compatible = "ti,clockdomain";
1613                 clocks = <&dpll1_ck>;
1614         };
1615
1616         per_clkdm: per_clkdm {
1617                 compatible = "ti,clockdomain";
1618                 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1619                          <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1620                          <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1621                          <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1622                          <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1623                          <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1624                          <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1625                          <&mcbsp4_ick>;
1626         };
1627
1628         emu_clkdm: emu_clkdm {
1629                 compatible = "ti,clockdomain";
1630                 clocks = <&emu_src_ck>;
1631         };
1632
1633         dpll4_clkdm: dpll4_clkdm {
1634                 compatible = "ti,clockdomain";
1635                 clocks = <&dpll4_ck>;
1636         };
1637
1638         wkup_clkdm: wkup_clkdm {
1639                 compatible = "ti,clockdomain";
1640                 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1641                          <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1642                          <&gpt1_ick>;
1643         };
1644
1645         dss_clkdm: dss_clkdm {
1646                 compatible = "ti,clockdomain";
1647                 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1648         };
1649
1650         core_l4_clkdm: core_l4_clkdm {
1651                 compatible = "ti,clockdomain";
1652                 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1653                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1654                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1655                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1656                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1657                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1658                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1659                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1660                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1661         };
1662 };