arch/arm/boot/dts/mt7629.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  *
   5  * Author: Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/mt7629-clk.h>
  11 #include <dt-bindings/power/mt7622-power.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/reset/mt7629-resets.h>
  15
  16 / {
  17         compatible = "mediatek,mt7629";
  18         interrupt-parent = <&sysirq>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 enable-method = "mediatek,mt6589-smp";
  26
  27                 cpu0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x0>;
  31                         clock-frequency = <1250000000>;
  32                         cci-control-port = <&cci_control2>;
  33                 };
  34
  35                 cpu1: cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x1>;
  39                         clock-frequency = <1250000000>;
  40                         cci-control-port = <&cci_control2>;
  41                 };
  42         };
  43
  44         pmu {
  45                 compatible = "arm,cortex-a7-pmu";
  46                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
  47                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
  48                 interrupt-affinity = <&cpu0>, <&cpu1>;
  49         };
  50
  51         clk20m: oscillator-0 {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <20000000>;
  55                 clock-output-names = "clk20m";
  56         };
  57
  58         clk40m: oscillator-1 {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <40000000>;
  62                 clock-output-names = "clkxtal";
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv7-timer";
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  69                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  70                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  71                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72                 clock-frequency = <20000000>;
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges;
  80
  81                 infracfg: syscon@10000000 {
  82                         compatible = "mediatek,mt7629-infracfg", "syscon";
  83                         reg = <0x10000000 0x1000>;
  84                         #clock-cells = <1>;
  85                 };
  86
  87                 pericfg: syscon@10002000 {
  88                         compatible = "mediatek,mt7629-pericfg", "syscon";
  89                         reg = <0x10002000 0x1000>;
  90                         #clock-cells = <1>;
  91                 };
  92
  93                 scpsys: scpsys@10006000 {
  94                         compatible = "mediatek,mt7629-scpsys",
  95                                      "mediatek,mt7622-scpsys";
  96                         #power-domain-cells = <1>;
  97                         reg = <0x10006000 0x1000>;
  98                         clocks = <&topckgen CLK_TOP_HIF_SEL>;
  99                         clock-names = "hif_sel";
 100                         assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
 101                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
 102                         infracfg = <&infracfg>;
 103                 };
 104
 105                 timer: timer@10009000 {
 106                         compatible = "mediatek,mt7629-timer",
 107                                      "mediatek,mt6765-timer";
 108                         reg = <0x10009000 0x60>;
 109                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 110                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 111                         clocks = <&clk20m>;
 112                         clock-names = "clk20m";
 113                 };
 114
 115                 sysirq: interrupt-controller@10200a80 {
 116                         compatible = "mediatek,mt7629-sysirq",
 117                                      "mediatek,mt6577-sysirq";
 118                         reg = <0x10200a80 0x20>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <3>;
 121                         interrupt-parent = <&gic>;
 122                 };
 123
 124                 apmixedsys: syscon@10209000 {
 125                         compatible = "mediatek,mt7629-apmixedsys", "syscon";
 126                         reg = <0x10209000 0x1000>;
 127                         #clock-cells = <1>;
 128                 };
 129
 130                 rng: rng@1020f000 {
 131                         compatible = "mediatek,mt7629-rng",
 132                                      "mediatek,mt7623-rng";
 133                         reg = <0x1020f000 0x100>;
 134                         clocks = <&infracfg CLK_INFRA_TRNG_PD>;
 135                         clock-names = "rng";
 136                 };
 137
 138                 topckgen: syscon@10210000 {
 139                         compatible = "mediatek,mt7629-topckgen", "syscon";
 140                         reg = <0x10210000 0x1000>;
 141                         #clock-cells = <1>;
 142                 };
 143
 144                 watchdog: watchdog@10212000 {
 145                         compatible = "mediatek,mt7629-wdt",
 146                                      "mediatek,mt6589-wdt";
 147                         reg = <0x10212000 0x100>;
 148                 };
 149
 150                 pio: pinctrl@10217000 {
 151                         compatible = "mediatek,mt7629-pinctrl";
 152                         reg = <0x10217000 0x8000>,
 153                               <0x10005000 0x1000>;
 154                         reg-names = "base", "eint";
 155                         gpio-controller;
 156                         gpio-ranges = <&pio 0 0 79>;
 157                         #gpio-cells = <2>;
 158                         #interrupt-cells = <2>;
 159                         interrupt-controller;
 160                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 161                         interrupt-parent = <&gic>;
 162                 };
 163
 164                 gic: interrupt-controller@10300000 {
 165                         compatible = "arm,gic-400";
 166                         interrupt-controller;
 167                         #interrupt-cells = <3>;
 168                         interrupt-parent = <&gic>;
 169                         reg = <0x10310000 0x1000>,
 170                               <0x10320000 0x1000>,
 171                               <0x10340000 0x2000>,
 172                               <0x10360000 0x2000>;
 173                 };
 174
 175                 cci: cci@10390000 {
 176                         compatible = "arm,cci-400";
 177                         #address-cells = <1>;
 178                         #size-cells = <1>;
 179                         reg = <0x10390000 0x1000>;
 180                         ranges = <0 0x10390000 0x10000>;
 181
 182                         cci_control0: slave-if@1000 {
 183                                 compatible = "arm,cci-400-ctrl-if";
 184                                 interface-type = "ace-lite";
 185                                 reg = <0x1000 0x1000>;
 186                         };
 187
 188                         cci_control1: slave-if@4000 {
 189                                 compatible = "arm,cci-400-ctrl-if";
 190                                 interface-type = "ace";
 191                                 reg = <0x4000 0x1000>;
 192                         };
 193
 194                         cci_control2: slave-if@5000 {
 195                                 compatible = "arm,cci-400-ctrl-if";
 196                                 interface-type = "ace";
 197                                 reg = <0x5000 0x1000>;
 198                         };
 199
 200                         pmu@9000 {
 201                                 compatible = "arm,cci-400-pmu,r1";
 202                                 reg = <0x9000 0x5000>;
 203                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 204                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 205                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 206                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 207                                              <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 208                         };
 209                 };
 210
 211                 uart0: serial@11002000 {
 212                         compatible = "mediatek,mt7629-uart",
 213                                      "mediatek,mt6577-uart";
 214                         reg = <0x11002000 0x400>;
 215                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 216                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 217                                  <&pericfg CLK_PERI_UART0_PD>;
 218                         clock-names = "baud", "bus";
 219                         status = "disabled";
 220                 };
 221
 222                 uart1: serial@11003000 {
 223                         compatible = "mediatek,mt7629-uart",
 224                                      "mediatek,mt6577-uart";
 225                         reg = <0x11003000 0x400>;
 226                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 227                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 228                                  <&pericfg CLK_PERI_UART1_PD>;
 229                         clock-names = "baud", "bus";
 230                         status = "disabled";
 231                 };
 232
 233                 uart2: serial@11004000 {
 234                         compatible = "mediatek,mt7629-uart",
 235                                      "mediatek,mt6577-uart";
 236                         reg = <0x11004000 0x400>;
 237                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 238                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 239                                  <&pericfg CLK_PERI_UART2_PD>;
 240                         clock-names = "baud", "bus";
 241                         status = "disabled";
 242                 };
 243
 244                 i2c: i2c@11007000 {
 245                         compatible = "mediatek,mt7629-i2c",
 246                                      "mediatek,mt2712-i2c";
 247                         reg = <0x11007000 0x90>,
 248                               <0x11000100 0x80>;
 249                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 250                         clock-div = <4>;
 251                         clocks = <&pericfg CLK_PERI_I2C0_PD>,
 252                                  <&pericfg CLK_PERI_AP_DMA_PD>;
 253                         clock-names = "main", "dma";
 254                         assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 255                         assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         status = "disabled";
 259                 };
 260
 261                 spi: spi@1100a000 {
 262                         compatible = "mediatek,mt7629-spi",
 263                                      "mediatek,mt7622-spi";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         reg = <0x1100a000 0x100>;
 267                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 268                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 269                                  <&topckgen CLK_TOP_SPI0_SEL>,
 270                                  <&pericfg CLK_PERI_SPI0_PD>;
 271                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 272                         status = "disabled";
 273                 };
 274
 275                 qspi: spi@11014000 {
 276                         compatible = "mediatek,mt7629-nor",
 277                                      "mediatek,mt8173-nor";
 278                         reg = <0x11014000 0xe0>;
 279                         clocks = <&pericfg CLK_PERI_FLASH_PD>,
 280                                  <&topckgen CLK_TOP_FLASH_SEL>;
 281                         clock-names = "spi", "sf";
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         status = "disabled";
 285                 };
 286
 287                 ssusbsys: syscon@1a000000 {
 288                         compatible = "mediatek,mt7629-ssusbsys", "syscon";
 289                         reg = <0x1a000000 0x1000>;
 290                         #clock-cells = <1>;
 291                         #reset-cells = <1>;
 292                 };
 293
 294                 ssusb: usb@1a0c0000 {
 295                         compatible = "mediatek,mt7629-xhci",
 296                                      "mediatek,mtk-xhci";
 297                         reg = <0x1a0c0000 0x01000>,
 298                               <0x1a0c3e00 0x0100>;
 299                         reg-names = "mac", "ippc";
 300                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 301                         clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 302                                  <&ssusbsys CLK_SSUSB_REF_EN>,
 303                                  <&ssusbsys CLK_SSUSB_MCU_EN>,
 304                                  <&ssusbsys CLK_SSUSB_DMA_EN>;
 305                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 306                         assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
 307                                           <&topckgen CLK_TOP_SATA_SEL>,
 308                                           <&topckgen CLK_TOP_HIF_SEL>;
 309                         assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
 310                                                  <&topckgen CLK_TOP_UNIVPLL2_D4>,
 311                                                  <&topckgen CLK_TOP_UNIVPLL1_D2>;
 312                         power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 313                         phys = <&u2port0 PHY_TYPE_USB2>,
 314                                <&u3port0 PHY_TYPE_USB3>;
 315                         status = "disabled";
 316                 };
 317
 318                 u3phy0: usb-phy@1a0c4000 {
 319                         compatible = "mediatek,generic-tphy-v2";
 320                         #address-cells = <1>;
 321                         #size-cells = <1>;
 322                         ranges = <0 0x1a0c4000 0xe00>;
 323                         status = "disabled";
 324
 325                         u2port0: usb-phy@0 {
 326                                 reg = <0 0x700>;
 327                                 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 328                                 clock-names = "ref";
 329                                 #phy-cells = <1>;
 330                                 status = "okay";
 331                         };
 332
 333                         u3port0: usb-phy@700 {
 334                                 reg = <0x700 0x700>;
 335                                 clocks = <&clk20m>;
 336                                 clock-names = "ref";
 337                                 #phy-cells = <1>;
 338                                 status = "okay";
 339                         };
 340                 };
 341
 342                 pciesys: syscon@1a100800 {
 343                         compatible = "mediatek,mt7629-pciesys", "syscon";
 344                         reg = <0x1a100800 0x1000>;
 345                         #clock-cells = <1>;
 346                         #reset-cells = <1>;
 347                 };
 348
 349                 pcie: pcie@1a140000 {
 350                         compatible = "mediatek,mt7629-pcie";
 351                         device_type = "pci";
 352                         reg = <0x1a140000 0x1000>,
 353                               <0x1a145000 0x1000>;
 354                         reg-names = "subsys","port1";
 355                         #address-cells = <3>;
 356                         #size-cells = <2>;
 357                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
 358                                      <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 359                         clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 360                                  <&pciesys CLK_PCIE_P0_AHB_EN>,
 361                                  <&pciesys CLK_PCIE_P1_AUX_EN>,
 362                                  <&pciesys CLK_PCIE_P1_AXI_EN>,
 363                                  <&pciesys CLK_PCIE_P1_OBFF_EN>,
 364                                  <&pciesys CLK_PCIE_P1_PIPE_EN>;
 365                         clock-names = "sys_ck1", "ahb_ck1",
 366                                       "aux_ck1", "axi_ck1",
 367                                       "obff_ck1", "pipe_ck1";
 368                         assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
 369                                           <&topckgen CLK_TOP_AXI_SEL>,
 370                                           <&topckgen CLK_TOP_HIF_SEL>;
 371                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 372                                                  <&topckgen CLK_TOP_SYSPLL1_D2>,
 373                                                  <&topckgen CLK_TOP_UNIVPLL1_D2>;
 374                         phys = <&pcieport1 PHY_TYPE_PCIE>;
 375                         phy-names = "pcie-phy1";
 376                         power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 377                         bus-range = <0x00 0xff>;
 378                         ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
 379
 380                         pcie1: pcie@1,0 {
 381                                 device_type = "pci";
 382                                 reg = <0x0800 0 0 0 0>;
 383                                 #address-cells = <3>;
 384                                 #size-cells = <2>;
 385                                 #interrupt-cells = <1>;
 386                                 ranges;
 387                                 num-lanes = <1>;
 388                                 interrupt-map-mask = <0 0 0 7>;
 389                                 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 390                                                 <0 0 0 2 &pcie_intc1 1>,
 391                                                 <0 0 0 3 &pcie_intc1 2>,
 392                                                 <0 0 0 4 &pcie_intc1 3>;
 393
 394                                 pcie_intc1: interrupt-controller {
 395                                         interrupt-controller;
 396                                         #address-cells = <0>;
 397                                         #interrupt-cells = <1>;
 398                                 };
 399                         };
 400                 };
 401
 402                 pciephy1: pcie-phy@1a14a000 {
 403                         compatible = "mediatek,generic-tphy-v2";
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         ranges = <0 0x1a14a000 0x1000>;
 407                         status = "disabled";
 408
 409                         pcieport1: port1phy@0 {
 410                                 reg = <0 0x1000>;
 411                                 clocks = <&clk20m>;
 412                                 clock-names = "ref";
 413                                 #phy-cells = <1>;
 414                                 status = "okay";
 415                         };
 416                 };
 417
 418                 ethsys: syscon@1b000000 {
 419                         compatible = "mediatek,mt7629-ethsys", "syscon";
 420                         reg = <0x1b000000 0x1000>;
 421                         #clock-cells = <1>;
 422                         #reset-cells = <1>;
 423                 };
 424
 425                 eth: ethernet@1b100000 {
 426                         compatible = "mediatek,mt7629-eth","syscon";
 427                         reg = <0x1b100000 0x20000>;
 428                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 429                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 430                                      <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 431                         clocks = <&topckgen CLK_TOP_ETH_SEL>,
 432                                  <&topckgen CLK_TOP_F10M_REF_SEL>,
 433                                  <&ethsys CLK_ETH_ESW_EN>,
 434                                  <&ethsys CLK_ETH_GP0_EN>,
 435                                  <&ethsys CLK_ETH_GP1_EN>,
 436                                  <&ethsys CLK_ETH_GP2_EN>,
 437                                  <&ethsys CLK_ETH_FE_EN>,
 438                                  <&sgmiisys0 CLK_SGMII_TX_EN>,
 439                                  <&sgmiisys0 CLK_SGMII_RX_EN>,
 440                                  <&sgmiisys0 CLK_SGMII_CDR_REF>,
 441                                  <&sgmiisys0 CLK_SGMII_CDR_FB>,
 442                                  <&sgmiisys1 CLK_SGMII_TX_EN>,
 443                                  <&sgmiisys1 CLK_SGMII_RX_EN>,
 444                                  <&sgmiisys1 CLK_SGMII_CDR_REF>,
 445                                  <&sgmiisys1 CLK_SGMII_CDR_FB>,
 446                                  <&apmixedsys CLK_APMIXED_SGMIPLL>,
 447                                  <&apmixedsys CLK_APMIXED_ETH2PLL>;
 448                         clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
 449                                       "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
 450                                       "sgmii_cdr_ref", "sgmii_cdr_fb",
 451                                       "sgmii2_tx250m", "sgmii2_rx250m",
 452                                       "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 453                                       "sgmii_ck", "eth2pll";
 454                         assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
 455                                           <&topckgen CLK_TOP_F10M_REF_SEL>;
 456                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
 457                                                  <&topckgen CLK_TOP_SGMIIPLL_D2>;
 458                         power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 459                         mediatek,ethsys = <&ethsys>;
 460                         mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 461                         mediatek,infracfg = <&infracfg>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         status = "disabled";
 465                 };
 466
 467                 sgmiisys0: syscon@1b128000 {
 468                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
 469                         reg = <0x1b128000 0x3000>;
 470                         #clock-cells = <1>;
 471                 };
 472
 473                 sgmiisys1: syscon@1b130000 {
 474                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
 475                         reg = <0x1b130000 0x3000>;
 476                         #clock-cells = <1>;
 477                 };
 478         };
 479 };