arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25 #include "skeleton64.dtsi"
  26
  27 / {
  28         compatible = "mediatek,mt7623";
  29         interrupt-parent = <&sysirq>;
  30
  31         cpu_opp_table: opp-table {
  32                 compatible = "operating-points-v2";
  33                 opp-shared;
  34
  35                 opp-98000000 {
  36                         opp-hz = /bits/ 64 <98000000>;
  37                         opp-microvolt = <1050000>;
  38                 };
  39
  40                 opp-198000000 {
  41                         opp-hz = /bits/ 64 <198000000>;
  42                         opp-microvolt = <1050000>;
  43                 };
  44
  45                 opp-398000000 {
  46                         opp-hz = /bits/ 64 <398000000>;
  47                         opp-microvolt = <1050000>;
  48                 };
  49
  50                 opp-598000000 {
  51                         opp-hz = /bits/ 64 <598000000>;
  52                         opp-microvolt = <1050000>;
  53                 };
  54
  55                 opp-747500000 {
  56                         opp-hz = /bits/ 64 <747500000>;
  57                         opp-microvolt = <1050000>;
  58                 };
  59
  60                 opp-1040000000 {
  61                         opp-hz = /bits/ 64 <1040000000>;
  62                         opp-microvolt = <1150000>;
  63                 };
  64
  65                 opp-1196000000 {
  66                         opp-hz = /bits/ 64 <1196000000>;
  67                         opp-microvolt = <1200000>;
  68                 };
  69
  70                 opp-1300000000 {
  71                         opp-hz = /bits/ 64 <1300000000>;
  72                         opp-microvolt = <1300000>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 enable-method = "mediatek,mt6589-smp";
  80
  81                 cpu0: cpu@0 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x0>;
  85                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  86                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         #cooling-cells = <2>;
  90                         clock-frequency = <1300000000>;
  91                 };
  92
  93                 cpu1: cpu@1 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x1>;
  97                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  98                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  99                         clock-names = "cpu", "intermediate";
 100                         operating-points-v2 = <&cpu_opp_table>;
 101                         clock-frequency = <1300000000>;
 102                 };
 103
 104                 cpu2: cpu@2 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a7";
 107                         reg = <0x2>;
 108                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 109                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 110                         clock-names = "cpu", "intermediate";
 111                         operating-points-v2 = <&cpu_opp_table>;
 112                         clock-frequency = <1300000000>;
 113                 };
 114
 115                 cpu3: cpu@3 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a7";
 118                         reg = <0x3>;
 119                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 120                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 121                         clock-names = "cpu", "intermediate";
 122                         operating-points-v2 = <&cpu_opp_table>;
 123                         clock-frequency = <1300000000>;
 124                 };
 125         };
 126
 127         system_clk: dummy13m {
 128                 compatible = "fixed-clock";
 129                 clock-frequency = <13000000>;
 130                 #clock-cells = <0>;
 131         };
 132
 133         rtc32k: oscillator@1 {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <32000>;
 137                 clock-output-names = "rtc32k";
 138         };
 139
 140         clk26m: oscillator@0 {
 141                 compatible = "fixed-clock";
 142                 #clock-cells = <0>;
 143                 clock-frequency = <26000000>;
 144                 clock-output-names = "clk26m";
 145         };
 146
 147         thermal-zones {
 148                         cpu_thermal: cpu-thermal {
 149                                 polling-delay-passive = <1000>;
 150                                 polling-delay = <1000>;
 151
 152                                 thermal-sensors = <&thermal 0>;
 153
 154                                 trips {
 155                                         cpu_passive: cpu-passive {
 156                                                 temperature = <47000>;
 157                                                 hysteresis = <2000>;
 158                                                 type = "passive";
 159                                         };
 160
 161                                         cpu_active: cpu-active {
 162                                                 temperature = <67000>;
 163                                                 hysteresis = <2000>;
 164                                                 type = "active";
 165                                         };
 166
 167                                         cpu_hot: cpu-hot {
 168                                                 temperature = <87000>;
 169                                                 hysteresis = <2000>;
 170                                                 type = "hot";
 171                                         };
 172
 173                                         cpu-crit {
 174                                                 temperature = <107000>;
 175                                                 hysteresis = <2000>;
 176                                                 type = "critical";
 177                                         };
 178                                 };
 179
 180                         cooling-maps {
 181                                 map0 {
 182                                         trip = <&cpu_passive>;
 183                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 184                                 };
 185
 186                                 map1 {
 187                                         trip = <&cpu_active>;
 188                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 189                                 };
 190
 191                                 map2 {
 192                                         trip = <&cpu_hot>;
 193                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 194                                 };
 195                         };
 196                 };
 197         };
 198
 199         timer {
 200                 compatible = "arm,armv7-timer";
 201                 interrupt-parent = <&gic>;
 202                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 203                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 204                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 205                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 206                 clock-frequency = <13000000>;
 207                 arm,cpu-registers-not-fw-configured;
 208         };
 209
 210         topckgen: syscon@10000000 {
 211                 compatible = "mediatek,mt7623-topckgen",
 212                              "mediatek,mt2701-topckgen",
 213                              "syscon";
 214                 reg = <0 0x10000000 0 0x1000>;
 215                 #clock-cells = <1>;
 216         };
 217
 218         infracfg: syscon@10001000 {
 219                 compatible = "mediatek,mt7623-infracfg",
 220                              "mediatek,mt2701-infracfg",
 221                              "syscon";
 222                 reg = <0 0x10001000 0 0x1000>;
 223                 #clock-cells = <1>;
 224                 #reset-cells = <1>;
 225         };
 226
 227         pericfg: syscon@10003000 {
 228                 compatible =  "mediatek,mt7623-pericfg",
 229                               "mediatek,mt2701-pericfg",
 230                               "syscon";
 231                 reg = <0 0x10003000 0 0x1000>;
 232                 #clock-cells = <1>;
 233                 #reset-cells = <1>;
 234         };
 235
 236         pio: pinctrl@10005000 {
 237                 compatible = "mediatek,mt7623-pinctrl";
 238                 reg = <0 0x1000b000 0 0x1000>;
 239                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 240                 pins-are-numbered;
 241                 gpio-controller;
 242                 #gpio-cells = <2>;
 243                 interrupt-controller;
 244                 interrupt-parent = <&gic>;
 245                 #interrupt-cells = <2>;
 246                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 248         };
 249
 250         syscfg_pctl_a: syscfg@10005000 {
 251                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 252                 reg = <0 0x10005000 0 0x1000>;
 253         };
 254
 255         scpsys: scpsys@10006000 {
 256                 compatible = "mediatek,mt7623-scpsys",
 257                              "mediatek,mt2701-scpsys",
 258                              "syscon";
 259                 #power-domain-cells = <1>;
 260                 reg = <0 0x10006000 0 0x1000>;
 261                 infracfg = <&infracfg>;
 262                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 263                          <&topckgen CLK_TOP_MFG_SEL>,
 264                          <&topckgen CLK_TOP_ETHIF_SEL>;
 265                 clock-names = "mm", "mfg", "ethif";
 266         };
 267
 268         watchdog: watchdog@10007000 {
 269                 compatible = "mediatek,mt7623-wdt",
 270                              "mediatek,mt6589-wdt";
 271                 reg = <0 0x10007000 0 0x100>;
 272         };
 273
 274         timer: timer@10008000 {
 275                 compatible = "mediatek,mt7623-timer",
 276                              "mediatek,mt6577-timer";
 277                 reg = <0 0x10008000 0 0x80>;
 278                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 279                 clocks = <&system_clk>, <&rtc32k>;
 280                 clock-names = "system-clk", "rtc-clk";
 281         };
 282
 283         pwrap: pwrap@1000d000 {
 284                 compatible = "mediatek,mt7623-pwrap",
 285                              "mediatek,mt2701-pwrap";
 286                 reg = <0 0x1000d000 0 0x1000>;
 287                 reg-names = "pwrap";
 288                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 289                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 290                 reset-names = "pwrap";
 291                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 292                          <&infracfg CLK_INFRA_PMICWRAP>;
 293                 clock-names = "spi", "wrap";
 294         };
 295
 296         cir: cir@10013000 {
 297                 compatible = "mediatek,mt7623-cir";
 298                 reg = <0 0x10013000 0 0x1000>;
 299                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 300                 clocks = <&infracfg CLK_INFRA_IRRX>;
 301                 clock-names = "clk";
 302                 status = "disabled";
 303         };
 304
 305         sysirq: interrupt-controller@10200100 {
 306                 compatible = "mediatek,mt7623-sysirq",
 307                              "mediatek,mt6577-sysirq";
 308                 interrupt-controller;
 309                 #interrupt-cells = <3>;
 310                 interrupt-parent = <&gic>;
 311                 reg = <0 0x10200100 0 0x1c>;
 312         };
 313
 314         efuse: efuse@10206000 {
 315                 compatible = "mediatek,mt7623-efuse",
 316                              "mediatek,mt8173-efuse";
 317                 reg = <0 0x10206000 0 0x1000>;
 318                 #address-cells = <1>;
 319                 #size-cells = <1>;
 320                 thermal_calibration_data: calib@424 {
 321                         reg = <0x424 0xc>;
 322                 };
 323         };
 324
 325         apmixedsys: syscon@10209000 {
 326                 compatible = "mediatek,mt7623-apmixedsys",
 327                              "mediatek,mt2701-apmixedsys",
 328                              "syscon";
 329                 reg = <0 0x10209000 0 0x1000>;
 330                 #clock-cells = <1>;
 331         };
 332
 333         rng: rng@1020f000 {
 334                 compatible = "mediatek,mt7623-rng";
 335                 reg = <0 0x1020f000 0 0x1000>;
 336                 clocks = <&infracfg CLK_INFRA_TRNG>;
 337                 clock-names = "rng";
 338         };
 339
 340         gic: interrupt-controller@10211000 {
 341                 compatible = "arm,cortex-a7-gic";
 342                 interrupt-controller;
 343                 #interrupt-cells = <3>;
 344                 interrupt-parent = <&gic>;
 345                 reg = <0 0x10211000 0 0x1000>,
 346                       <0 0x10212000 0 0x2000>,
 347                       <0 0x10214000 0 0x2000>,
 348                       <0 0x10216000 0 0x2000>;
 349         };
 350
 351         auxadc: adc@11001000 {
 352                 compatible = "mediatek,mt7623-auxadc",
 353                              "mediatek,mt2701-auxadc";
 354                 reg = <0 0x11001000 0 0x1000>;
 355                 clocks = <&pericfg CLK_PERI_AUXADC>;
 356                 clock-names = "main";
 357                 #io-channel-cells = <1>;
 358         };
 359
 360         uart0: serial@11002000 {
 361                 compatible = "mediatek,mt7623-uart",
 362                              "mediatek,mt6577-uart";
 363                 reg = <0 0x11002000 0 0x400>;
 364                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 365                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 366                          <&pericfg CLK_PERI_UART0>;
 367                 clock-names = "baud", "bus";
 368                 status = "disabled";
 369         };
 370
 371         uart1: serial@11003000 {
 372                 compatible = "mediatek,mt7623-uart",
 373                              "mediatek,mt6577-uart";
 374                 reg = <0 0x11003000 0 0x400>;
 375                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 376                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 377                          <&pericfg CLK_PERI_UART1>;
 378                 clock-names = "baud", "bus";
 379                 status = "disabled";
 380         };
 381
 382         uart2: serial@11004000 {
 383                 compatible = "mediatek,mt7623-uart",
 384                              "mediatek,mt6577-uart";
 385                 reg = <0 0x11004000 0 0x400>;
 386                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 387                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 388                          <&pericfg CLK_PERI_UART2>;
 389                 clock-names = "baud", "bus";
 390                 status = "disabled";
 391         };
 392
 393         uart3: serial@11005000 {
 394                 compatible = "mediatek,mt7623-uart",
 395                              "mediatek,mt6577-uart";
 396                 reg = <0 0x11005000 0 0x400>;
 397                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 398                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 399                          <&pericfg CLK_PERI_UART3>;
 400                 clock-names = "baud", "bus";
 401                 status = "disabled";
 402         };
 403
 404         pwm: pwm@11006000 {
 405                 compatible = "mediatek,mt7623-pwm";
 406                 reg = <0 0x11006000 0 0x1000>;
 407                 #pwm-cells = <2>;
 408                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 409                          <&pericfg CLK_PERI_PWM>,
 410                          <&pericfg CLK_PERI_PWM1>,
 411                          <&pericfg CLK_PERI_PWM2>,
 412                          <&pericfg CLK_PERI_PWM3>,
 413                          <&pericfg CLK_PERI_PWM4>,
 414                          <&pericfg CLK_PERI_PWM5>;
 415                 clock-names = "top", "main", "pwm1", "pwm2",
 416                               "pwm3", "pwm4", "pwm5";
 417                 status = "disabled";
 418         };
 419
 420         i2c0: i2c@11007000 {
 421                 compatible = "mediatek,mt7623-i2c",
 422                              "mediatek,mt6577-i2c";
 423                 reg = <0 0x11007000 0 0x70>,
 424                       <0 0x11000200 0 0x80>;
 425                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 426                 clock-div = <16>;
 427                 clocks = <&pericfg CLK_PERI_I2C0>,
 428                          <&pericfg CLK_PERI_AP_DMA>;
 429                 clock-names = "main", "dma";
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 status = "disabled";
 433         };
 434
 435         i2c1: i2c@11008000 {
 436                 compatible = "mediatek,mt7623-i2c",
 437                              "mediatek,mt6577-i2c";
 438                 reg = <0 0x11008000 0 0x70>,
 439                       <0 0x11000280 0 0x80>;
 440                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 441                 clock-div = <16>;
 442                 clocks = <&pericfg CLK_PERI_I2C1>,
 443                          <&pericfg CLK_PERI_AP_DMA>;
 444                 clock-names = "main", "dma";
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 status = "disabled";
 448         };
 449
 450         i2c2: i2c@11009000 {
 451                 compatible = "mediatek,mt7623-i2c",
 452                              "mediatek,mt6577-i2c";
 453                 reg = <0 0x11009000 0 0x70>,
 454                       <0 0x11000300 0 0x80>;
 455                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 456                 clock-div = <16>;
 457                 clocks = <&pericfg CLK_PERI_I2C2>,
 458                          <&pericfg CLK_PERI_AP_DMA>;
 459                 clock-names = "main", "dma";
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 status = "disabled";
 463         };
 464
 465         spi0: spi@1100a000 {
 466                 compatible = "mediatek,mt7623-spi",
 467                              "mediatek,mt2701-spi";
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 reg = <0 0x1100a000 0 0x100>;
 471                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 472                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 473                          <&topckgen CLK_TOP_SPI0_SEL>,
 474                          <&pericfg CLK_PERI_SPI0>;
 475                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 476                 status = "disabled";
 477         };
 478
 479         thermal: thermal@1100b000 {
 480                 #thermal-sensor-cells = <1>;
 481                 compatible = "mediatek,mt7623-thermal",
 482                              "mediatek,mt2701-thermal";
 483                 reg = <0 0x1100b000 0 0x1000>;
 484                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 485                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 486                 clock-names = "therm", "auxadc";
 487                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 488                 reset-names = "therm";
 489                 mediatek,auxadc = <&auxadc>;
 490                 mediatek,apmixedsys = <&apmixedsys>;
 491                 nvmem-cells = <&thermal_calibration_data>;
 492                 nvmem-cell-names = "calibration-data";
 493         };
 494
 495         nandc: nfi@1100d000 {
 496                 compatible = "mediatek,mt7623-nfc",
 497                              "mediatek,mt2701-nfc";
 498                 reg = <0 0x1100d000 0 0x1000>;
 499                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 500                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 501                 clocks = <&pericfg CLK_PERI_NFI>,
 502                          <&pericfg CLK_PERI_NFI_PAD>;
 503                 clock-names = "nfi_clk", "pad_clk";
 504                 status = "disabled";
 505                 ecc-engine = <&bch>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508         };
 509
 510         bch: ecc@1100e000 {
 511                 compatible = "mediatek,mt7623-ecc",
 512                              "mediatek,mt2701-ecc";
 513                 reg = <0 0x1100e000 0 0x1000>;
 514                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 515                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 516                 clock-names = "nfiecc_clk";
 517                 status = "disabled";
 518         };
 519
 520         spi1: spi@11016000 {
 521                 compatible = "mediatek,mt7623-spi",
 522                              "mediatek,mt2701-spi";
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 reg = <0 0x11016000 0 0x100>;
 526                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 527                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 528                          <&topckgen CLK_TOP_SPI1_SEL>,
 529                          <&pericfg CLK_PERI_SPI1>;
 530                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 531                 status = "disabled";
 532         };
 533
 534         spi2: spi@11017000 {
 535                 compatible = "mediatek,mt7623-spi",
 536                              "mediatek,mt2701-spi";
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 reg = <0 0x11017000 0 0x1000>;
 540                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 541                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 542                          <&topckgen CLK_TOP_SPI2_SEL>,
 543                          <&pericfg CLK_PERI_SPI2>;
 544                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 545                 status = "disabled";
 546         };
 547
 548         afe: audio-controller@11220000 {
 549                 compatible = "mediatek,mt7623-audio",
 550                              "mediatek,mt2701-audio";
 551                 reg = <0 0x11220000 0 0x2000>,
 552                       <0 0x112a0000 0 0x20000>;
 553                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 554                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 555                 interrupt-names = "afe", "asys";
 556                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 557
 558                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 559                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 560                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 561                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 562                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 563                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 564                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 565                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 566                          <&topckgen CLK_TOP_APLL_SEL>,
 567                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 568                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 569                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 570                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 571                          <&topckgen CLK_TOP_AUDPLL>,
 572                          <&topckgen CLK_TOP_AUDPLL_D4>,
 573                          <&topckgen CLK_TOP_AUDPLL_D8>,
 574                          <&topckgen CLK_TOP_AUDPLL_D16>,
 575                          <&topckgen CLK_TOP_AUDPLL_D24>,
 576                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 577                          <&clk26m>,
 578                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 579                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 580                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 581                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 582                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 583                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 584                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 585                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 586                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 587                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 588                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 589                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 590                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 591                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 592                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 593                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 594                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 595                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 596                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 597                          <&topckgen CLK_TOP_ASM_M_SEL>,
 598                          <&topckgen CLK_TOP_ASM_H_SEL>,
 599                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 600                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 601                          <&topckgen CLK_TOP_SYSPLL_D5>;
 602
 603                 clock-names = "infra_sys_audio_clk",
 604                          "top_audio_mux1_sel",
 605                          "top_audio_mux2_sel",
 606                          "top_audio_mux1_div",
 607                          "top_audio_mux2_div",
 608                          "top_audio_48k_timing",
 609                          "top_audio_44k_timing",
 610                          "top_audpll_mux_sel",
 611                          "top_apll_sel",
 612                          "top_aud1_pll_98M",
 613                          "top_aud2_pll_90M",
 614                          "top_hadds2_pll_98M",
 615                          "top_hadds2_pll_294M",
 616                          "top_audpll",
 617                          "top_audpll_d4",
 618                          "top_audpll_d8",
 619                          "top_audpll_d16",
 620                          "top_audpll_d24",
 621                          "top_audintbus_sel",
 622                          "clk_26m",
 623                          "top_syspll1_d4",
 624                          "top_aud_k1_src_sel",
 625                          "top_aud_k2_src_sel",
 626                          "top_aud_k3_src_sel",
 627                          "top_aud_k4_src_sel",
 628                          "top_aud_k5_src_sel",
 629                          "top_aud_k6_src_sel",
 630                          "top_aud_k1_src_div",
 631                          "top_aud_k2_src_div",
 632                          "top_aud_k3_src_div",
 633                          "top_aud_k4_src_div",
 634                          "top_aud_k5_src_div",
 635                          "top_aud_k6_src_div",
 636                          "top_aud_i2s1_mclk",
 637                          "top_aud_i2s2_mclk",
 638                          "top_aud_i2s3_mclk",
 639                          "top_aud_i2s4_mclk",
 640                          "top_aud_i2s5_mclk",
 641                          "top_aud_i2s6_mclk",
 642                          "top_asm_m_sel",
 643                          "top_asm_h_sel",
 644                          "top_univpll2_d4",
 645                          "top_univpll2_d2",
 646                          "top_syspll_d5";
 647         };
 648
 649         mmc0: mmc@11230000 {
 650                 compatible = "mediatek,mt7623-mmc",
 651                              "mediatek,mt2701-mmc";
 652                 reg = <0 0x11230000 0 0x1000>;
 653                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 654                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 655                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 656                 clock-names = "source", "hclk";
 657                 status = "disabled";
 658         };
 659
 660         mmc1: mmc@11240000 {
 661                 compatible = "mediatek,mt7623-mmc",
 662                              "mediatek,mt2701-mmc";
 663                 reg = <0 0x11240000 0 0x1000>;
 664                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 665                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 666                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 667                 clock-names = "source", "hclk";
 668                 status = "disabled";
 669         };
 670
 671         hifsys: syscon@1a000000 {
 672                 compatible = "mediatek,mt7623-hifsys",
 673                              "mediatek,mt2701-hifsys",
 674                              "syscon";
 675                 reg = <0 0x1a000000 0 0x1000>;
 676                 #clock-cells = <1>;
 677                 #reset-cells = <1>;
 678         };
 679
 680         pcie: pcie@1a140000 {
 681                 compatible = "mediatek,mt7623-pcie";
 682                 device_type = "pci";
 683                 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
 684                       <0 0x1a142000 0 0x1000>, /* Port0 registers */
 685                       <0 0x1a143000 0 0x1000>, /* Port1 registers */
 686                       <0 0x1a144000 0 0x1000>; /* Port2 registers */
 687                 reg-names = "subsys", "port0", "port1", "port2";
 688                 #address-cells = <3>;
 689                 #size-cells = <2>;
 690                 #interrupt-cells = <1>;
 691                 interrupt-map-mask = <0xf800 0 0 0>;
 692                 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 693                                 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 694                                 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 695                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 696                          <&hifsys CLK_HIFSYS_PCIE0>,
 697                          <&hifsys CLK_HIFSYS_PCIE1>,
 698                          <&hifsys CLK_HIFSYS_PCIE2>;
 699                 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
 700                 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 701                          <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 702                          <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 703                 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
 704                 phys = <&pcie0_port PHY_TYPE_PCIE>,
 705                        <&pcie1_port PHY_TYPE_PCIE>,
 706                        <&u3port1 PHY_TYPE_PCIE>;
 707                 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
 708                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 709                 bus-range = <0x00 0xff>;
 710                 status = "disabled";
 711                 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
 712                           0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
 713
 714                 pcie@0,0 {
 715                         reg = <0x0000 0 0 0 0>;
 716                         #address-cells = <3>;
 717                         #size-cells = <2>;
 718                         #interrupt-cells = <1>;
 719                         interrupt-map-mask = <0 0 0 0>;
 720                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 721                         ranges;
 722                         num-lanes = <1>;
 723                         status = "disabled";
 724                 };
 725
 726                 pcie@1,0 {
 727                         reg = <0x0800 0 0 0 0>;
 728                         #address-cells = <3>;
 729                         #size-cells = <2>;
 730                         #interrupt-cells = <1>;
 731                         interrupt-map-mask = <0 0 0 0>;
 732                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 733                         ranges;
 734                         num-lanes = <1>;
 735                         status = "disabled";
 736                 };
 737
 738                 pcie@2,0 {
 739                         reg = <0x1000 0 0 0 0>;
 740                         #address-cells = <3>;
 741                         #size-cells = <2>;
 742                         #interrupt-cells = <1>;
 743                         interrupt-map-mask = <0 0 0 0>;
 744                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 745                         ranges;
 746                         num-lanes = <1>;
 747                         status = "disabled";
 748                 };
 749         };
 750
 751         pcie0_phy: pcie-phy@1a149000 {
 752                 compatible = "mediatek,generic-tphy-v1";
 753                 reg = <0 0x1a149000 0 0x0700>;
 754                 #address-cells = <2>;
 755                 #size-cells = <2>;
 756                 ranges;
 757                 status = "disabled";
 758
 759                 pcie0_port: pcie-phy@1a149900 {
 760                         reg = <0 0x1a149900 0 0x0700>;
 761                         clocks = <&clk26m>;
 762                         clock-names = "ref";
 763                         #phy-cells = <1>;
 764                         status = "okay";
 765                 };
 766         };
 767
 768         pcie1_phy: pcie-phy@1a14a000 {
 769                 compatible = "mediatek,generic-tphy-v1";
 770                 reg = <0 0x1a14a000 0 0x0700>;
 771                 #address-cells = <2>;
 772                 #size-cells = <2>;
 773                 ranges;
 774                 status = "disabled";
 775
 776                 pcie1_port: pcie-phy@1a14a900 {
 777                         reg = <0 0x1a14a900 0 0x0700>;
 778                         clocks = <&clk26m>;
 779                         clock-names = "ref";
 780                         #phy-cells = <1>;
 781                         status = "okay";
 782                 };
 783         };
 784
 785         usb1: usb@1a1c0000 {
 786                 compatible = "mediatek,mt7623-xhci",
 787                              "mediatek,mt8173-xhci";
 788                 reg = <0 0x1a1c0000 0 0x1000>,
 789                       <0 0x1a1c4700 0 0x0100>;
 790                 reg-names = "mac", "ippc";
 791                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 792                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 793                          <&topckgen CLK_TOP_ETHIF_SEL>;
 794                 clock-names = "sys_ck", "ref_ck";
 795                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 796                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 797                 status = "disabled";
 798         };
 799
 800         u3phy1: usb-phy@1a1c4000 {
 801                 compatible = "mediatek,mt7623-u3phy",
 802                              "mediatek,mt2701-u3phy";
 803                 reg = <0 0x1a1c4000 0 0x0700>;
 804                 #address-cells = <2>;
 805                 #size-cells = <2>;
 806                 ranges;
 807                 status = "disabled";
 808
 809                 u2port0: usb-phy@1a1c4800 {
 810                         reg = <0 0x1a1c4800 0 0x0100>;
 811                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 812                         clock-names = "ref";
 813                         #phy-cells = <1>;
 814                         status = "okay";
 815                 };
 816
 817                 u3port0: usb-phy@1a1c4900 {
 818                         reg = <0 0x1a1c4900 0 0x0700>;
 819                         clocks = <&clk26m>;
 820                         clock-names = "ref";
 821                         #phy-cells = <1>;
 822                         status = "okay";
 823                 };
 824         };
 825
 826         usb2: usb@1a240000 {
 827                 compatible = "mediatek,mt7623-xhci",
 828                              "mediatek,mt8173-xhci";
 829                 reg = <0 0x1a240000 0 0x1000>,
 830                       <0 0x1a244700 0 0x0100>;
 831                 reg-names = "mac", "ippc";
 832                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 833                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 834                          <&topckgen CLK_TOP_ETHIF_SEL>;
 835                 clock-names = "sys_ck", "ref_ck";
 836                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 837                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 838                 status = "disabled";
 839         };
 840
 841         u3phy2: usb-phy@1a244000 {
 842                 compatible = "mediatek,mt7623-u3phy",
 843                              "mediatek,mt2701-u3phy";
 844                 reg = <0 0x1a244000 0 0x0700>;
 845                 #address-cells = <2>;
 846                 #size-cells = <2>;
 847                 ranges;
 848                 status = "disabled";
 849
 850                 u2port1: usb-phy@1a244800 {
 851                         reg = <0 0x1a244800 0 0x0100>;
 852                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 853                         clock-names = "ref";
 854                         #phy-cells = <1>;
 855                         status = "okay";
 856                 };
 857
 858                 u3port1: usb-phy@1a244900 {
 859                         reg = <0 0x1a244900 0 0x0700>;
 860                         clocks = <&clk26m>;
 861                         clock-names = "ref";
 862                         #phy-cells = <1>;
 863                         status = "okay";
 864                 };
 865         };
 866
 867         ethsys: syscon@1b000000 {
 868                 compatible = "mediatek,mt7623-ethsys",
 869                              "mediatek,mt2701-ethsys",
 870                              "syscon";
 871                 reg = <0 0x1b000000 0 0x1000>;
 872                 #clock-cells = <1>;
 873                 #reset-cells = <1>;
 874         };
 875
 876         eth: ethernet@1b100000 {
 877                 compatible = "mediatek,mt7623-eth",
 878                              "mediatek,mt2701-eth",
 879                              "syscon";
 880                 reg = <0 0x1b100000 0 0x20000>;
 881                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 882                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 883                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 884                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 885                          <&ethsys CLK_ETHSYS_ESW>,
 886                          <&ethsys CLK_ETHSYS_GP1>,
 887                          <&ethsys CLK_ETHSYS_GP2>,
 888                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 889                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 890                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 891                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 892                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 893                 reset-names = "fe", "gmac", "ppe";
 894                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 895                 mediatek,ethsys = <&ethsys>;
 896                 mediatek,pctl = <&syscfg_pctl_a>;
 897                 #address-cells = <1>;
 898                 #size-cells = <0>;
 899                 status = "disabled";
 900         };
 901
 902         crypto: crypto@1b240000 {
 903                 compatible = "mediatek,eip97-crypto";
 904                 reg = <0 0x1b240000 0 0x20000>;
 905                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 906                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 907                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 908                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 909                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 910                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 911                 clock-names = "cryp";
 912                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 913                 status = "disabled";
 914         };
 915 };