arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include "skeleton64.dtsi"
  25
  26 / {
  27         compatible = "mediatek,mt7623";
  28         interrupt-parent = <&sysirq>;
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 enable-method = "mediatek,mt6589-smp";
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x0>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a7";
  43                         reg = <0x1>;
  44                 };
  45                 cpu@2 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a7";
  48                         reg = <0x2>;
  49                 };
  50                 cpu@3 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0x3>;
  54                 };
  55         };
  56
  57         system_clk: dummy13m {
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <13000000>;
  60                 #clock-cells = <0>;
  61         };
  62
  63         rtc32k: oscillator@1 {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <32000>;
  67                 clock-output-names = "rtc32k";
  68         };
  69
  70         clk26m: oscillator@0 {
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0>;
  73                 clock-frequency = <26000000>;
  74                 clock-output-names = "clk26m";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupt-parent = <&gic>;
  80                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  81                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  82                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  83                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  84                 clock-frequency = <13000000>;
  85                 arm,cpu-registers-not-fw-configured;
  86         };
  87
  88         topckgen: syscon@10000000 {
  89                 compatible = "mediatek,mt7623-topckgen",
  90                              "mediatek,mt2701-topckgen",
  91                              "syscon";
  92                 reg = <0 0x10000000 0 0x1000>;
  93                 #clock-cells = <1>;
  94         };
  95
  96         infracfg: syscon@10001000 {
  97                 compatible = "mediatek,mt7623-infracfg",
  98                              "mediatek,mt2701-infracfg",
  99                              "syscon";
 100                 reg = <0 0x10001000 0 0x1000>;
 101                 #clock-cells = <1>;
 102                 #reset-cells = <1>;
 103         };
 104
 105         pericfg: syscon@10003000 {
 106                 compatible =  "mediatek,mt7623-pericfg",
 107                               "mediatek,mt2701-pericfg",
 108                               "syscon";
 109                 reg = <0 0x10003000 0 0x1000>;
 110                 #clock-cells = <1>;
 111                 #reset-cells = <1>;
 112         };
 113
 114         pio: pinctrl@10005000 {
 115                 compatible = "mediatek,mt7623-pinctrl",
 116                              "mediatek,mt2701-pinctrl";
 117                 reg = <0 0x1000b000 0 0x1000>;
 118                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 119                 pins-are-numbered;
 120                 gpio-controller;
 121                 #gpio-cells = <2>;
 122                 interrupt-controller;
 123                 interrupt-parent = <&gic>;
 124                 #interrupt-cells = <2>;
 125                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 127         };
 128
 129         syscfg_pctl_a: syscfg@10005000 {
 130                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 131                 reg = <0 0x10005000 0 0x1000>;
 132         };
 133
 134         scpsys: scpsys@10006000 {
 135                 compatible = "mediatek,mt7623-scpsys",
 136                              "mediatek,mt2701-scpsys",
 137                              "syscon";
 138                 #power-domain-cells = <1>;
 139                 reg = <0 0x10006000 0 0x1000>;
 140                 infracfg = <&infracfg>;
 141                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 142                          <&topckgen CLK_TOP_MFG_SEL>,
 143                          <&topckgen CLK_TOP_ETHIF_SEL>;
 144                 clock-names = "mm", "mfg", "ethif";
 145         };
 146
 147         watchdog: watchdog@10007000 {
 148                 compatible = "mediatek,mt7623-wdt",
 149                              "mediatek,mt6589-wdt";
 150                 reg = <0 0x10007000 0 0x100>;
 151         };
 152
 153         timer: timer@10008000 {
 154                 compatible = "mediatek,mt7623-timer",
 155                              "mediatek,mt6577-timer";
 156                 reg = <0 0x10008000 0 0x80>;
 157                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 158                 clocks = <&system_clk>, <&rtc32k>;
 159                 clock-names = "system-clk", "rtc-clk";
 160         };
 161
 162         pwrap: pwrap@1000d000 {
 163                 compatible = "mediatek,mt7623-pwrap",
 164                              "mediatek,mt2701-pwrap";
 165                 reg = <0 0x1000d000 0 0x1000>;
 166                 reg-names = "pwrap";
 167                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 168                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 169                 reset-names = "pwrap";
 170                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 171                          <&infracfg CLK_INFRA_PMICWRAP>;
 172                 clock-names = "spi", "wrap";
 173         };
 174
 175         cir: cir@0x10013000 {
 176                 compatible = "mediatek,mt7623-cir";
 177                 reg = <0 0x10013000 0 0x1000>;
 178                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 179                 clocks = <&infracfg CLK_INFRA_IRRX>;
 180                 clock-names = "clk";
 181                 status = "disabled";
 182         };
 183
 184         sysirq: interrupt-controller@10200100 {
 185                 compatible = "mediatek,mt7623-sysirq",
 186                              "mediatek,mt6577-sysirq";
 187                 interrupt-controller;
 188                 #interrupt-cells = <3>;
 189                 interrupt-parent = <&gic>;
 190                 reg = <0 0x10200100 0 0x1c>;
 191         };
 192
 193         efuse: efuse@10206000 {
 194                 compatible = "mediatek,mt7623-efuse",
 195                              "mediatek,mt8173-efuse";
 196                 reg        = <0 0x10206000 0 0x1000>;
 197                 #address-cells = <1>;
 198                 #size-cells = <1>;
 199                 thermal_calibration_data: calib@424 {
 200                         reg = <0x424 0xc>;
 201                 };
 202         };
 203
 204         apmixedsys: syscon@10209000 {
 205                 compatible = "mediatek,mt7623-apmixedsys",
 206                              "mediatek,mt2701-apmixedsys",
 207                              "syscon";
 208                 reg = <0 0x10209000 0 0x1000>;
 209                 #clock-cells = <1>;
 210         };
 211
 212         rng: rng@1020f000 {
 213                 compatible = "mediatek,mt7623-rng";
 214                 reg = <0 0x1020f000 0 0x1000>;
 215                 clocks = <&infracfg CLK_INFRA_TRNG>;
 216                 clock-names = "rng";
 217         };
 218
 219         gic: interrupt-controller@10211000 {
 220                 compatible = "arm,cortex-a7-gic";
 221                 interrupt-controller;
 222                 #interrupt-cells = <3>;
 223                 interrupt-parent = <&gic>;
 224                 reg = <0 0x10211000 0 0x1000>,
 225                       <0 0x10212000 0 0x2000>,
 226                       <0 0x10214000 0 0x2000>,
 227                       <0 0x10216000 0 0x2000>;
 228         };
 229
 230         auxadc: adc@11001000 {
 231                 compatible = "mediatek,mt7623-auxadc",
 232                              "mediatek,mt2701-auxadc";
 233                 reg = <0 0x11001000 0 0x1000>;
 234                 clocks = <&pericfg CLK_PERI_AUXADC>;
 235                 clock-names = "main";
 236                 #io-channel-cells = <1>;
 237         };
 238
 239         uart0: serial@11002000 {
 240                 compatible = "mediatek,mt7623-uart",
 241                              "mediatek,mt6577-uart";
 242                 reg = <0 0x11002000 0 0x400>;
 243                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 244                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 245                          <&pericfg CLK_PERI_UART0>;
 246                 clock-names = "baud", "bus";
 247                 status = "disabled";
 248         };
 249
 250         uart1: serial@11003000 {
 251                 compatible = "mediatek,mt7623-uart",
 252                              "mediatek,mt6577-uart";
 253                 reg = <0 0x11003000 0 0x400>;
 254                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 255                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 256                          <&pericfg CLK_PERI_UART1>;
 257                 clock-names = "baud", "bus";
 258                 status = "disabled";
 259         };
 260
 261         uart2: serial@11004000 {
 262                 compatible = "mediatek,mt7623-uart",
 263                              "mediatek,mt6577-uart";
 264                 reg = <0 0x11004000 0 0x400>;
 265                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 266                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 267                          <&pericfg CLK_PERI_UART2>;
 268                 clock-names = "baud", "bus";
 269                 status = "disabled";
 270         };
 271
 272         uart3: serial@11005000 {
 273                 compatible = "mediatek,mt7623-uart",
 274                              "mediatek,mt6577-uart";
 275                 reg = <0 0x11005000 0 0x400>;
 276                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 277                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 278                          <&pericfg CLK_PERI_UART3>;
 279                 clock-names = "baud", "bus";
 280                 status = "disabled";
 281         };
 282
 283         pwm: pwm@11006000 {
 284                 compatible = "mediatek,mt7623-pwm";
 285                 reg = <0 0x11006000 0 0x1000>;
 286                 #pwm-cells = <2>;
 287                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 288                          <&pericfg CLK_PERI_PWM>,
 289                          <&pericfg CLK_PERI_PWM1>,
 290                          <&pericfg CLK_PERI_PWM2>,
 291                          <&pericfg CLK_PERI_PWM3>,
 292                          <&pericfg CLK_PERI_PWM4>,
 293                          <&pericfg CLK_PERI_PWM5>;
 294                 clock-names = "top", "main", "pwm1", "pwm2",
 295                               "pwm3", "pwm4", "pwm5";
 296                 status = "disabled";
 297         };
 298
 299         i2c0: i2c@11007000 {
 300                 compatible = "mediatek,mt7623-i2c",
 301                              "mediatek,mt6577-i2c";
 302                 reg = <0 0x11007000 0 0x70>,
 303                       <0 0x11000200 0 0x80>;
 304                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 305                 clock-div = <16>;
 306                 clocks = <&pericfg CLK_PERI_I2C0>,
 307                          <&pericfg CLK_PERI_AP_DMA>;
 308                 clock-names = "main", "dma";
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 status = "disabled";
 312         };
 313
 314         i2c1: i2c@11008000 {
 315                 compatible = "mediatek,mt7623-i2c",
 316                              "mediatek,mt6577-i2c";
 317                 reg = <0 0x11008000 0 0x70>,
 318                       <0 0x11000280 0 0x80>;
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 320                 clock-div = <16>;
 321                 clocks = <&pericfg CLK_PERI_I2C1>,
 322                          <&pericfg CLK_PERI_AP_DMA>;
 323                 clock-names = "main", "dma";
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328
 329         i2c2: i2c@11009000 {
 330                 compatible = "mediatek,mt7623-i2c",
 331                              "mediatek,mt6577-i2c";
 332                 reg = <0 0x11009000 0 0x70>,
 333                       <0 0x11000300 0 0x80>;
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 335                 clock-div = <16>;
 336                 clocks = <&pericfg CLK_PERI_I2C2>,
 337                          <&pericfg CLK_PERI_AP_DMA>;
 338                 clock-names = "main", "dma";
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 status = "disabled";
 342         };
 343
 344         spi0: spi@1100a000 {
 345                 compatible = "mediatek,mt7623-spi",
 346                              "mediatek,mt2701-spi";
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 reg = <0 0x1100a000 0 0x100>;
 350                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 351                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 352                          <&topckgen CLK_TOP_SPI0_SEL>,
 353                          <&pericfg CLK_PERI_SPI0>;
 354                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 355                 status = "disabled";
 356         };
 357
 358         thermal: thermal@1100b000 {
 359                 #thermal-sensor-cells = <1>;
 360                 compatible = "mediatek,mt7623-thermal",
 361                              "mediatek,mt2701-thermal";
 362                 reg = <0 0x1100b000 0 0x1000>;
 363                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 364                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 365                 clock-names = "therm", "auxadc";
 366                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 367                 reset-names = "therm";
 368                 mediatek,auxadc = <&auxadc>;
 369                 mediatek,apmixedsys = <&apmixedsys>;
 370                 nvmem-cells = <&thermal_calibration_data>;
 371                 nvmem-cell-names = "calibration-data";
 372         };
 373
 374         spi1: spi@11016000 {
 375                 compatible = "mediatek,mt7623-spi",
 376                              "mediatek,mt2701-spi";
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 reg = <0 0x11016000 0 0x100>;
 380                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 381                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 382                          <&topckgen CLK_TOP_SPI1_SEL>,
 383                          <&pericfg CLK_PERI_SPI1>;
 384                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 385                 status = "disabled";
 386         };
 387
 388         spi2: spi@11017000 {
 389                 compatible = "mediatek,mt7623-spi",
 390                              "mediatek,mt2701-spi";
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 reg = <0 0x11017000 0 0x1000>;
 394                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 395                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 396                          <&topckgen CLK_TOP_SPI2_SEL>,
 397                          <&pericfg CLK_PERI_SPI2>;
 398                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 399                 status = "disabled";
 400         };
 401
 402         nandc: nfi@1100d000 {
 403                 compatible = "mediatek,mt7623-nfc",
 404                              "mediatek,mt2701-nfc";
 405                 reg = <0 0x1100d000 0 0x1000>;
 406                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 407                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 408                 clocks = <&pericfg CLK_PERI_NFI>,
 409                          <&pericfg CLK_PERI_NFI_PAD>;
 410                 clock-names = "nfi_clk", "pad_clk";
 411                 status = "disabled";
 412                 ecc-engine = <&bch>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415         };
 416
 417         bch: ecc@1100e000 {
 418                 compatible = "mediatek,mt7623-ecc",
 419                              "mediatek,mt2701-ecc";
 420                 reg = <0 0x1100e000 0 0x1000>;
 421                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 422                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 423                 clock-names = "nfiecc_clk";
 424                 status = "disabled";
 425         };
 426
 427         afe: audio-controller@11220000 {
 428                 compatible = "mediatek,mt7623-audio",
 429                              "mediatek,mt2701-audio";
 430                 reg = <0 0x11220000 0 0x2000>,
 431                       <0 0x112a0000 0 0x20000>;
 432                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 433                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 434
 435                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 436                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 437                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 438                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 439                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 440                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 441                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 442                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 443                          <&topckgen CLK_TOP_APLL_SEL>,
 444                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 445                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 446                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 447                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 448                          <&topckgen CLK_TOP_AUDPLL>,
 449                          <&topckgen CLK_TOP_AUDPLL_D4>,
 450                          <&topckgen CLK_TOP_AUDPLL_D8>,
 451                          <&topckgen CLK_TOP_AUDPLL_D16>,
 452                          <&topckgen CLK_TOP_AUDPLL_D24>,
 453                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 454                          <&clk26m>,
 455                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 456                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 457                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 458                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 459                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 460                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 461                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 462                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 463                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 464                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 465                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 466                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 467                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 468                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 469                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 470                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 471                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 472                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 473                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 474                          <&topckgen CLK_TOP_ASM_M_SEL>,
 475                          <&topckgen CLK_TOP_ASM_H_SEL>,
 476                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 477                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 478                          <&topckgen CLK_TOP_SYSPLL_D5>;
 479
 480                 clock-names = "infra_sys_audio_clk",
 481                          "top_audio_mux1_sel",
 482                          "top_audio_mux2_sel",
 483                          "top_audio_mux1_div",
 484                          "top_audio_mux2_div",
 485                          "top_audio_48k_timing",
 486                          "top_audio_44k_timing",
 487                          "top_audpll_mux_sel",
 488                          "top_apll_sel",
 489                          "top_aud1_pll_98M",
 490                          "top_aud2_pll_90M",
 491                          "top_hadds2_pll_98M",
 492                          "top_hadds2_pll_294M",
 493                          "top_audpll",
 494                          "top_audpll_d4",
 495                          "top_audpll_d8",
 496                          "top_audpll_d16",
 497                          "top_audpll_d24",
 498                          "top_audintbus_sel",
 499                          "clk_26m",
 500                          "top_syspll1_d4",
 501                          "top_aud_k1_src_sel",
 502                          "top_aud_k2_src_sel",
 503                          "top_aud_k3_src_sel",
 504                          "top_aud_k4_src_sel",
 505                          "top_aud_k5_src_sel",
 506                          "top_aud_k6_src_sel",
 507                          "top_aud_k1_src_div",
 508                          "top_aud_k2_src_div",
 509                          "top_aud_k3_src_div",
 510                          "top_aud_k4_src_div",
 511                          "top_aud_k5_src_div",
 512                          "top_aud_k6_src_div",
 513                          "top_aud_i2s1_mclk",
 514                          "top_aud_i2s2_mclk",
 515                          "top_aud_i2s3_mclk",
 516                          "top_aud_i2s4_mclk",
 517                          "top_aud_i2s5_mclk",
 518                          "top_aud_i2s6_mclk",
 519                          "top_asm_m_sel",
 520                          "top_asm_h_sel",
 521                          "top_univpll2_d4",
 522                          "top_univpll2_d2",
 523                          "top_syspll_d5";
 524         };
 525
 526         mmc0: mmc@11230000 {
 527                 compatible = "mediatek,mt7623-mmc",
 528                              "mediatek,mt8135-mmc";
 529                 reg = <0 0x11230000 0 0x1000>;
 530                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 531                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 532                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 533                 clock-names = "source", "hclk";
 534                 status = "disabled";
 535         };
 536
 537         mmc1: mmc@11240000 {
 538                 compatible = "mediatek,mt7623-mmc",
 539                              "mediatek,mt8135-mmc";
 540                 reg = <0 0x11240000 0 0x1000>;
 541                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 542                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 543                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 544                 clock-names = "source", "hclk";
 545                 status = "disabled";
 546         };
 547
 548         usb1: usb@1a1c0000 {
 549                 compatible = "mediatek,mt7623-xhci",
 550                              "mediatek,mt8173-xhci";
 551                 reg = <0 0x1a1c0000 0 0x1000>,
 552                       <0 0x1a1c4700 0 0x0100>;
 553                 reg-names = "mac", "ippc";
 554                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 555                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 556                          <&topckgen CLK_TOP_ETHIF_SEL>;
 557                 clock-names = "sys_ck", "free_ck";
 558                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 559                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 560                 status = "disabled";
 561         };
 562
 563         u3phy1: usb-phy@1a1c4000 {
 564                 compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
 565                 reg = <0 0x1a1c4000 0 0x0700>;
 566                 clocks = <&clk26m>;
 567                 clock-names = "u3phya_ref";
 568                 #address-cells = <2>;
 569                 #size-cells = <2>;
 570                 ranges;
 571                 status = "disabled";
 572
 573                 u2port0: usb-phy@1a1c4800 {
 574                         reg = <0 0x1a1c4800 0 0x0100>;
 575                         #phy-cells = <1>;
 576                         status = "okay";
 577                 };
 578
 579                 u3port0: usb-phy@1a1c4900 {
 580                         reg = <0 0x1a1c4900 0 0x0700>;
 581                         #phy-cells = <1>;
 582                         status = "okay";
 583                 };
 584         };
 585
 586         usb2: usb@1a240000 {
 587                 compatible = "mediatek,mt7623-xhci",
 588                              "mediatek,mt8173-xhci";
 589                 reg = <0 0x1a240000 0 0x1000>,
 590                       <0 0x1a244700 0 0x0100>;
 591                 reg-names = "mac", "ippc";
 592                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 593                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 594                          <&topckgen CLK_TOP_ETHIF_SEL>;
 595                 clock-names = "sys_ck", "free_ck";
 596                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 597                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 598                 status = "disabled";
 599         };
 600
 601         u3phy2: usb-phy@1a244000 {
 602                 compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
 603                 reg = <0 0x1a244000 0 0x0700>;
 604                 clocks = <&clk26m>;
 605                 clock-names = "u3phya_ref";
 606                 #address-cells = <2>;
 607                 #size-cells = <2>;
 608                 ranges;
 609                 status = "disabled";
 610
 611                 u2port1: usb-phy@1a244800 {
 612                         reg = <0 0x1a244800 0 0x0100>;
 613                         #phy-cells = <1>;
 614                         status = "okay";
 615                 };
 616
 617                 u3port1: usb-phy@1a244900 {
 618                         reg = <0 0x1a244900 0 0x0700>;
 619                         #phy-cells = <1>;
 620                         status = "okay";
 621                 };
 622         };
 623
 624         hifsys: syscon@1a000000 {
 625                 compatible = "mediatek,mt7623-hifsys",
 626                              "mediatek,mt2701-hifsys",
 627                              "syscon";
 628                 reg = <0 0x1a000000 0 0x1000>;
 629                 #clock-cells = <1>;
 630                 #reset-cells = <1>;
 631         };
 632
 633         ethsys: syscon@1b000000 {
 634                 compatible = "mediatek,mt7623-ethsys",
 635                              "mediatek,mt2701-ethsys",
 636                              "syscon";
 637                 reg = <0 0x1b000000 0 0x1000>;
 638                 #clock-cells = <1>;
 639         };
 640
 641         eth: ethernet@1b100000 {
 642                 compatible = "mediatek,mt2701-eth", "syscon";
 643                 reg = <0 0x1b100000 0 0x20000>;
 644                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 645                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 646                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 647                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 648                          <&ethsys CLK_ETHSYS_ESW>,
 649                          <&ethsys CLK_ETHSYS_GP1>,
 650                          <&ethsys CLK_ETHSYS_GP2>,
 651                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 652                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 653                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 654                 mediatek,ethsys = <&ethsys>;
 655                 mediatek,pctl = <&syscfg_pctl_a>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 status = "disabled";
 659         };
 660
 661         crypto: crypto@1b240000 {
 662                 compatible = "mediatek,mt7623-crypto";
 663                 reg = <0 0x1b240000 0 0x20000>;
 664                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 665                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 666                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 667                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 668                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 669                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 670                          <&ethsys CLK_ETHSYS_CRYPTO>;
 671                 clock-names = "ethif","cryp";
 672                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 673                 status = "disabled";
 674         };
 675 };