arch/arm/boot/dts/mt7623.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2018 MediaTek Inc.
   4  * Author: John Crispin <john@phrozen.org>
   5  *         Sean Wang <sean.wang@mediatek.com>
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt2701-clk.h>
  12 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  13 #include <dt-bindings/power/mt2701-power.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16 #include <dt-bindings/memory/mt2701-larb-port.h>
  17 #include <dt-bindings/reset/mt2701-resets.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19
  20 / {
  21         compatible = "mediatek,mt7623";
  22         interrupt-parent = <&sysirq>;
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         cpu_opp_table: opp-table {
  27                 compatible = "operating-points-v2";
  28                 opp-shared;
  29
  30                 opp-98000000 {
  31                         opp-hz = /bits/ 64 <98000000>;
  32                         opp-microvolt = <1050000>;
  33                 };
  34
  35                 opp-198000000 {
  36                         opp-hz = /bits/ 64 <198000000>;
  37                         opp-microvolt = <1050000>;
  38                 };
  39
  40                 opp-398000000 {
  41                         opp-hz = /bits/ 64 <398000000>;
  42                         opp-microvolt = <1050000>;
  43                 };
  44
  45                 opp-598000000 {
  46                         opp-hz = /bits/ 64 <598000000>;
  47                         opp-microvolt = <1050000>;
  48                 };
  49
  50                 opp-747500000 {
  51                         opp-hz = /bits/ 64 <747500000>;
  52                         opp-microvolt = <1050000>;
  53                 };
  54
  55                 opp-1040000000 {
  56                         opp-hz = /bits/ 64 <1040000000>;
  57                         opp-microvolt = <1150000>;
  58                 };
  59
  60                 opp-1196000000 {
  61                         opp-hz = /bits/ 64 <1196000000>;
  62                         opp-microvolt = <1200000>;
  63                 };
  64
  65                 opp-1300000000 {
  66                         opp-hz = /bits/ 64 <1300000000>;
  67                         opp-microvolt = <1300000>;
  68                 };
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 enable-method = "mediatek,mt6589-smp";
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0x0>;
  80                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  81                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  82                         clock-names = "cpu", "intermediate";
  83                         operating-points-v2 = <&cpu_opp_table>;
  84                         #cooling-cells = <2>;
  85                         clock-frequency = <1300000000>;
  86                 };
  87
  88                 cpu1: cpu@1 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0x1>;
  92                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  93                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  94                         clock-names = "cpu", "intermediate";
  95                         operating-points-v2 = <&cpu_opp_table>;
  96                         #cooling-cells = <2>;
  97                         clock-frequency = <1300000000>;
  98                 };
  99
 100                 cpu2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x2>;
 104                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 105                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 106                         clock-names = "cpu", "intermediate";
 107                         operating-points-v2 = <&cpu_opp_table>;
 108                         #cooling-cells = <2>;
 109                         clock-frequency = <1300000000>;
 110                 };
 111
 112                 cpu3: cpu@3 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a7";
 115                         reg = <0x3>;
 116                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 117                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 118                         clock-names = "cpu", "intermediate";
 119                         operating-points-v2 = <&cpu_opp_table>;
 120                         #cooling-cells = <2>;
 121                         clock-frequency = <1300000000>;
 122                 };
 123         };
 124
 125         pmu {
 126                 compatible = "arm,cortex-a7-pmu";
 127                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
 128                              <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
 129                              <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
 130                              <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
 131                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 132         };
 133
 134         system_clk: dummy13m {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <13000000>;
 137                 #clock-cells = <0>;
 138         };
 139
 140         rtc32k: oscillator-1 {
 141                 compatible = "fixed-clock";
 142                 #clock-cells = <0>;
 143                 clock-frequency = <32000>;
 144                 clock-output-names = "rtc32k";
 145         };
 146
 147         clk26m: oscillator-0 {
 148                 compatible = "fixed-clock";
 149                 #clock-cells = <0>;
 150                 clock-frequency = <26000000>;
 151                 clock-output-names = "clk26m";
 152         };
 153
 154         thermal-zones {
 155                         cpu_thermal: cpu-thermal {
 156                                 polling-delay-passive = <1000>;
 157                                 polling-delay = <1000>;
 158
 159                                 thermal-sensors = <&thermal 0>;
 160
 161                                 trips {
 162                                         cpu_passive: cpu-passive {
 163                                                 temperature = <47000>;
 164                                                 hysteresis = <2000>;
 165                                                 type = "passive";
 166                                         };
 167
 168                                         cpu_active: cpu-active {
 169                                                 temperature = <67000>;
 170                                                 hysteresis = <2000>;
 171                                                 type = "active";
 172                                         };
 173
 174                                         cpu_hot: cpu-hot {
 175                                                 temperature = <87000>;
 176                                                 hysteresis = <2000>;
 177                                                 type = "hot";
 178                                         };
 179
 180                                         cpu-crit {
 181                                                 temperature = <107000>;
 182                                                 hysteresis = <2000>;
 183                                                 type = "critical";
 184                                         };
 185                                 };
 186
 187                         cooling-maps {
 188                                 map0 {
 189                                         trip = <&cpu_passive>;
 190                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 191                                 };
 192
 193                                 map1 {
 194                                         trip = <&cpu_active>;
 195                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 196                                 };
 197
 198                                 map2 {
 199                                         trip = <&cpu_hot>;
 200                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 201                                 };
 202                         };
 203                 };
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv7-timer";
 208                 interrupt-parent = <&gic>;
 209                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 213                 clock-frequency = <13000000>;
 214                 arm,cpu-registers-not-fw-configured;
 215         };
 216
 217         topckgen: syscon@10000000 {
 218                 compatible = "mediatek,mt7623-topckgen",
 219                              "mediatek,mt2701-topckgen",
 220                              "syscon";
 221                 reg = <0 0x10000000 0 0x1000>;
 222                 #clock-cells = <1>;
 223         };
 224
 225         infracfg: syscon@10001000 {
 226                 compatible = "mediatek,mt7623-infracfg",
 227                              "mediatek,mt2701-infracfg",
 228                              "syscon";
 229                 reg = <0 0x10001000 0 0x1000>;
 230                 #clock-cells = <1>;
 231                 #reset-cells = <1>;
 232         };
 233
 234         pericfg: syscon@10003000 {
 235                 compatible =  "mediatek,mt7623-pericfg",
 236                               "mediatek,mt2701-pericfg",
 237                               "syscon";
 238                 reg = <0 0x10003000 0 0x1000>;
 239                 #clock-cells = <1>;
 240                 #reset-cells = <1>;
 241         };
 242
 243         pio: pinctrl@10005000 {
 244                 compatible = "mediatek,mt7623-pinctrl";
 245                 reg = <0 0x1000b000 0 0x1000>;
 246                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 247                 pins-are-numbered;
 248                 gpio-controller;
 249                 #gpio-cells = <2>;
 250                 interrupt-controller;
 251                 interrupt-parent = <&gic>;
 252                 #interrupt-cells = <2>;
 253                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 255         };
 256
 257         syscfg_pctl_a: syscfg@10005000 {
 258                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 259                 reg = <0 0x10005000 0 0x1000>;
 260         };
 261
 262         scpsys: scpsys@10006000 {
 263                 compatible = "mediatek,mt7623-scpsys",
 264                              "mediatek,mt2701-scpsys",
 265                              "syscon";
 266                 #power-domain-cells = <1>;
 267                 reg = <0 0x10006000 0 0x1000>;
 268                 infracfg = <&infracfg>;
 269                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 270                          <&topckgen CLK_TOP_MFG_SEL>,
 271                          <&topckgen CLK_TOP_ETHIF_SEL>;
 272                 clock-names = "mm", "mfg", "ethif";
 273         };
 274
 275         watchdog: watchdog@10007000 {
 276                 compatible = "mediatek,mt7623-wdt",
 277                              "mediatek,mt6589-wdt";
 278                 reg = <0 0x10007000 0 0x100>;
 279         };
 280
 281         timer: timer@10008000 {
 282                 compatible = "mediatek,mt7623-timer",
 283                              "mediatek,mt6577-timer";
 284                 reg = <0 0x10008000 0 0x80>;
 285                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 286                 clocks = <&system_clk>, <&rtc32k>;
 287                 clock-names = "system-clk", "rtc-clk";
 288         };
 289
 290         smi_common: smi@1000c000 {
 291                 compatible = "mediatek,mt7623-smi-common",
 292                              "mediatek,mt2701-smi-common";
 293                 reg = <0 0x1000c000 0 0x1000>;
 294                 clocks = <&infracfg CLK_INFRA_SMI>,
 295                          <&mmsys CLK_MM_SMI_COMMON>,
 296                          <&infracfg CLK_INFRA_SMI>;
 297                 clock-names = "apb", "smi", "async";
 298                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 299         };
 300
 301         pwrap: pwrap@1000d000 {
 302                 compatible = "mediatek,mt7623-pwrap",
 303                              "mediatek,mt2701-pwrap";
 304                 reg = <0 0x1000d000 0 0x1000>;
 305                 reg-names = "pwrap";
 306                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 307                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 308                 reset-names = "pwrap";
 309                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 310                          <&infracfg CLK_INFRA_PMICWRAP>;
 311                 clock-names = "spi", "wrap";
 312         };
 313
 314         cir: cir@10013000 {
 315                 compatible = "mediatek,mt7623-cir";
 316                 reg = <0 0x10013000 0 0x1000>;
 317                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 318                 clocks = <&infracfg CLK_INFRA_IRRX>;
 319                 clock-names = "clk";
 320                 status = "disabled";
 321         };
 322
 323         sysirq: interrupt-controller@10200100 {
 324                 compatible = "mediatek,mt7623-sysirq",
 325                              "mediatek,mt6577-sysirq";
 326                 interrupt-controller;
 327                 #interrupt-cells = <3>;
 328                 interrupt-parent = <&gic>;
 329                 reg = <0 0x10200100 0 0x1c>;
 330         };
 331
 332         iommu: mmsys_iommu@10205000 {
 333                 compatible = "mediatek,mt7623-m4u",
 334                              "mediatek,mt2701-m4u";
 335                 reg = <0 0x10205000 0 0x1000>;
 336                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 337                 clocks = <&infracfg CLK_INFRA_M4U>;
 338                 clock-names = "bclk";
 339                 mediatek,larbs = <&larb0 &larb1 &larb2>;
 340                 #iommu-cells = <1>;
 341         };
 342
 343         efuse: efuse@10206000 {
 344                 compatible = "mediatek,mt7623-efuse",
 345                              "mediatek,mt8173-efuse";
 346                 reg = <0 0x10206000 0 0x1000>;
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 thermal_calibration_data: calib@424 {
 350                         reg = <0x424 0xc>;
 351                 };
 352         };
 353
 354         apmixedsys: syscon@10209000 {
 355                 compatible = "mediatek,mt7623-apmixedsys",
 356                              "mediatek,mt2701-apmixedsys",
 357                              "syscon";
 358                 reg = <0 0x10209000 0 0x1000>;
 359                 #clock-cells = <1>;
 360         };
 361
 362         rng: rng@1020f000 {
 363                 compatible = "mediatek,mt7623-rng";
 364                 reg = <0 0x1020f000 0 0x1000>;
 365                 clocks = <&infracfg CLK_INFRA_TRNG>;
 366                 clock-names = "rng";
 367         };
 368
 369         gic: interrupt-controller@10211000 {
 370                 compatible = "arm,cortex-a7-gic";
 371                 interrupt-controller;
 372                 #interrupt-cells = <3>;
 373                 interrupt-parent = <&gic>;
 374                 reg = <0 0x10211000 0 0x1000>,
 375                       <0 0x10212000 0 0x2000>,
 376                       <0 0x10214000 0 0x2000>,
 377                       <0 0x10216000 0 0x2000>;
 378         };
 379
 380         auxadc: adc@11001000 {
 381                 compatible = "mediatek,mt7623-auxadc",
 382                              "mediatek,mt2701-auxadc";
 383                 reg = <0 0x11001000 0 0x1000>;
 384                 clocks = <&pericfg CLK_PERI_AUXADC>;
 385                 clock-names = "main";
 386                 #io-channel-cells = <1>;
 387         };
 388
 389         uart0: serial@11002000 {
 390                 compatible = "mediatek,mt7623-uart",
 391                              "mediatek,mt6577-uart";
 392                 reg = <0 0x11002000 0 0x400>;
 393                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 394                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 395                          <&pericfg CLK_PERI_UART0>;
 396                 clock-names = "baud", "bus";
 397                 status = "disabled";
 398         };
 399
 400         uart1: serial@11003000 {
 401                 compatible = "mediatek,mt7623-uart",
 402                              "mediatek,mt6577-uart";
 403                 reg = <0 0x11003000 0 0x400>;
 404                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 405                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 406                          <&pericfg CLK_PERI_UART1>;
 407                 clock-names = "baud", "bus";
 408                 status = "disabled";
 409         };
 410
 411         uart2: serial@11004000 {
 412                 compatible = "mediatek,mt7623-uart",
 413                              "mediatek,mt6577-uart";
 414                 reg = <0 0x11004000 0 0x400>;
 415                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 416                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 417                          <&pericfg CLK_PERI_UART2>;
 418                 clock-names = "baud", "bus";
 419                 status = "disabled";
 420         };
 421
 422         uart3: serial@11005000 {
 423                 compatible = "mediatek,mt7623-uart",
 424                              "mediatek,mt6577-uart";
 425                 reg = <0 0x11005000 0 0x400>;
 426                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 427                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 428                          <&pericfg CLK_PERI_UART3>;
 429                 clock-names = "baud", "bus";
 430                 status = "disabled";
 431         };
 432
 433         pwm: pwm@11006000 {
 434                 compatible = "mediatek,mt7623-pwm";
 435                 reg = <0 0x11006000 0 0x1000>;
 436                 #pwm-cells = <2>;
 437                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 438                          <&pericfg CLK_PERI_PWM>,
 439                          <&pericfg CLK_PERI_PWM1>,
 440                          <&pericfg CLK_PERI_PWM2>,
 441                          <&pericfg CLK_PERI_PWM3>,
 442                          <&pericfg CLK_PERI_PWM4>,
 443                          <&pericfg CLK_PERI_PWM5>;
 444                 clock-names = "top", "main", "pwm1", "pwm2",
 445                               "pwm3", "pwm4", "pwm5";
 446                 status = "disabled";
 447         };
 448
 449         i2c0: i2c@11007000 {
 450                 compatible = "mediatek,mt7623-i2c",
 451                              "mediatek,mt6577-i2c";
 452                 reg = <0 0x11007000 0 0x70>,
 453                       <0 0x11000200 0 0x80>;
 454                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 455                 clock-div = <16>;
 456                 clocks = <&pericfg CLK_PERI_I2C0>,
 457                          <&pericfg CLK_PERI_AP_DMA>;
 458                 clock-names = "main", "dma";
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 status = "disabled";
 462         };
 463
 464         i2c1: i2c@11008000 {
 465                 compatible = "mediatek,mt7623-i2c",
 466                              "mediatek,mt6577-i2c";
 467                 reg = <0 0x11008000 0 0x70>,
 468                       <0 0x11000280 0 0x80>;
 469                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 470                 clock-div = <16>;
 471                 clocks = <&pericfg CLK_PERI_I2C1>,
 472                          <&pericfg CLK_PERI_AP_DMA>;
 473                 clock-names = "main", "dma";
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 status = "disabled";
 477         };
 478
 479         i2c2: i2c@11009000 {
 480                 compatible = "mediatek,mt7623-i2c",
 481                              "mediatek,mt6577-i2c";
 482                 reg = <0 0x11009000 0 0x70>,
 483                       <0 0x11000300 0 0x80>;
 484                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 485                 clock-div = <16>;
 486                 clocks = <&pericfg CLK_PERI_I2C2>,
 487                          <&pericfg CLK_PERI_AP_DMA>;
 488                 clock-names = "main", "dma";
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 status = "disabled";
 492         };
 493
 494         spi0: spi@1100a000 {
 495                 compatible = "mediatek,mt7623-spi",
 496                              "mediatek,mt2701-spi";
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 reg = <0 0x1100a000 0 0x100>;
 500                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 501                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 502                          <&topckgen CLK_TOP_SPI0_SEL>,
 503                          <&pericfg CLK_PERI_SPI0>;
 504                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 505                 status = "disabled";
 506         };
 507
 508         thermal: thermal@1100b000 {
 509                 #thermal-sensor-cells = <1>;
 510                 compatible = "mediatek,mt7623-thermal",
 511                              "mediatek,mt2701-thermal";
 512                 reg = <0 0x1100b000 0 0x1000>;
 513                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 514                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 515                 clock-names = "therm", "auxadc";
 516                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 517                 reset-names = "therm";
 518                 mediatek,auxadc = <&auxadc>;
 519                 mediatek,apmixedsys = <&apmixedsys>;
 520                 nvmem-cells = <&thermal_calibration_data>;
 521                 nvmem-cell-names = "calibration-data";
 522         };
 523
 524         btif: serial@1100c000 {
 525                 compatible = "mediatek,mt7623-btif",
 526                              "mediatek,mtk-btif";
 527                 reg = <0 0x1100c000 0 0x1000>;
 528                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
 529                 clocks = <&pericfg CLK_PERI_BTIF>;
 530                 clock-names = "main";
 531                 reg-shift = <2>;
 532                 reg-io-width = <4>;
 533                 status = "disabled";
 534         };
 535
 536         nandc: nfi@1100d000 {
 537                 compatible = "mediatek,mt7623-nfc",
 538                              "mediatek,mt2701-nfc";
 539                 reg = <0 0x1100d000 0 0x1000>;
 540                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 541                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 542                 clocks = <&pericfg CLK_PERI_NFI>,
 543                          <&pericfg CLK_PERI_NFI_PAD>;
 544                 clock-names = "nfi_clk", "pad_clk";
 545                 status = "disabled";
 546                 ecc-engine = <&bch>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549         };
 550
 551         bch: ecc@1100e000 {
 552                 compatible = "mediatek,mt7623-ecc",
 553                              "mediatek,mt2701-ecc";
 554                 reg = <0 0x1100e000 0 0x1000>;
 555                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 556                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 557                 clock-names = "nfiecc_clk";
 558                 status = "disabled";
 559         };
 560
 561         nor_flash: spi@11014000 {
 562                 compatible = "mediatek,mt7623-nor",
 563                              "mediatek,mt8173-nor";
 564                 reg = <0 0x11014000 0 0x1000>;
 565                 clocks = <&pericfg CLK_PERI_FLASH>,
 566                          <&topckgen CLK_TOP_FLASH_SEL>;
 567                 clock-names = "spi", "sf";
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         spi1: spi@11016000 {
 574                 compatible = "mediatek,mt7623-spi",
 575                              "mediatek,mt2701-spi";
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 reg = <0 0x11016000 0 0x100>;
 579                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 580                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 581                          <&topckgen CLK_TOP_SPI1_SEL>,
 582                          <&pericfg CLK_PERI_SPI1>;
 583                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 584                 status = "disabled";
 585         };
 586
 587         spi2: spi@11017000 {
 588                 compatible = "mediatek,mt7623-spi",
 589                              "mediatek,mt2701-spi";
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 reg = <0 0x11017000 0 0x1000>;
 593                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 594                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 595                          <&topckgen CLK_TOP_SPI2_SEL>,
 596                          <&pericfg CLK_PERI_SPI2>;
 597                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 598                 status = "disabled";
 599         };
 600
 601         audsys: clock-controller@11220000 {
 602                 compatible = "mediatek,mt7623-audsys",
 603                              "mediatek,mt2701-audsys",
 604                              "syscon";
 605                 reg = <0 0x11220000 0 0x2000>;
 606                 #clock-cells = <1>;
 607
 608                 afe: audio-controller {
 609                         compatible = "mediatek,mt7623-audio",
 610                                      "mediatek,mt2701-audio";
 611                         interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 612                                       <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 613                         interrupt-names = "afe", "asys";
 614                         power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 615
 616                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 617                                  <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 618                                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 619                                  <&topckgen CLK_TOP_AUD_48K_TIMING>,
 620                                  <&topckgen CLK_TOP_AUD_44K_TIMING>,
 621                                  <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 622                                  <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 623                                  <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 624                                  <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 625                                  <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 626                                  <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 627                                  <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 628                                  <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 629                                  <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 630                                  <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 631                                  <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 632                                  <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 633                                  <&audsys CLK_AUD_I2SO1>,
 634                                  <&audsys CLK_AUD_I2SO2>,
 635                                  <&audsys CLK_AUD_I2SO3>,
 636                                  <&audsys CLK_AUD_I2SO4>,
 637                                  <&audsys CLK_AUD_I2SIN1>,
 638                                  <&audsys CLK_AUD_I2SIN2>,
 639                                  <&audsys CLK_AUD_I2SIN3>,
 640                                  <&audsys CLK_AUD_I2SIN4>,
 641                                  <&audsys CLK_AUD_ASRCO1>,
 642                                  <&audsys CLK_AUD_ASRCO2>,
 643                                  <&audsys CLK_AUD_ASRCO3>,
 644                                  <&audsys CLK_AUD_ASRCO4>,
 645                                  <&audsys CLK_AUD_AFE>,
 646                                  <&audsys CLK_AUD_AFE_CONN>,
 647                                  <&audsys CLK_AUD_A1SYS>,
 648                                  <&audsys CLK_AUD_A2SYS>,
 649                                  <&audsys CLK_AUD_AFE_MRGIF>;
 650
 651                         clock-names = "infra_sys_audio_clk",
 652                                       "top_audio_mux1_sel",
 653                                       "top_audio_mux2_sel",
 654                                       "top_audio_a1sys_hp",
 655                                       "top_audio_a2sys_hp",
 656                                       "i2s0_src_sel",
 657                                       "i2s1_src_sel",
 658                                       "i2s2_src_sel",
 659                                       "i2s3_src_sel",
 660                                       "i2s0_src_div",
 661                                       "i2s1_src_div",
 662                                       "i2s2_src_div",
 663                                       "i2s3_src_div",
 664                                       "i2s0_mclk_en",
 665                                       "i2s1_mclk_en",
 666                                       "i2s2_mclk_en",
 667                                       "i2s3_mclk_en",
 668                                       "i2so0_hop_ck",
 669                                       "i2so1_hop_ck",
 670                                       "i2so2_hop_ck",
 671                                       "i2so3_hop_ck",
 672                                       "i2si0_hop_ck",
 673                                       "i2si1_hop_ck",
 674                                       "i2si2_hop_ck",
 675                                       "i2si3_hop_ck",
 676                                       "asrc0_out_ck",
 677                                       "asrc1_out_ck",
 678                                       "asrc2_out_ck",
 679                                       "asrc3_out_ck",
 680                                       "audio_afe_pd",
 681                                       "audio_afe_conn_pd",
 682                                       "audio_a1sys_pd",
 683                                       "audio_a2sys_pd",
 684                                       "audio_mrgif_pd";
 685
 686                         assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 687                                           <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 688                                           <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 689                                           <&topckgen CLK_TOP_AUD_MUX2_DIV>;
 690                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
 691                                                  <&topckgen CLK_TOP_AUD2PLL_90M>;
 692                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 693                 };
 694         };
 695
 696         mmc0: mmc@11230000 {
 697                 compatible = "mediatek,mt7623-mmc",
 698                              "mediatek,mt2701-mmc";
 699                 reg = <0 0x11230000 0 0x1000>;
 700                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 701                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 702                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 703                 clock-names = "source", "hclk";
 704                 status = "disabled";
 705         };
 706
 707         mmc1: mmc@11240000 {
 708                 compatible = "mediatek,mt7623-mmc",
 709                              "mediatek,mt2701-mmc";
 710                 reg = <0 0x11240000 0 0x1000>;
 711                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 712                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 713                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 714                 clock-names = "source", "hclk";
 715                 status = "disabled";
 716         };
 717
 718         g3dsys: syscon@13000000 {
 719                 compatible = "mediatek,mt7623-g3dsys",
 720                              "mediatek,mt2701-g3dsys",
 721                              "syscon";
 722                 reg = <0 0x13000000 0 0x200>;
 723                 #clock-cells = <1>;
 724                 #reset-cells = <1>;
 725         };
 726
 727         mmsys: syscon@14000000 {
 728                 compatible = "mediatek,mt7623-mmsys",
 729                              "mediatek,mt2701-mmsys",
 730                              "syscon";
 731                 reg = <0 0x14000000 0 0x1000>;
 732                 #clock-cells = <1>;
 733         };
 734
 735         larb0: larb@14010000 {
 736                 compatible = "mediatek,mt7623-smi-larb",
 737                              "mediatek,mt2701-smi-larb";
 738                 reg = <0 0x14010000 0 0x1000>;
 739                 mediatek,smi = <&smi_common>;
 740                 mediatek,larb-id = <0>;
 741                 clocks = <&mmsys CLK_MM_SMI_LARB0>,
 742                          <&mmsys CLK_MM_SMI_LARB0>;
 743                 clock-names = "apb", "smi";
 744                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 745         };
 746
 747         imgsys: syscon@15000000 {
 748                 compatible = "mediatek,mt7623-imgsys",
 749                              "mediatek,mt2701-imgsys",
 750                              "syscon";
 751                 reg = <0 0x15000000 0 0x1000>;
 752                 #clock-cells = <1>;
 753         };
 754
 755         larb2: larb@15001000 {
 756                 compatible = "mediatek,mt7623-smi-larb",
 757                              "mediatek,mt2701-smi-larb";
 758                 reg = <0 0x15001000 0 0x1000>;
 759                 mediatek,smi = <&smi_common>;
 760                 mediatek,larb-id = <2>;
 761                 clocks = <&imgsys CLK_IMG_SMI_COMM>,
 762                          <&imgsys CLK_IMG_SMI_COMM>;
 763                 clock-names = "apb", "smi";
 764                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 765         };
 766
 767         jpegdec: jpegdec@15004000 {
 768                 compatible = "mediatek,mt7623-jpgdec",
 769                              "mediatek,mt2701-jpgdec";
 770                 reg = <0 0x15004000 0 0x1000>;
 771                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
 772                 clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
 773                           <&imgsys CLK_IMG_JPGDEC>;
 774                 clock-names = "jpgdec-smi",
 775                               "jpgdec";
 776                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 777                 mediatek,larb = <&larb2>;
 778                 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
 779                          <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
 780         };
 781
 782         vdecsys: syscon@16000000 {
 783                 compatible = "mediatek,mt7623-vdecsys",
 784                              "mediatek,mt2701-vdecsys",
 785                              "syscon";
 786                 reg = <0 0x16000000 0 0x1000>;
 787                 #clock-cells = <1>;
 788         };
 789
 790         larb1: larb@16010000 {
 791                 compatible = "mediatek,mt7623-smi-larb",
 792                              "mediatek,mt2701-smi-larb";
 793                 reg = <0 0x16010000 0 0x1000>;
 794                 mediatek,smi = <&smi_common>;
 795                 mediatek,larb-id = <1>;
 796                 clocks = <&vdecsys CLK_VDEC_CKGEN>,
 797                          <&vdecsys CLK_VDEC_LARB>;
 798                 clock-names = "apb", "smi";
 799                 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
 800         };
 801
 802         hifsys: syscon@1a000000 {
 803                 compatible = "mediatek,mt7623-hifsys",
 804                              "mediatek,mt2701-hifsys",
 805                              "syscon";
 806                 reg = <0 0x1a000000 0 0x1000>;
 807                 #clock-cells = <1>;
 808                 #reset-cells = <1>;
 809         };
 810
 811         pcie: pcie@1a140000 {
 812                 compatible = "mediatek,mt7623-pcie";
 813                 device_type = "pci";
 814                 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
 815                       <0 0x1a142000 0 0x1000>, /* Port0 registers */
 816                       <0 0x1a143000 0 0x1000>, /* Port1 registers */
 817                       <0 0x1a144000 0 0x1000>; /* Port2 registers */
 818                 reg-names = "subsys", "port0", "port1", "port2";
 819                 #address-cells = <3>;
 820                 #size-cells = <2>;
 821                 #interrupt-cells = <1>;
 822                 interrupt-map-mask = <0xf800 0 0 0>;
 823                 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 824                                 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 825                                 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 826                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 827                          <&hifsys CLK_HIFSYS_PCIE0>,
 828                          <&hifsys CLK_HIFSYS_PCIE1>,
 829                          <&hifsys CLK_HIFSYS_PCIE2>;
 830                 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
 831                 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 832                          <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 833                          <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 834                 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
 835                 phys = <&pcie0_port PHY_TYPE_PCIE>,
 836                        <&pcie1_port PHY_TYPE_PCIE>,
 837                        <&u3port1 PHY_TYPE_PCIE>;
 838                 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
 839                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 840                 bus-range = <0x00 0xff>;
 841                 status = "disabled";
 842                 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
 843                           0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
 844
 845                 pcie@0,0 {
 846                         reg = <0x0000 0 0 0 0>;
 847                         #address-cells = <3>;
 848                         #size-cells = <2>;
 849                         #interrupt-cells = <1>;
 850                         interrupt-map-mask = <0 0 0 0>;
 851                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 852                         ranges;
 853                         num-lanes = <1>;
 854                         status = "disabled";
 855                 };
 856
 857                 pcie@1,0 {
 858                         reg = <0x0800 0 0 0 0>;
 859                         #address-cells = <3>;
 860                         #size-cells = <2>;
 861                         #interrupt-cells = <1>;
 862                         interrupt-map-mask = <0 0 0 0>;
 863                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 864                         ranges;
 865                         num-lanes = <1>;
 866                         status = "disabled";
 867                 };
 868
 869                 pcie@2,0 {
 870                         reg = <0x1000 0 0 0 0>;
 871                         #address-cells = <3>;
 872                         #size-cells = <2>;
 873                         #interrupt-cells = <1>;
 874                         interrupt-map-mask = <0 0 0 0>;
 875                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 876                         ranges;
 877                         num-lanes = <1>;
 878                         status = "disabled";
 879                 };
 880         };
 881
 882         pcie0_phy: pcie-phy@1a149000 {
 883                 compatible = "mediatek,generic-tphy-v1";
 884                 reg = <0 0x1a149000 0 0x0700>;
 885                 #address-cells = <2>;
 886                 #size-cells = <2>;
 887                 ranges;
 888                 status = "disabled";
 889
 890                 pcie0_port: pcie-phy@1a149900 {
 891                         reg = <0 0x1a149900 0 0x0700>;
 892                         clocks = <&clk26m>;
 893                         clock-names = "ref";
 894                         #phy-cells = <1>;
 895                         status = "okay";
 896                 };
 897         };
 898
 899         pcie1_phy: pcie-phy@1a14a000 {
 900                 compatible = "mediatek,generic-tphy-v1";
 901                 reg = <0 0x1a14a000 0 0x0700>;
 902                 #address-cells = <2>;
 903                 #size-cells = <2>;
 904                 ranges;
 905                 status = "disabled";
 906
 907                 pcie1_port: pcie-phy@1a14a900 {
 908                         reg = <0 0x1a14a900 0 0x0700>;
 909                         clocks = <&clk26m>;
 910                         clock-names = "ref";
 911                         #phy-cells = <1>;
 912                         status = "okay";
 913                 };
 914         };
 915
 916         usb1: usb@1a1c0000 {
 917                 compatible = "mediatek,mt7623-xhci",
 918                              "mediatek,mt8173-xhci";
 919                 reg = <0 0x1a1c0000 0 0x1000>,
 920                       <0 0x1a1c4700 0 0x0100>;
 921                 reg-names = "mac", "ippc";
 922                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 923                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 924                          <&topckgen CLK_TOP_ETHIF_SEL>;
 925                 clock-names = "sys_ck", "ref_ck";
 926                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 927                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 928                 status = "disabled";
 929         };
 930
 931         u3phy1: usb-phy@1a1c4000 {
 932                 compatible = "mediatek,mt7623-u3phy",
 933                              "mediatek,mt2701-u3phy";
 934                 reg = <0 0x1a1c4000 0 0x0700>;
 935                 #address-cells = <2>;
 936                 #size-cells = <2>;
 937                 ranges;
 938                 status = "disabled";
 939
 940                 u2port0: usb-phy@1a1c4800 {
 941                         reg = <0 0x1a1c4800 0 0x0100>;
 942                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 943                         clock-names = "ref";
 944                         #phy-cells = <1>;
 945                         status = "okay";
 946                 };
 947
 948                 u3port0: usb-phy@1a1c4900 {
 949                         reg = <0 0x1a1c4900 0 0x0700>;
 950                         clocks = <&clk26m>;
 951                         clock-names = "ref";
 952                         #phy-cells = <1>;
 953                         status = "okay";
 954                 };
 955         };
 956
 957         usb2: usb@1a240000 {
 958                 compatible = "mediatek,mt7623-xhci",
 959                              "mediatek,mt8173-xhci";
 960                 reg = <0 0x1a240000 0 0x1000>,
 961                       <0 0x1a244700 0 0x0100>;
 962                 reg-names = "mac", "ippc";
 963                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 964                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 965                          <&topckgen CLK_TOP_ETHIF_SEL>;
 966                 clock-names = "sys_ck", "ref_ck";
 967                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 968                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 969                 status = "disabled";
 970         };
 971
 972         u3phy2: usb-phy@1a244000 {
 973                 compatible = "mediatek,mt7623-u3phy",
 974                              "mediatek,mt2701-u3phy";
 975                 reg = <0 0x1a244000 0 0x0700>;
 976                 #address-cells = <2>;
 977                 #size-cells = <2>;
 978                 ranges;
 979                 status = "disabled";
 980
 981                 u2port1: usb-phy@1a244800 {
 982                         reg = <0 0x1a244800 0 0x0100>;
 983                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 984                         clock-names = "ref";
 985                         #phy-cells = <1>;
 986                         status = "okay";
 987                 };
 988
 989                 u3port1: usb-phy@1a244900 {
 990                         reg = <0 0x1a244900 0 0x0700>;
 991                         clocks = <&clk26m>;
 992                         clock-names = "ref";
 993                         #phy-cells = <1>;
 994                         status = "okay";
 995                 };
 996         };
 997
 998         ethsys: syscon@1b000000 {
 999                 compatible = "mediatek,mt7623-ethsys",
1000                              "mediatek,mt2701-ethsys",
1001                              "syscon";
1002                 reg = <0 0x1b000000 0 0x1000>;
1003                 #clock-cells = <1>;
1004                 #reset-cells = <1>;
1005         };
1006
1007         hsdma: dma-controller@1b007000 {
1008                 compatible = "mediatek,mt7623-hsdma";
1009                 reg = <0 0x1b007000 0 0x1000>;
1010                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
1011                 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
1012                 clock-names = "hsdma";
1013                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1014                 #dma-cells = <1>;
1015         };
1016
1017         eth: ethernet@1b100000 {
1018                 compatible = "mediatek,mt7623-eth",
1019                              "mediatek,mt2701-eth",
1020                              "syscon";
1021                 reg = <0 0x1b100000 0 0x20000>;
1022                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
1023                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
1024                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1025                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1026                          <&ethsys CLK_ETHSYS_ESW>,
1027                          <&ethsys CLK_ETHSYS_GP1>,
1028                          <&ethsys CLK_ETHSYS_GP2>,
1029                          <&apmixedsys CLK_APMIXED_TRGPLL>;
1030                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
1031                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
1032                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
1033                          <&ethsys MT2701_ETHSYS_PPE_RST>;
1034                 reset-names = "fe", "gmac", "ppe";
1035                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1036                 mediatek,ethsys = <&ethsys>;
1037                 mediatek,pctl = <&syscfg_pctl_a>;
1038                 #address-cells = <1>;
1039                 #size-cells = <0>;
1040                 status = "disabled";
1041         };
1042
1043         crypto: crypto@1b240000 {
1044                 compatible = "mediatek,eip97-crypto";
1045                 reg = <0 0x1b240000 0 0x20000>;
1046                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1047                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1048                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
1049                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
1050                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
1051                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
1052                 clock-names = "cryp";
1053                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1054                 status = "disabled";
1055         };
1056
1057         bdpsys: syscon@1c000000 {
1058                 compatible = "mediatek,mt7623-bdpsys",
1059                              "mediatek,mt2701-bdpsys",
1060                              "syscon";
1061                 reg = <0 0x1c000000 0 0x1000>;
1062                 #clock-cells = <1>;
1063         };
1064 };
1065
1066 &pio {
1067         cir_pins_a:cir-default {
1068                 pins-cir {
1069                         pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1070                         bias-disable;
1071                 };
1072         };
1073
1074         i2c0_pins_a: i2c0-default {
1075                 pins-i2c0 {
1076                         pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1077                                  <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1078                         bias-disable;
1079                 };
1080         };
1081
1082         i2c1_pins_a: i2c1-default {
1083                 pin-i2c1 {
1084                         pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1085                                  <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1086                         bias-disable;
1087                 };
1088         };
1089
1090         i2c1_pins_b: i2c1-alt {
1091                 pin-i2c1 {
1092                         pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1093                                  <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1094                         bias-disable;
1095                 };
1096         };
1097
1098         i2c2_pins_a: i2c2-default {
1099                 pin-i2c2 {
1100                         pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1101                                  <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1102                         bias-disable;
1103                 };
1104         };
1105
1106         i2c2_pins_b: i2c2-alt {
1107                 pin-i2c2 {
1108                         pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1109                                  <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1110                         bias-disable;
1111                 };
1112         };
1113
1114         i2s0_pins_a: i2s0-default {
1115                 pin-i2s0 {
1116                         pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1117                                  <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1118                                  <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1119                                  <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1120                                  <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1121                         drive-strength = <MTK_DRIVE_12mA>;
1122                         bias-pull-down;
1123                 };
1124         };
1125
1126         i2s1_pins_a: i2s1-default {
1127                 pin-i2s1 {
1128                         pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1129                                  <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1130                                  <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1131                                  <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1132                                  <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1133                         drive-strength = <MTK_DRIVE_12mA>;
1134                         bias-pull-down;
1135                 };
1136         };
1137
1138         key_pins_a: keys-alt {
1139                 pins-keys {
1140                         pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1141                                  <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1142                         input-enable;
1143                 };
1144         };
1145
1146         led_pins_a: leds-alt {
1147                 pins-leds {
1148                         pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1149                                  <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1150                                  <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1151                 };
1152         };
1153
1154         mmc0_pins_default: mmc0default {
1155                 pins-cmd-dat {
1156                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1157                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1158                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1159                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1160                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1161                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1162                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1163                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1164                                  <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1165                         input-enable;
1166                         bias-pull-up;
1167                 };
1168
1169                 pins-clk {
1170                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1171                         bias-pull-down;
1172                 };
1173
1174                 pins-rst {
1175                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1176                         bias-pull-up;
1177                 };
1178         };
1179
1180         mmc0_pins_uhs: mmc0 {
1181                 pins-cmd-dat {
1182                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1183                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1184                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1185                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1186                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1187                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1188                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1189                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1190                                  <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1191                         input-enable;
1192                         drive-strength = <MTK_DRIVE_2mA>;
1193                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1194                 };
1195
1196                 pins-clk {
1197                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1198                         drive-strength = <MTK_DRIVE_2mA>;
1199                         bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1200                 };
1201
1202                 pins-rst {
1203                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1204                         bias-pull-up;
1205                 };
1206         };
1207
1208         mmc1_pins_default: mmc1default {
1209                 pins-cmd-dat {
1210                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1211                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1212                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1213                                  <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1214                                  <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1215                         input-enable;
1216                         drive-strength = <MTK_DRIVE_4mA>;
1217                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1218                 };
1219
1220                 pins-clk {
1221                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1222                         bias-pull-down;
1223                         drive-strength = <MTK_DRIVE_4mA>;
1224                 };
1225
1226                 pins-wp {
1227                         pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1228                         input-enable;
1229                         bias-pull-up;
1230                 };
1231
1232                 pins-insert {
1233                         pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1234                         bias-pull-up;
1235                 };
1236         };
1237
1238         mmc1_pins_uhs: mmc1 {
1239                 pins-cmd-dat {
1240                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1241                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1242                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1243                                  <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1244                                  <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1245                         input-enable;
1246                         drive-strength = <MTK_DRIVE_4mA>;
1247                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1248                 };
1249
1250                 pins-clk {
1251                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1252                         drive-strength = <MTK_DRIVE_4mA>;
1253                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1254                 };
1255         };
1256
1257         nand_pins_default: nanddefault {
1258                 pins-ale {
1259                         pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1260                         drive-strength = <MTK_DRIVE_8mA>;
1261                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1262                 };
1263
1264                 pins-dat {
1265                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1266                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1267                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1268                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1269                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1270                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1271                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1272                                  <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1273                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1274                         input-enable;
1275                         drive-strength = <MTK_DRIVE_8mA>;
1276                         bias-pull-up;
1277                 };
1278
1279                 pins-we {
1280                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1281                         drive-strength = <MTK_DRIVE_8mA>;
1282                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1283                 };
1284         };
1285
1286         pcie_default: pcie_pin_default {
1287                 pins_cmd_dat {
1288                         pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1289                                  <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1290                         bias-disable;
1291                 };
1292         };
1293
1294         pwm_pins_a: pwm-default {
1295                 pins-pwm {
1296                         pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1297                                  <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1298                                  <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1299                                  <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1300                                  <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1301                 };
1302         };
1303
1304         spi0_pins_a: spi0-default {
1305                 pins-spi {
1306                         pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1307                                 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1308                                 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1309                                 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1310                         bias-disable;
1311                 };
1312         };
1313
1314         spi1_pins_a: spi1-default {
1315                 pins-spi {
1316                         pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1317                                 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1318                                 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1319                                 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1320                 };
1321         };
1322
1323         spi2_pins_a: spi2-default {
1324                 pins-spi {
1325                         pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1326                                  <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1327                                  <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1328                                  <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1329                 };
1330         };
1331
1332         uart0_pins_a: uart0-default {
1333                 pins-dat {
1334                         pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1335                                  <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1336                 };
1337         };
1338
1339         uart1_pins_a: uart1-default {
1340                 pins-dat {
1341                         pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1342                                  <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1343                 };
1344         };
1345
1346         uart2_pins_a: uart2-default {
1347                 pins-dat {
1348                         pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1349                                  <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1350                 };
1351         };
1352
1353         uart2_pins_b: uart2-alt {
1354                 pins-dat {
1355                         pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1356                                  <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1357                 };
1358         };
1359 };