arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25 #include "skeleton64.dtsi"
  26
  27 / {
  28         compatible = "mediatek,mt7623";
  29         interrupt-parent = <&sysirq>;
  30
  31         cpu_opp_table: opp_table {
  32                 compatible = "operating-points-v2";
  33                 opp-shared;
  34
  35                 opp-98000000 {
  36                         opp-hz = /bits/ 64 <98000000>;
  37                         opp-microvolt = <1050000>;
  38                 };
  39
  40                 opp-198000000 {
  41                         opp-hz = /bits/ 64 <198000000>;
  42                         opp-microvolt = <1050000>;
  43                 };
  44
  45                 opp-398000000 {
  46                         opp-hz = /bits/ 64 <398000000>;
  47                         opp-microvolt = <1050000>;
  48                 };
  49
  50                 opp-598000000 {
  51                         opp-hz = /bits/ 64 <598000000>;
  52                         opp-microvolt = <1050000>;
  53                 };
  54
  55                 opp-747500000 {
  56                         opp-hz = /bits/ 64 <747500000>;
  57                         opp-microvolt = <1050000>;
  58                 };
  59
  60                 opp-1040000000 {
  61                         opp-hz = /bits/ 64 <1040000000>;
  62                         opp-microvolt = <1150000>;
  63                 };
  64
  65                 opp-1196000000 {
  66                         opp-hz = /bits/ 64 <1196000000>;
  67                         opp-microvolt = <1200000>;
  68                 };
  69
  70                 opp-1300000000 {
  71                         opp-hz = /bits/ 64 <1300000000>;
  72                         opp-microvolt = <1300000>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 enable-method = "mediatek,mt6589-smp";
  80
  81                 cpu0: cpu@0 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x0>;
  85                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  86                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         #cooling-cells = <2>;
  90                         cooling-min-level = <0>;
  91                         cooling-max-level = <7>;
  92                         clock-frequency = <1300000000>;
  93                 };
  94
  95                 cpu1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x1>;
  99                         operating-points-v2 = <&cpu_opp_table>;
 100                         clock-frequency = <1300000000>;
 101                 };
 102
 103                 cpu2: cpu@2 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a7";
 106                         reg = <0x2>;
 107                         operating-points-v2 = <&cpu_opp_table>;
 108                         clock-frequency = <1300000000>;
 109                 };
 110
 111                 cpu3: cpu@3 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a7";
 114                         reg = <0x3>;
 115                         operating-points-v2 = <&cpu_opp_table>;
 116                         clock-frequency = <1300000000>;
 117                 };
 118         };
 119
 120         system_clk: dummy13m {
 121                 compatible = "fixed-clock";
 122                 clock-frequency = <13000000>;
 123                 #clock-cells = <0>;
 124         };
 125
 126         rtc32k: oscillator@1 {
 127                 compatible = "fixed-clock";
 128                 #clock-cells = <0>;
 129                 clock-frequency = <32000>;
 130                 clock-output-names = "rtc32k";
 131         };
 132
 133         clk26m: oscillator@0 {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <26000000>;
 137                 clock-output-names = "clk26m";
 138         };
 139
 140         thermal-zones {
 141                         cpu_thermal: cpu_thermal {
 142                                 polling-delay-passive = <1000>;
 143                                 polling-delay = <1000>;
 144
 145                                 thermal-sensors = <&thermal 0>;
 146
 147                                 trips {
 148                                         cpu_passive: cpu_passive {
 149                                                 temperature = <47000>;
 150                                                 hysteresis = <2000>;
 151                                                 type = "passive";
 152                                         };
 153
 154                                         cpu_active: cpu_active {
 155                                                 temperature = <67000>;
 156                                                 hysteresis = <2000>;
 157                                                 type = "active";
 158                                         };
 159
 160                                         cpu_hot: cpu_hot {
 161                                                 temperature = <87000>;
 162                                                 hysteresis = <2000>;
 163                                                 type = "hot";
 164                                         };
 165
 166                                         cpu_crit {
 167                                                 temperature = <107000>;
 168                                                 hysteresis = <2000>;
 169                                                 type = "critical";
 170                                         };
 171                                 };
 172
 173                         cooling-maps {
 174                                 map0 {
 175                                         trip = <&cpu_passive>;
 176                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 177                                 };
 178
 179                                 map1 {
 180                                         trip = <&cpu_active>;
 181                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 182                                 };
 183
 184                                 map2 {
 185                                         trip = <&cpu_hot>;
 186                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 187                                 };
 188                         };
 189                 };
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupt-parent = <&gic>;
 195                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 196                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 197                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 198                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 199                 clock-frequency = <13000000>;
 200                 arm,cpu-registers-not-fw-configured;
 201         };
 202
 203         topckgen: syscon@10000000 {
 204                 compatible = "mediatek,mt7623-topckgen",
 205                              "mediatek,mt2701-topckgen",
 206                              "syscon";
 207                 reg = <0 0x10000000 0 0x1000>;
 208                 #clock-cells = <1>;
 209         };
 210
 211         infracfg: syscon@10001000 {
 212                 compatible = "mediatek,mt7623-infracfg",
 213                              "mediatek,mt2701-infracfg",
 214                              "syscon";
 215                 reg = <0 0x10001000 0 0x1000>;
 216                 #clock-cells = <1>;
 217                 #reset-cells = <1>;
 218         };
 219
 220         pericfg: syscon@10003000 {
 221                 compatible =  "mediatek,mt7623-pericfg",
 222                               "mediatek,mt2701-pericfg",
 223                               "syscon";
 224                 reg = <0 0x10003000 0 0x1000>;
 225                 #clock-cells = <1>;
 226                 #reset-cells = <1>;
 227         };
 228
 229         pio: pinctrl@10005000 {
 230                 compatible = "mediatek,mt7623-pinctrl";
 231                 reg = <0 0x1000b000 0 0x1000>;
 232                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 233                 pins-are-numbered;
 234                 gpio-controller;
 235                 #gpio-cells = <2>;
 236                 interrupt-controller;
 237                 interrupt-parent = <&gic>;
 238                 #interrupt-cells = <2>;
 239                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 241         };
 242
 243         syscfg_pctl_a: syscfg@10005000 {
 244                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 245                 reg = <0 0x10005000 0 0x1000>;
 246         };
 247
 248         scpsys: scpsys@10006000 {
 249                 compatible = "mediatek,mt7623-scpsys",
 250                              "mediatek,mt2701-scpsys",
 251                              "syscon";
 252                 #power-domain-cells = <1>;
 253                 reg = <0 0x10006000 0 0x1000>;
 254                 infracfg = <&infracfg>;
 255                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 256                          <&topckgen CLK_TOP_MFG_SEL>,
 257                          <&topckgen CLK_TOP_ETHIF_SEL>;
 258                 clock-names = "mm", "mfg", "ethif";
 259         };
 260
 261         watchdog: watchdog@10007000 {
 262                 compatible = "mediatek,mt7623-wdt",
 263                              "mediatek,mt6589-wdt";
 264                 reg = <0 0x10007000 0 0x100>;
 265         };
 266
 267         timer: timer@10008000 {
 268                 compatible = "mediatek,mt7623-timer",
 269                              "mediatek,mt6577-timer";
 270                 reg = <0 0x10008000 0 0x80>;
 271                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 272                 clocks = <&system_clk>, <&rtc32k>;
 273                 clock-names = "system-clk", "rtc-clk";
 274         };
 275
 276         pwrap: pwrap@1000d000 {
 277                 compatible = "mediatek,mt7623-pwrap",
 278                              "mediatek,mt2701-pwrap";
 279                 reg = <0 0x1000d000 0 0x1000>;
 280                 reg-names = "pwrap";
 281                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 282                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 283                 reset-names = "pwrap";
 284                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 285                          <&infracfg CLK_INFRA_PMICWRAP>;
 286                 clock-names = "spi", "wrap";
 287         };
 288
 289         cir: cir@10013000 {
 290                 compatible = "mediatek,mt7623-cir";
 291                 reg = <0 0x10013000 0 0x1000>;
 292                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 293                 clocks = <&infracfg CLK_INFRA_IRRX>;
 294                 clock-names = "clk";
 295                 status = "disabled";
 296         };
 297
 298         sysirq: interrupt-controller@10200100 {
 299                 compatible = "mediatek,mt7623-sysirq",
 300                              "mediatek,mt6577-sysirq";
 301                 interrupt-controller;
 302                 #interrupt-cells = <3>;
 303                 interrupt-parent = <&gic>;
 304                 reg = <0 0x10200100 0 0x1c>;
 305         };
 306
 307         efuse: efuse@10206000 {
 308                 compatible = "mediatek,mt7623-efuse",
 309                              "mediatek,mt8173-efuse";
 310                 reg = <0 0x10206000 0 0x1000>;
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 thermal_calibration_data: calib@424 {
 314                         reg = <0x424 0xc>;
 315                 };
 316         };
 317
 318         apmixedsys: syscon@10209000 {
 319                 compatible = "mediatek,mt7623-apmixedsys",
 320                              "mediatek,mt2701-apmixedsys",
 321                              "syscon";
 322                 reg = <0 0x10209000 0 0x1000>;
 323                 #clock-cells = <1>;
 324         };
 325
 326         rng: rng@1020f000 {
 327                 compatible = "mediatek,mt7623-rng";
 328                 reg = <0 0x1020f000 0 0x1000>;
 329                 clocks = <&infracfg CLK_INFRA_TRNG>;
 330                 clock-names = "rng";
 331         };
 332
 333         gic: interrupt-controller@10211000 {
 334                 compatible = "arm,cortex-a7-gic";
 335                 interrupt-controller;
 336                 #interrupt-cells = <3>;
 337                 interrupt-parent = <&gic>;
 338                 reg = <0 0x10211000 0 0x1000>,
 339                       <0 0x10212000 0 0x2000>,
 340                       <0 0x10214000 0 0x2000>,
 341                       <0 0x10216000 0 0x2000>;
 342         };
 343
 344         auxadc: adc@11001000 {
 345                 compatible = "mediatek,mt7623-auxadc",
 346                              "mediatek,mt2701-auxadc";
 347                 reg = <0 0x11001000 0 0x1000>;
 348                 clocks = <&pericfg CLK_PERI_AUXADC>;
 349                 clock-names = "main";
 350                 #io-channel-cells = <1>;
 351         };
 352
 353         uart0: serial@11002000 {
 354                 compatible = "mediatek,mt7623-uart",
 355                              "mediatek,mt6577-uart";
 356                 reg = <0 0x11002000 0 0x400>;
 357                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 358                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 359                          <&pericfg CLK_PERI_UART0>;
 360                 clock-names = "baud", "bus";
 361                 status = "disabled";
 362         };
 363
 364         uart1: serial@11003000 {
 365                 compatible = "mediatek,mt7623-uart",
 366                              "mediatek,mt6577-uart";
 367                 reg = <0 0x11003000 0 0x400>;
 368                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 369                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 370                          <&pericfg CLK_PERI_UART1>;
 371                 clock-names = "baud", "bus";
 372                 status = "disabled";
 373         };
 374
 375         uart2: serial@11004000 {
 376                 compatible = "mediatek,mt7623-uart",
 377                              "mediatek,mt6577-uart";
 378                 reg = <0 0x11004000 0 0x400>;
 379                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 380                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 381                          <&pericfg CLK_PERI_UART2>;
 382                 clock-names = "baud", "bus";
 383                 status = "disabled";
 384         };
 385
 386         uart3: serial@11005000 {
 387                 compatible = "mediatek,mt7623-uart",
 388                              "mediatek,mt6577-uart";
 389                 reg = <0 0x11005000 0 0x400>;
 390                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 391                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 392                          <&pericfg CLK_PERI_UART3>;
 393                 clock-names = "baud", "bus";
 394                 status = "disabled";
 395         };
 396
 397         pwm: pwm@11006000 {
 398                 compatible = "mediatek,mt7623-pwm";
 399                 reg = <0 0x11006000 0 0x1000>;
 400                 #pwm-cells = <2>;
 401                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 402                          <&pericfg CLK_PERI_PWM>,
 403                          <&pericfg CLK_PERI_PWM1>,
 404                          <&pericfg CLK_PERI_PWM2>,
 405                          <&pericfg CLK_PERI_PWM3>,
 406                          <&pericfg CLK_PERI_PWM4>,
 407                          <&pericfg CLK_PERI_PWM5>;
 408                 clock-names = "top", "main", "pwm1", "pwm2",
 409                               "pwm3", "pwm4", "pwm5";
 410                 status = "disabled";
 411         };
 412
 413         i2c0: i2c@11007000 {
 414                 compatible = "mediatek,mt7623-i2c",
 415                              "mediatek,mt6577-i2c";
 416                 reg = <0 0x11007000 0 0x70>,
 417                       <0 0x11000200 0 0x80>;
 418                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 419                 clock-div = <16>;
 420                 clocks = <&pericfg CLK_PERI_I2C0>,
 421                          <&pericfg CLK_PERI_AP_DMA>;
 422                 clock-names = "main", "dma";
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 status = "disabled";
 426         };
 427
 428         i2c1: i2c@11008000 {
 429                 compatible = "mediatek,mt7623-i2c",
 430                              "mediatek,mt6577-i2c";
 431                 reg = <0 0x11008000 0 0x70>,
 432                       <0 0x11000280 0 0x80>;
 433                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 434                 clock-div = <16>;
 435                 clocks = <&pericfg CLK_PERI_I2C1>,
 436                          <&pericfg CLK_PERI_AP_DMA>;
 437                 clock-names = "main", "dma";
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 status = "disabled";
 441         };
 442
 443         i2c2: i2c@11009000 {
 444                 compatible = "mediatek,mt7623-i2c",
 445                              "mediatek,mt6577-i2c";
 446                 reg = <0 0x11009000 0 0x70>,
 447                       <0 0x11000300 0 0x80>;
 448                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 449                 clock-div = <16>;
 450                 clocks = <&pericfg CLK_PERI_I2C2>,
 451                          <&pericfg CLK_PERI_AP_DMA>;
 452                 clock-names = "main", "dma";
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 status = "disabled";
 456         };
 457
 458         spi0: spi@1100a000 {
 459                 compatible = "mediatek,mt7623-spi",
 460                              "mediatek,mt2701-spi";
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 reg = <0 0x1100a000 0 0x100>;
 464                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 465                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 466                          <&topckgen CLK_TOP_SPI0_SEL>,
 467                          <&pericfg CLK_PERI_SPI0>;
 468                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 469                 status = "disabled";
 470         };
 471
 472         thermal: thermal@1100b000 {
 473                 #thermal-sensor-cells = <1>;
 474                 compatible = "mediatek,mt7623-thermal",
 475                              "mediatek,mt2701-thermal";
 476                 reg = <0 0x1100b000 0 0x1000>;
 477                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 478                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 479                 clock-names = "therm", "auxadc";
 480                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 481                 reset-names = "therm";
 482                 mediatek,auxadc = <&auxadc>;
 483                 mediatek,apmixedsys = <&apmixedsys>;
 484                 nvmem-cells = <&thermal_calibration_data>;
 485                 nvmem-cell-names = "calibration-data";
 486         };
 487
 488         nandc: nfi@1100d000 {
 489                 compatible = "mediatek,mt7623-nfc",
 490                              "mediatek,mt2701-nfc";
 491                 reg = <0 0x1100d000 0 0x1000>;
 492                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 493                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 494                 clocks = <&pericfg CLK_PERI_NFI>,
 495                          <&pericfg CLK_PERI_NFI_PAD>;
 496                 clock-names = "nfi_clk", "pad_clk";
 497                 status = "disabled";
 498                 ecc-engine = <&bch>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501         };
 502
 503         bch: ecc@1100e000 {
 504                 compatible = "mediatek,mt7623-ecc",
 505                              "mediatek,mt2701-ecc";
 506                 reg = <0 0x1100e000 0 0x1000>;
 507                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 508                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 509                 clock-names = "nfiecc_clk";
 510                 status = "disabled";
 511         };
 512
 513         spi1: spi@11016000 {
 514                 compatible = "mediatek,mt7623-spi",
 515                              "mediatek,mt2701-spi";
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 reg = <0 0x11016000 0 0x100>;
 519                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 520                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 521                          <&topckgen CLK_TOP_SPI1_SEL>,
 522                          <&pericfg CLK_PERI_SPI1>;
 523                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 524                 status = "disabled";
 525         };
 526
 527         spi2: spi@11017000 {
 528                 compatible = "mediatek,mt7623-spi",
 529                              "mediatek,mt2701-spi";
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 reg = <0 0x11017000 0 0x1000>;
 533                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 534                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 535                          <&topckgen CLK_TOP_SPI2_SEL>,
 536                          <&pericfg CLK_PERI_SPI2>;
 537                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 538                 status = "disabled";
 539         };
 540
 541         afe: audio-controller@11220000 {
 542                 compatible = "mediatek,mt7623-audio",
 543                              "mediatek,mt2701-audio";
 544                 reg = <0 0x11220000 0 0x2000>,
 545                       <0 0x112a0000 0 0x20000>;
 546                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 547                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 548                 interrupt-names = "afe", "asys";
 549                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 550
 551                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 552                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 553                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 554                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 555                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 556                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 557                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 558                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 559                          <&topckgen CLK_TOP_APLL_SEL>,
 560                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 561                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 562                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 563                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 564                          <&topckgen CLK_TOP_AUDPLL>,
 565                          <&topckgen CLK_TOP_AUDPLL_D4>,
 566                          <&topckgen CLK_TOP_AUDPLL_D8>,
 567                          <&topckgen CLK_TOP_AUDPLL_D16>,
 568                          <&topckgen CLK_TOP_AUDPLL_D24>,
 569                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 570                          <&clk26m>,
 571                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 572                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 573                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 574                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 575                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 576                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 577                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 578                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 579                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 580                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 581                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 582                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 583                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 584                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 585                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 586                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 587                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 588                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 589                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 590                          <&topckgen CLK_TOP_ASM_M_SEL>,
 591                          <&topckgen CLK_TOP_ASM_H_SEL>,
 592                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 593                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 594                          <&topckgen CLK_TOP_SYSPLL_D5>;
 595
 596                 clock-names = "infra_sys_audio_clk",
 597                          "top_audio_mux1_sel",
 598                          "top_audio_mux2_sel",
 599                          "top_audio_mux1_div",
 600                          "top_audio_mux2_div",
 601                          "top_audio_48k_timing",
 602                          "top_audio_44k_timing",
 603                          "top_audpll_mux_sel",
 604                          "top_apll_sel",
 605                          "top_aud1_pll_98M",
 606                          "top_aud2_pll_90M",
 607                          "top_hadds2_pll_98M",
 608                          "top_hadds2_pll_294M",
 609                          "top_audpll",
 610                          "top_audpll_d4",
 611                          "top_audpll_d8",
 612                          "top_audpll_d16",
 613                          "top_audpll_d24",
 614                          "top_audintbus_sel",
 615                          "clk_26m",
 616                          "top_syspll1_d4",
 617                          "top_aud_k1_src_sel",
 618                          "top_aud_k2_src_sel",
 619                          "top_aud_k3_src_sel",
 620                          "top_aud_k4_src_sel",
 621                          "top_aud_k5_src_sel",
 622                          "top_aud_k6_src_sel",
 623                          "top_aud_k1_src_div",
 624                          "top_aud_k2_src_div",
 625                          "top_aud_k3_src_div",
 626                          "top_aud_k4_src_div",
 627                          "top_aud_k5_src_div",
 628                          "top_aud_k6_src_div",
 629                          "top_aud_i2s1_mclk",
 630                          "top_aud_i2s2_mclk",
 631                          "top_aud_i2s3_mclk",
 632                          "top_aud_i2s4_mclk",
 633                          "top_aud_i2s5_mclk",
 634                          "top_aud_i2s6_mclk",
 635                          "top_asm_m_sel",
 636                          "top_asm_h_sel",
 637                          "top_univpll2_d4",
 638                          "top_univpll2_d2",
 639                          "top_syspll_d5";
 640         };
 641
 642         mmc0: mmc@11230000 {
 643                 compatible = "mediatek,mt7623-mmc",
 644                              "mediatek,mt2701-mmc";
 645                 reg = <0 0x11230000 0 0x1000>;
 646                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 647                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 648                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 649                 clock-names = "source", "hclk";
 650                 status = "disabled";
 651         };
 652
 653         mmc1: mmc@11240000 {
 654                 compatible = "mediatek,mt7623-mmc",
 655                              "mediatek,mt2701-mmc";
 656                 reg = <0 0x11240000 0 0x1000>;
 657                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 658                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 659                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 660                 clock-names = "source", "hclk";
 661                 status = "disabled";
 662         };
 663
 664         hifsys: syscon@1a000000 {
 665                 compatible = "mediatek,mt7623-hifsys",
 666                              "mediatek,mt2701-hifsys",
 667                              "syscon";
 668                 reg = <0 0x1a000000 0 0x1000>;
 669                 #clock-cells = <1>;
 670                 #reset-cells = <1>;
 671         };
 672
 673         usb1: usb@1a1c0000 {
 674                 compatible = "mediatek,mt7623-xhci",
 675                              "mediatek,mt8173-xhci";
 676                 reg = <0 0x1a1c0000 0 0x1000>,
 677                       <0 0x1a1c4700 0 0x0100>;
 678                 reg-names = "mac", "ippc";
 679                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 680                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 681                          <&topckgen CLK_TOP_ETHIF_SEL>;
 682                 clock-names = "sys_ck", "ref_ck";
 683                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 684                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 685                 status = "disabled";
 686         };
 687
 688         u3phy1: usb-phy@1a1c4000 {
 689                 compatible = "mediatek,mt7623-u3phy",
 690                              "mediatek,mt2701-u3phy";
 691                 reg = <0 0x1a1c4000 0 0x0700>;
 692                 #address-cells = <2>;
 693                 #size-cells = <2>;
 694                 ranges;
 695                 status = "disabled";
 696
 697                 u2port0: usb-phy@1a1c4800 {
 698                         reg = <0 0x1a1c4800 0 0x0100>;
 699                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 700                         clock-names = "ref";
 701                         #phy-cells = <1>;
 702                         status = "okay";
 703                 };
 704
 705                 u3port0: usb-phy@1a1c4900 {
 706                         reg = <0 0x1a1c4900 0 0x0700>;
 707                         clocks = <&clk26m>;
 708                         clock-names = "ref";
 709                         #phy-cells = <1>;
 710                         status = "okay";
 711                 };
 712         };
 713
 714         usb2: usb@1a240000 {
 715                 compatible = "mediatek,mt7623-xhci",
 716                              "mediatek,mt8173-xhci";
 717                 reg = <0 0x1a240000 0 0x1000>,
 718                       <0 0x1a244700 0 0x0100>;
 719                 reg-names = "mac", "ippc";
 720                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 721                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 722                          <&topckgen CLK_TOP_ETHIF_SEL>;
 723                 clock-names = "sys_ck", "ref_ck";
 724                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 725                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 726                 status = "disabled";
 727         };
 728
 729         u3phy2: usb-phy@1a244000 {
 730                 compatible = "mediatek,mt7623-u3phy",
 731                              "mediatek,mt2701-u3phy";
 732                 reg = <0 0x1a244000 0 0x0700>;
 733                 #address-cells = <2>;
 734                 #size-cells = <2>;
 735                 ranges;
 736                 status = "disabled";
 737
 738                 u2port1: usb-phy@1a244800 {
 739                         reg = <0 0x1a244800 0 0x0100>;
 740                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 741                         clock-names = "ref";
 742                         #phy-cells = <1>;
 743                         status = "okay";
 744                 };
 745
 746                 u3port1: usb-phy@1a244900 {
 747                         reg = <0 0x1a244900 0 0x0700>;
 748                         clocks = <&clk26m>;
 749                         clock-names = "ref";
 750                         #phy-cells = <1>;
 751                         status = "okay";
 752                 };
 753         };
 754
 755         ethsys: syscon@1b000000 {
 756                 compatible = "mediatek,mt7623-ethsys",
 757                              "mediatek,mt2701-ethsys",
 758                              "syscon";
 759                 reg = <0 0x1b000000 0 0x1000>;
 760                 #clock-cells = <1>;
 761                 #reset-cells = <1>;
 762         };
 763
 764         eth: ethernet@1b100000 {
 765                 compatible = "mediatek,mt7623-eth",
 766                              "mediatek,mt2701-eth",
 767                              "syscon";
 768                 reg = <0 0x1b100000 0 0x20000>;
 769                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 770                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 771                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 772                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 773                          <&ethsys CLK_ETHSYS_ESW>,
 774                          <&ethsys CLK_ETHSYS_GP1>,
 775                          <&ethsys CLK_ETHSYS_GP2>,
 776                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 777                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 778                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 779                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 780                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 781                 reset-names = "fe", "gmac", "ppe";
 782                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 783                 mediatek,ethsys = <&ethsys>;
 784                 mediatek,pctl = <&syscfg_pctl_a>;
 785                 #address-cells = <1>;
 786                 #size-cells = <0>;
 787                 status = "disabled";
 788         };
 789
 790         crypto: crypto@1b240000 {
 791                 compatible = "mediatek,eip97-crypto";
 792                 reg = <0 0x1b240000 0 0x20000>;
 793                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 794                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 795                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 796                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 797                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 798                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 799                 clock-names = "cryp";
 800                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 801                 status = "disabled";
 802         };
 803 };