arch/arm/boot/dts/mt6589.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2014 MundoReader S.L.
   4  * Author: Matthias Brugger <matthias.bgg@gmail.com>
   5  *
   6 */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "mediatek,mt6589";
  14         interrupt-parent = <&sysirq>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a7";
  23                         reg = <0x0>;
  24                 };
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a7";
  28                         reg = <0x1>;
  29                 };
  30                 cpu@2 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a7";
  33                         reg = <0x2>;
  34                 };
  35                 cpu@3 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x3>;
  39                 };
  40
  41         };
  42
  43         clocks {
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 compatible = "simple-bus";
  47                 ranges;
  48
  49                 system_clk: dummy13m {
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <13000000>;
  52                         #clock-cells = <0>;
  53                 };
  54
  55                 rtc_clk: dummy32k {
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <32000>;
  58                         #clock-cells = <0>;
  59                 };
  60
  61                 uart_clk: dummy26m {
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <26000000>;
  64                         #clock-cells = <0>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 ranges;
  73
  74                 timer: timer@10008000 {
  75                         compatible = "mediatek,mt6577-timer";
  76                         reg = <0x10008000 0x80>;
  77                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
  78                         clocks = <&system_clk>, <&rtc_clk>;
  79                         clock-names = "system-clk", "rtc-clk";
  80                 };
  81
  82                 sysirq: interrupt-controller@10200100 {
  83                         compatible = "mediatek,mt6589-sysirq",
  84                                      "mediatek,mt6577-sysirq";
  85                         interrupt-controller;
  86                         #interrupt-cells = <3>;
  87                         interrupt-parent = <&gic>;
  88                         reg = <0x10200100 0x1c>;
  89                 };
  90
  91                 gic: interrupt-controller@10211000 {
  92                         compatible = "arm,cortex-a7-gic";
  93                         interrupt-controller;
  94                         #interrupt-cells = <3>;
  95                         interrupt-parent = <&gic>;
  96                         reg = <0x10211000 0x1000>,
  97                               <0x10212000 0x2000>,
  98                               <0x10214000 0x2000>,
  99                               <0x10216000 0x2000>;
 100                 };
 101
 102                 uart0: serial@11006000 {
 103                         compatible = "mediatek,mt6577-uart";
 104                         reg = <0x11006000 0x400>;
 105                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 106                         clocks = <&uart_clk>;
 107                         status = "disabled";
 108                 };
 109
 110                 uart1: serial@11007000 {
 111                         compatible = "mediatek,mt6577-uart";
 112                         reg = <0x11007000 0x400>;
 113                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 114                         clocks = <&uart_clk>;
 115                         status = "disabled";
 116                 };
 117
 118                 uart2: serial@11008000 {
 119                         compatible = "mediatek,mt6577-uart";
 120                         reg = <0x11008000 0x400>;
 121                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 122                         clocks = <&uart_clk>;
 123                         status = "disabled";
 124                 };
 125
 126                 uart3: serial@11009000 {
 127                         compatible = "mediatek,mt6577-uart";
 128                         reg = <0x11009000 0x400>;
 129                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 wdt: watchdog@10000000 {
 135                         compatible = "mediatek,mt6589-wdt";
 136                         reg = <0x10000000 0x44>;
 137                 };
 138         };
 139 };