arch/arm/boot/dts/mt2701.dtsi

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Erin.Lo <erin.lo@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/clock/mt2701-clk.h>
  16 #include <dt-bindings/power/mt2701-power.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/memory/mt2701-larb-port.h>
  20 #include <dt-bindings/reset/mt2701-resets.h>
  21 #include "skeleton64.dtsi"
  22 #include "mt2701-pinfunc.h"
  23
  24 / {
  25         compatible = "mediatek,mt2701";
  26         interrupt-parent = <&cirq>;
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31                 enable-method = "mediatek,mt81xx-tz-smp";
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0x0>;
  37                 };
  38                 cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0x1>;
  42                 };
  43                 cpu@2 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a7";
  46                         reg = <0x2>;
  47                 };
  48                 cpu@3 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0x3>;
  52                 };
  53         };
  54
  55         reserved-memory {
  56                 #address-cells = <2>;
  57                 #size-cells = <2>;
  58                 ranges;
  59
  60                 trustzone-bootinfo@80002000 {
  61                         compatible = "mediatek,trustzone-bootinfo";
  62                         reg = <0 0x80002000 0 0x1000>;
  63                 };
  64         };
  65
  66         system_clk: dummy13m {
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <13000000>;
  69                 #clock-cells = <0>;
  70         };
  71
  72         rtc_clk: dummy32k {
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <32000>;
  75                 #clock-cells = <0>;
  76         };
  77
  78         clk26m: oscillator@0 {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <26000000>;
  82                 clock-output-names = "clk26m";
  83         };
  84
  85         rtc32k: oscillator@1 {
  86                 compatible = "fixed-clock";
  87                 #clock-cells = <0>;
  88                 clock-frequency = <32000>;
  89                 clock-output-names = "rtc32k";
  90         };
  91
  92         thermal-zones {
  93                 cpu_thermal: cpu_thermal {
  94                         polling-delay-passive = <1000>; /* milliseconds */
  95                         polling-delay = <1000>; /* milliseconds */
  96
  97                         thermal-sensors = <&thermal 0>;
  98                         sustainable-power = <1000>;
  99
 100                         trips {
 101                                 threshold: trip-point@0 {
 102                                         temperature = <68000>;
 103                                         hysteresis = <2000>;
 104                                         type = "passive";
 105                                 };
 106
 107                                 target: trip-point@1 {
 108                                         temperature = <85000>;
 109                                         hysteresis = <2000>;
 110                                         type = "passive";
 111                                 };
 112
 113                                 cpu_crit: cpu_crit@0 {
 114                                         temperature = <115000>;
 115                                         hysteresis = <2000>;
 116                                         type = "critical";
 117                                 };
 118                         };
 119                 };
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv7-timer";
 124                 interrupt-parent = <&gic>;
 125                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 129         };
 130
 131         topckgen: syscon@10000000 {
 132                 compatible = "mediatek,mt2701-topckgen", "syscon";
 133                 reg = <0 0x10000000 0 0x1000>;
 134                 #clock-cells = <1>;
 135         };
 136
 137         infracfg: syscon@10001000 {
 138                 compatible = "mediatek,mt2701-infracfg", "syscon";
 139                 reg = <0 0x10001000 0 0x1000>;
 140                 #clock-cells = <1>;
 141                 #reset-cells = <1>;
 142         };
 143
 144         pericfg: syscon@10003000 {
 145                 compatible = "mediatek,mt2701-pericfg", "syscon";
 146                 reg = <0 0x10003000 0 0x1000>;
 147                 #clock-cells = <1>;
 148                 #reset-cells = <1>;
 149         };
 150
 151         syscfg_pctl_a: syscfg@10005000 {
 152                 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
 153                 reg = <0 0x10005000 0 0x1000>;
 154         };
 155
 156         scpsys: scpsys@10006000 {
 157                 compatible = "mediatek,mt2701-scpsys", "syscon";
 158                 #power-domain-cells = <1>;
 159                 reg = <0 0x10006000 0 0x1000>;
 160                 infracfg = <&infracfg>;
 161                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 162                          <&topckgen CLK_TOP_MFG_SEL>,
 163                          <&topckgen CLK_TOP_ETHIF_SEL>;
 164                 clock-names = "mm", "mfg", "ethif";
 165         };
 166
 167         watchdog: watchdog@10007000 {
 168                 compatible = "mediatek,mt2701-wdt",
 169                              "mediatek,mt6589-wdt";
 170                 reg = <0 0x10007000 0 0x100>;
 171         };
 172
 173         timer: timer@10008000 {
 174                 compatible = "mediatek,mt2701-timer",
 175                              "mediatek,mt6577-timer";
 176                 reg = <0 0x10008000 0 0x80>;
 177                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 178                 clocks = <&system_clk>, <&rtc_clk>;
 179                 clock-names = "system-clk", "rtc-clk";
 180         };
 181
 182         pio: pinctrl@1000b000 {
 183                 compatible = "mediatek,mt2701-pinctrl";
 184                 reg = <0 0x1000b000 0 0x1000>;
 185                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 186                 pins-are-numbered;
 187                 gpio-controller;
 188                 #gpio-cells = <2>;
 189                 interrupt-controller;
 190                 #interrupt-cells = <2>;
 191                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 193         };
 194
 195         smi_common: smi@1000c000 {
 196                 compatible = "mediatek,mt2701-smi-common";
 197                 reg = <0 0x1000c000 0 0x1000>;
 198                 clocks = <&infracfg CLK_INFRA_SMI>,
 199                          <&mmsys CLK_MM_SMI_COMMON>,
 200                          <&infracfg CLK_INFRA_SMI>;
 201                 clock-names = "apb", "smi", "async";
 202                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 203         };
 204
 205         sysirq: interrupt-controller@10200100 {
 206                 compatible = "mediatek,mt2701-sysirq",
 207                              "mediatek,mt6577-sysirq";
 208                 interrupt-controller;
 209                 #interrupt-cells = <3>;
 210                 interrupt-parent = <&gic>;
 211                 reg = <0 0x10200100 0 0x1c>;
 212         };
 213
 214         cirq: interrupt-controller@10204000 {
 215                 compatible = "mediatek,mt2701-cirq",
 216                              "mediatek,mtk-cirq";
 217                 interrupt-controller;
 218                 #interrupt-cells = <3>;
 219                 interrupt-parent = <&sysirq>;
 220                 reg = <0 0x10204000 0 0x400>;
 221                 mediatek,ext-irq-range = <32 200>;
 222         };
 223
 224         iommu: mmsys_iommu@10205000 {
 225                 compatible = "mediatek,mt2701-m4u";
 226                 reg = <0 0x10205000 0 0x1000>;
 227                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 228                 clocks = <&infracfg CLK_INFRA_M4U>;
 229                 clock-names = "bclk";
 230                 mediatek,larbs = <&larb0 &larb1 &larb2>;
 231                 #iommu-cells = <1>;
 232         };
 233
 234         apmixedsys: syscon@10209000 {
 235                 compatible = "mediatek,mt2701-apmixedsys", "syscon";
 236                 reg = <0 0x10209000 0 0x1000>;
 237                 #clock-cells = <1>;
 238         };
 239
 240         gic: interrupt-controller@10211000 {
 241                 compatible = "arm,cortex-a7-gic";
 242                 interrupt-controller;
 243                 #interrupt-cells = <3>;
 244                 interrupt-parent = <&gic>;
 245                 reg = <0 0x10211000 0 0x1000>,
 246                       <0 0x10212000 0 0x2000>,
 247                       <0 0x10214000 0 0x2000>,
 248                       <0 0x10216000 0 0x2000>;
 249         };
 250
 251         auxadc: adc@11001000 {
 252                 compatible = "mediatek,mt2701-auxadc";
 253                 reg = <0 0x11001000 0 0x1000>;
 254                 clocks = <&pericfg CLK_PERI_AUXADC>;
 255                 clock-names = "main";
 256                 #io-channel-cells = <1>;
 257                 status = "disabled";
 258         };
 259
 260         uart0: serial@11002000 {
 261                 compatible = "mediatek,mt2701-uart",
 262                              "mediatek,mt6577-uart";
 263                 reg = <0 0x11002000 0 0x400>;
 264                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 265                 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 266                 clock-names = "baud", "bus";
 267                 status = "disabled";
 268         };
 269
 270         uart1: serial@11003000 {
 271                 compatible = "mediatek,mt2701-uart",
 272                              "mediatek,mt6577-uart";
 273                 reg = <0 0x11003000 0 0x400>;
 274                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 275                 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 276                 clock-names = "baud", "bus";
 277                 status = "disabled";
 278         };
 279
 280         uart2: serial@11004000 {
 281                 compatible = "mediatek,mt2701-uart",
 282                              "mediatek,mt6577-uart";
 283                 reg = <0 0x11004000 0 0x400>;
 284                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 285                 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 286                 clock-names = "baud", "bus";
 287                 status = "disabled";
 288         };
 289
 290         uart3: serial@11005000 {
 291                 compatible = "mediatek,mt2701-uart",
 292                              "mediatek,mt6577-uart";
 293                 reg = <0 0x11005000 0 0x400>;
 294                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 295                 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 296                 clock-names = "baud", "bus";
 297                 status = "disabled";
 298         };
 299
 300         i2c0: i2c@11007000 {
 301                 compatible = "mediatek,mt2701-i2c",
 302                              "mediatek,mt6577-i2c";
 303                 reg = <0 0x11007000 0 0x70>,
 304                       <0 0x11000200 0 0x80>;
 305                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 306                 clock-div = <16>;
 307                 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
 308                 clock-names = "main", "dma";
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 status = "disabled";
 312         };
 313
 314         i2c1: i2c@11008000 {
 315                 compatible = "mediatek,mt2701-i2c",
 316                              "mediatek,mt6577-i2c";
 317                 reg = <0 0x11008000 0 0x70>,
 318                       <0 0x11000280 0 0x80>;
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 320                 clock-div = <16>;
 321                 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
 322                 clock-names = "main", "dma";
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         i2c2: i2c@11009000 {
 329                 compatible = "mediatek,mt2701-i2c",
 330                              "mediatek,mt6577-i2c";
 331                 reg = <0 0x11009000 0 0x70>,
 332                       <0 0x11000300 0 0x80>;
 333                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 334                 clock-div = <16>;
 335                 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
 336                 clock-names = "main", "dma";
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 status = "disabled";
 340         };
 341
 342         spi0: spi@1100a000 {
 343                 compatible = "mediatek,mt2701-spi";
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346                 reg = <0 0x1100a000 0 0x100>;
 347                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 348                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 349                          <&topckgen CLK_TOP_SPI0_SEL>,
 350                          <&pericfg CLK_PERI_SPI0>;
 351                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 352                 status = "disabled";
 353         };
 354
 355         thermal: thermal@1100b000 {
 356                 #thermal-sensor-cells = <0>;
 357                 compatible = "mediatek,mt2701-thermal";
 358                 reg = <0 0x1100b000 0 0x1000>;
 359                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
 360                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 361                 clock-names = "therm", "auxadc";
 362                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 363                 reset-names = "therm";
 364                 mediatek,auxadc = <&auxadc>;
 365                 mediatek,apmixedsys = <&apmixedsys>;
 366         };
 367
 368         nandc: nfi@1100d000 {
 369                 compatible = "mediatek,mt2701-nfc";
 370                 reg = <0 0x1100d000 0 0x1000>;
 371                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 372                 clocks = <&pericfg CLK_PERI_NFI>,
 373                          <&pericfg CLK_PERI_NFI_PAD>;
 374                 clock-names = "nfi_clk", "pad_clk";
 375                 status = "disabled";
 376                 ecc-engine = <&bch>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379         };
 380
 381         bch: ecc@1100e000 {
 382                 compatible = "mediatek,mt2701-ecc";
 383                 reg = <0 0x1100e000 0 0x1000>;
 384                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 385                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 386                 clock-names = "nfiecc_clk";
 387                 status = "disabled";
 388         };
 389
 390         nor_flash: spi@11014000 {
 391                 compatible = "mediatek,mt2701-nor",
 392                              "mediatek,mt8173-nor";
 393                 reg = <0 0x11014000 0 0xe0>;
 394                 clocks = <&pericfg CLK_PERI_FLASH>,
 395                          <&topckgen CLK_TOP_FLASH_SEL>;
 396                 clock-names = "spi", "sf";
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         spi1: spi@11016000 {
 403                 compatible = "mediatek,mt2701-spi";
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 reg = <0 0x11016000 0 0x100>;
 407                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 408                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 409                          <&topckgen CLK_TOP_SPI1_SEL>,
 410                          <&pericfg CLK_PERI_SPI1>;
 411                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 412                 status = "disabled";
 413         };
 414
 415         spi2: spi@11017000 {
 416                 compatible = "mediatek,mt2701-spi";
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 reg = <0 0x11017000 0 0x1000>;
 420                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 421                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 422                          <&topckgen CLK_TOP_SPI2_SEL>,
 423                          <&pericfg CLK_PERI_SPI2>;
 424                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 425                 status = "disabled";
 426         };
 427
 428         afe: audio-controller@11220000 {
 429                 compatible = "mediatek,mt2701-audio";
 430                 reg = <0 0x11220000 0 0x2000>,
 431                       <0 0x112a0000 0 0x20000>;
 432                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 433                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 434
 435                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 436                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 437                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 438                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 439                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 440                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 441                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 442                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 443                          <&topckgen CLK_TOP_APLL_SEL>,
 444                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 445                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 446                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 447                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 448                          <&topckgen CLK_TOP_AUDPLL>,
 449                          <&topckgen CLK_TOP_AUDPLL_D4>,
 450                          <&topckgen CLK_TOP_AUDPLL_D8>,
 451                          <&topckgen CLK_TOP_AUDPLL_D16>,
 452                          <&topckgen CLK_TOP_AUDPLL_D24>,
 453                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 454                          <&clk26m>,
 455                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 456                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 457                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 458                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 459                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 460                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 461                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 462                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 463                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 464                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 465                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 466                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 467                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 468                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 469                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 470                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 471                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 472                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 473                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 474                          <&topckgen CLK_TOP_ASM_M_SEL>,
 475                          <&topckgen CLK_TOP_ASM_H_SEL>,
 476                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 477                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 478                          <&topckgen CLK_TOP_SYSPLL_D5>;
 479
 480                 clock-names = "infra_sys_audio_clk",
 481                          "top_audio_mux1_sel",
 482                          "top_audio_mux2_sel",
 483                          "top_audio_mux1_div",
 484                          "top_audio_mux2_div",
 485                          "top_audio_48k_timing",
 486                          "top_audio_44k_timing",
 487                          "top_audpll_mux_sel",
 488                          "top_apll_sel",
 489                          "top_aud1_pll_98M",
 490                          "top_aud2_pll_90M",
 491                          "top_hadds2_pll_98M",
 492                          "top_hadds2_pll_294M",
 493                          "top_audpll",
 494                          "top_audpll_d4",
 495                          "top_audpll_d8",
 496                          "top_audpll_d16",
 497                          "top_audpll_d24",
 498                          "top_audintbus_sel",
 499                          "clk_26m",
 500                          "top_syspll1_d4",
 501                          "top_aud_k1_src_sel",
 502                          "top_aud_k2_src_sel",
 503                          "top_aud_k3_src_sel",
 504                          "top_aud_k4_src_sel",
 505                          "top_aud_k5_src_sel",
 506                          "top_aud_k6_src_sel",
 507                          "top_aud_k1_src_div",
 508                          "top_aud_k2_src_div",
 509                          "top_aud_k3_src_div",
 510                          "top_aud_k4_src_div",
 511                          "top_aud_k5_src_div",
 512                          "top_aud_k6_src_div",
 513                          "top_aud_i2s1_mclk",
 514                          "top_aud_i2s2_mclk",
 515                          "top_aud_i2s3_mclk",
 516                          "top_aud_i2s4_mclk",
 517                          "top_aud_i2s5_mclk",
 518                          "top_aud_i2s6_mclk",
 519                          "top_asm_m_sel",
 520                          "top_asm_h_sel",
 521                          "top_univpll2_d4",
 522                          "top_univpll2_d2",
 523                          "top_syspll_d5";
 524         };
 525
 526         mmsys: syscon@14000000 {
 527                 compatible = "mediatek,mt2701-mmsys", "syscon";
 528                 reg = <0 0x14000000 0 0x1000>;
 529                 #clock-cells = <1>;
 530         };
 531
 532         larb0: larb@14010000 {
 533                 compatible = "mediatek,mt2701-smi-larb";
 534                 reg = <0 0x14010000 0 0x1000>;
 535                 mediatek,smi = <&smi_common>;
 536                 clocks = <&mmsys CLK_MM_SMI_LARB0>,
 537                          <&mmsys CLK_MM_SMI_LARB0>;
 538                 clock-names = "apb", "smi";
 539                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 540         };
 541
 542         imgsys: syscon@15000000 {
 543                 compatible = "mediatek,mt2701-imgsys", "syscon";
 544                 reg = <0 0x15000000 0 0x1000>;
 545                 #clock-cells = <1>;
 546         };
 547
 548         larb2: larb@15001000 {
 549                 compatible = "mediatek,mt2701-smi-larb";
 550                 reg = <0 0x15001000 0 0x1000>;
 551                 mediatek,smi = <&smi_common>;
 552                 clocks = <&imgsys CLK_IMG_SMI_COMM>,
 553                          <&imgsys CLK_IMG_SMI_COMM>;
 554                 clock-names = "apb", "smi";
 555                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 556         };
 557
 558         jpegdec: jpegdec@15004000 {
 559                 compatible = "mediatek,mt2701-jpgdec";
 560                 reg = <0 0x15004000 0 0x1000>;
 561                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
 562                 clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
 563                           <&imgsys CLK_IMG_JPGDEC>;
 564                 clock-names = "jpgdec-smi",
 565                               "jpgdec";
 566                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 567                 mediatek,larb = <&larb2>;
 568                 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
 569                          <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
 570         };
 571
 572         vdecsys: syscon@16000000 {
 573                 compatible = "mediatek,mt2701-vdecsys", "syscon";
 574                 reg = <0 0x16000000 0 0x1000>;
 575                 #clock-cells = <1>;
 576         };
 577
 578         larb1: larb@16010000 {
 579                 compatible = "mediatek,mt2701-smi-larb";
 580                 reg = <0 0x16010000 0 0x1000>;
 581                 mediatek,smi = <&smi_common>;
 582                 clocks = <&vdecsys CLK_VDEC_CKGEN>,
 583                          <&vdecsys CLK_VDEC_LARB>;
 584                 clock-names = "apb", "smi";
 585                 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
 586         };
 587
 588         hifsys: syscon@1a000000 {
 589                 compatible = "mediatek,mt2701-hifsys", "syscon";
 590                 reg = <0 0x1a000000 0 0x1000>;
 591                 #clock-cells = <1>;
 592         };
 593
 594         ethsys: syscon@1b000000 {
 595                 compatible = "mediatek,mt2701-ethsys", "syscon";
 596                 reg = <0 0x1b000000 0 0x1000>;
 597                 #clock-cells = <1>;
 598         };
 599
 600         bdpsys: syscon@1c000000 {
 601                 compatible = "mediatek,mt2701-bdpsys", "syscon";
 602                 reg = <0 0x1c000000 0 0x1000>;
 603                 #clock-cells = <1>;
 604         };
 605 };