arch/arm/boot/dts/mt2701.dtsi

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Erin.Lo <erin.lo@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/clock/mt2701-clk.h>
  16 #include <dt-bindings/phy/phy.h>
  17 #include <dt-bindings/power/mt2701-power.h>
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/memory/mt2701-larb-port.h>
  21 #include <dt-bindings/reset/mt2701-resets.h>
  22 #include "skeleton64.dtsi"
  23 #include "mt2701-pinfunc.h"
  24
  25 / {
  26         compatible = "mediatek,mt2701";
  27         interrupt-parent = <&cirq>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32                 enable-method = "mediatek,mt81xx-tz-smp";
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0x0>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a7";
  42                         reg = <0x1>;
  43                 };
  44                 cpu@2 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a7";
  47                         reg = <0x2>;
  48                 };
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a7";
  52                         reg = <0x3>;
  53                 };
  54         };
  55
  56         reserved-memory {
  57                 #address-cells = <2>;
  58                 #size-cells = <2>;
  59                 ranges;
  60
  61                 trustzone-bootinfo@80002000 {
  62                         compatible = "mediatek,trustzone-bootinfo";
  63                         reg = <0 0x80002000 0 0x1000>;
  64                 };
  65         };
  66
  67         system_clk: dummy13m {
  68                 compatible = "fixed-clock";
  69                 clock-frequency = <13000000>;
  70                 #clock-cells = <0>;
  71         };
  72
  73         rtc_clk: dummy32k {
  74                 compatible = "fixed-clock";
  75                 clock-frequency = <32000>;
  76                 #clock-cells = <0>;
  77         };
  78
  79         clk26m: oscillator@0 {
  80                 compatible = "fixed-clock";
  81                 #clock-cells = <0>;
  82                 clock-frequency = <26000000>;
  83                 clock-output-names = "clk26m";
  84         };
  85
  86         rtc32k: oscillator@1 {
  87                 compatible = "fixed-clock";
  88                 #clock-cells = <0>;
  89                 clock-frequency = <32000>;
  90                 clock-output-names = "rtc32k";
  91         };
  92
  93         thermal-zones {
  94                 cpu_thermal: cpu_thermal {
  95                         polling-delay-passive = <1000>; /* milliseconds */
  96                         polling-delay = <1000>; /* milliseconds */
  97
  98                         thermal-sensors = <&thermal 0>;
  99                         sustainable-power = <1000>;
 100
 101                         trips {
 102                                 threshold: trip-point@0 {
 103                                         temperature = <68000>;
 104                                         hysteresis = <2000>;
 105                                         type = "passive";
 106                                 };
 107
 108                                 target: trip-point@1 {
 109                                         temperature = <85000>;
 110                                         hysteresis = <2000>;
 111                                         type = "passive";
 112                                 };
 113
 114                                 cpu_crit: cpu_crit@0 {
 115                                         temperature = <115000>;
 116                                         hysteresis = <2000>;
 117                                         type = "critical";
 118                                 };
 119                         };
 120                 };
 121         };
 122
 123         timer {
 124                 compatible = "arm,armv7-timer";
 125                 interrupt-parent = <&gic>;
 126                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 130         };
 131
 132         topckgen: syscon@10000000 {
 133                 compatible = "mediatek,mt2701-topckgen", "syscon";
 134                 reg = <0 0x10000000 0 0x1000>;
 135                 #clock-cells = <1>;
 136         };
 137
 138         infracfg: syscon@10001000 {
 139                 compatible = "mediatek,mt2701-infracfg", "syscon";
 140                 reg = <0 0x10001000 0 0x1000>;
 141                 #clock-cells = <1>;
 142                 #reset-cells = <1>;
 143         };
 144
 145         pericfg: syscon@10003000 {
 146                 compatible = "mediatek,mt2701-pericfg", "syscon";
 147                 reg = <0 0x10003000 0 0x1000>;
 148                 #clock-cells = <1>;
 149                 #reset-cells = <1>;
 150         };
 151
 152         syscfg_pctl_a: syscfg@10005000 {
 153                 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
 154                 reg = <0 0x10005000 0 0x1000>;
 155         };
 156
 157         scpsys: scpsys@10006000 {
 158                 compatible = "mediatek,mt2701-scpsys", "syscon";
 159                 #power-domain-cells = <1>;
 160                 reg = <0 0x10006000 0 0x1000>;
 161                 infracfg = <&infracfg>;
 162                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 163                          <&topckgen CLK_TOP_MFG_SEL>,
 164                          <&topckgen CLK_TOP_ETHIF_SEL>;
 165                 clock-names = "mm", "mfg", "ethif";
 166         };
 167
 168         watchdog: watchdog@10007000 {
 169                 compatible = "mediatek,mt2701-wdt",
 170                              "mediatek,mt6589-wdt";
 171                 reg = <0 0x10007000 0 0x100>;
 172         };
 173
 174         timer: timer@10008000 {
 175                 compatible = "mediatek,mt2701-timer",
 176                              "mediatek,mt6577-timer";
 177                 reg = <0 0x10008000 0 0x80>;
 178                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 179                 clocks = <&system_clk>, <&rtc_clk>;
 180                 clock-names = "system-clk", "rtc-clk";
 181         };
 182
 183         pio: pinctrl@1000b000 {
 184                 compatible = "mediatek,mt2701-pinctrl";
 185                 reg = <0 0x1000b000 0 0x1000>;
 186                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 187                 pins-are-numbered;
 188                 gpio-controller;
 189                 #gpio-cells = <2>;
 190                 interrupt-controller;
 191                 #interrupt-cells = <2>;
 192                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 194         };
 195
 196         smi_common: smi@1000c000 {
 197                 compatible = "mediatek,mt2701-smi-common";
 198                 reg = <0 0x1000c000 0 0x1000>;
 199                 clocks = <&infracfg CLK_INFRA_SMI>,
 200                          <&mmsys CLK_MM_SMI_COMMON>,
 201                          <&infracfg CLK_INFRA_SMI>;
 202                 clock-names = "apb", "smi", "async";
 203                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 204         };
 205
 206         sysirq: interrupt-controller@10200100 {
 207                 compatible = "mediatek,mt2701-sysirq",
 208                              "mediatek,mt6577-sysirq";
 209                 interrupt-controller;
 210                 #interrupt-cells = <3>;
 211                 interrupt-parent = <&gic>;
 212                 reg = <0 0x10200100 0 0x1c>;
 213         };
 214
 215         cirq: interrupt-controller@10204000 {
 216                 compatible = "mediatek,mt2701-cirq",
 217                              "mediatek,mtk-cirq";
 218                 interrupt-controller;
 219                 #interrupt-cells = <3>;
 220                 interrupt-parent = <&sysirq>;
 221                 reg = <0 0x10204000 0 0x400>;
 222                 mediatek,ext-irq-range = <32 200>;
 223         };
 224
 225         iommu: mmsys_iommu@10205000 {
 226                 compatible = "mediatek,mt2701-m4u";
 227                 reg = <0 0x10205000 0 0x1000>;
 228                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 229                 clocks = <&infracfg CLK_INFRA_M4U>;
 230                 clock-names = "bclk";
 231                 mediatek,larbs = <&larb0 &larb1 &larb2>;
 232                 #iommu-cells = <1>;
 233         };
 234
 235         apmixedsys: syscon@10209000 {
 236                 compatible = "mediatek,mt2701-apmixedsys", "syscon";
 237                 reg = <0 0x10209000 0 0x1000>;
 238                 #clock-cells = <1>;
 239         };
 240
 241         gic: interrupt-controller@10211000 {
 242                 compatible = "arm,cortex-a7-gic";
 243                 interrupt-controller;
 244                 #interrupt-cells = <3>;
 245                 interrupt-parent = <&gic>;
 246                 reg = <0 0x10211000 0 0x1000>,
 247                       <0 0x10212000 0 0x2000>,
 248                       <0 0x10214000 0 0x2000>,
 249                       <0 0x10216000 0 0x2000>;
 250         };
 251
 252         auxadc: adc@11001000 {
 253                 compatible = "mediatek,mt2701-auxadc";
 254                 reg = <0 0x11001000 0 0x1000>;
 255                 clocks = <&pericfg CLK_PERI_AUXADC>;
 256                 clock-names = "main";
 257                 #io-channel-cells = <1>;
 258                 status = "disabled";
 259         };
 260
 261         uart0: serial@11002000 {
 262                 compatible = "mediatek,mt2701-uart",
 263                              "mediatek,mt6577-uart";
 264                 reg = <0 0x11002000 0 0x400>;
 265                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 266                 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 267                 clock-names = "baud", "bus";
 268                 status = "disabled";
 269         };
 270
 271         uart1: serial@11003000 {
 272                 compatible = "mediatek,mt2701-uart",
 273                              "mediatek,mt6577-uart";
 274                 reg = <0 0x11003000 0 0x400>;
 275                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 276                 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 277                 clock-names = "baud", "bus";
 278                 status = "disabled";
 279         };
 280
 281         uart2: serial@11004000 {
 282                 compatible = "mediatek,mt2701-uart",
 283                              "mediatek,mt6577-uart";
 284                 reg = <0 0x11004000 0 0x400>;
 285                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 286                 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 287                 clock-names = "baud", "bus";
 288                 status = "disabled";
 289         };
 290
 291         uart3: serial@11005000 {
 292                 compatible = "mediatek,mt2701-uart",
 293                              "mediatek,mt6577-uart";
 294                 reg = <0 0x11005000 0 0x400>;
 295                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 296                 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 297                 clock-names = "baud", "bus";
 298                 status = "disabled";
 299         };
 300
 301         i2c0: i2c@11007000 {
 302                 compatible = "mediatek,mt2701-i2c",
 303                              "mediatek,mt6577-i2c";
 304                 reg = <0 0x11007000 0 0x70>,
 305                       <0 0x11000200 0 0x80>;
 306                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 307                 clock-div = <16>;
 308                 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
 309                 clock-names = "main", "dma";
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         i2c1: i2c@11008000 {
 316                 compatible = "mediatek,mt2701-i2c",
 317                              "mediatek,mt6577-i2c";
 318                 reg = <0 0x11008000 0 0x70>,
 319                       <0 0x11000280 0 0x80>;
 320                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 321                 clock-div = <16>;
 322                 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
 323                 clock-names = "main", "dma";
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328
 329         i2c2: i2c@11009000 {
 330                 compatible = "mediatek,mt2701-i2c",
 331                              "mediatek,mt6577-i2c";
 332                 reg = <0 0x11009000 0 0x70>,
 333                       <0 0x11000300 0 0x80>;
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 335                 clock-div = <16>;
 336                 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
 337                 clock-names = "main", "dma";
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         spi0: spi@1100a000 {
 344                 compatible = "mediatek,mt2701-spi";
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 reg = <0 0x1100a000 0 0x100>;
 348                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 349                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 350                          <&topckgen CLK_TOP_SPI0_SEL>,
 351                          <&pericfg CLK_PERI_SPI0>;
 352                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 353                 status = "disabled";
 354         };
 355
 356         thermal: thermal@1100b000 {
 357                 #thermal-sensor-cells = <0>;
 358                 compatible = "mediatek,mt2701-thermal";
 359                 reg = <0 0x1100b000 0 0x1000>;
 360                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
 361                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 362                 clock-names = "therm", "auxadc";
 363                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 364                 reset-names = "therm";
 365                 mediatek,auxadc = <&auxadc>;
 366                 mediatek,apmixedsys = <&apmixedsys>;
 367         };
 368
 369         nandc: nfi@1100d000 {
 370                 compatible = "mediatek,mt2701-nfc";
 371                 reg = <0 0x1100d000 0 0x1000>;
 372                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 373                 clocks = <&pericfg CLK_PERI_NFI>,
 374                          <&pericfg CLK_PERI_NFI_PAD>;
 375                 clock-names = "nfi_clk", "pad_clk";
 376                 status = "disabled";
 377                 ecc-engine = <&bch>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380         };
 381
 382         bch: ecc@1100e000 {
 383                 compatible = "mediatek,mt2701-ecc";
 384                 reg = <0 0x1100e000 0 0x1000>;
 385                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 386                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 387                 clock-names = "nfiecc_clk";
 388                 status = "disabled";
 389         };
 390
 391         nor_flash: spi@11014000 {
 392                 compatible = "mediatek,mt2701-nor",
 393                              "mediatek,mt8173-nor";
 394                 reg = <0 0x11014000 0 0xe0>;
 395                 clocks = <&pericfg CLK_PERI_FLASH>,
 396                          <&topckgen CLK_TOP_FLASH_SEL>;
 397                 clock-names = "spi", "sf";
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 status = "disabled";
 401         };
 402
 403         spi1: spi@11016000 {
 404                 compatible = "mediatek,mt2701-spi";
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 reg = <0 0x11016000 0 0x100>;
 408                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 409                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 410                          <&topckgen CLK_TOP_SPI1_SEL>,
 411                          <&pericfg CLK_PERI_SPI1>;
 412                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 413                 status = "disabled";
 414         };
 415
 416         spi2: spi@11017000 {
 417                 compatible = "mediatek,mt2701-spi";
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 reg = <0 0x11017000 0 0x1000>;
 421                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 422                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 423                          <&topckgen CLK_TOP_SPI2_SEL>,
 424                          <&pericfg CLK_PERI_SPI2>;
 425                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 426                 status = "disabled";
 427         };
 428
 429         afe: audio-controller@11220000 {
 430                 compatible = "mediatek,mt2701-audio";
 431                 reg = <0 0x11220000 0 0x2000>,
 432                       <0 0x112a0000 0 0x20000>;
 433                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 434                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 435                 interrupt-names = "afe", "asys";
 436                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 437
 438                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 439                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 440                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 441                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 442                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 443                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 444                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 445                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 446                          <&topckgen CLK_TOP_APLL_SEL>,
 447                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 448                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 449                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 450                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 451                          <&topckgen CLK_TOP_AUDPLL>,
 452                          <&topckgen CLK_TOP_AUDPLL_D4>,
 453                          <&topckgen CLK_TOP_AUDPLL_D8>,
 454                          <&topckgen CLK_TOP_AUDPLL_D16>,
 455                          <&topckgen CLK_TOP_AUDPLL_D24>,
 456                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 457                          <&clk26m>,
 458                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 459                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 460                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 461                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 462                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 463                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 464                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 465                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 466                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 467                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 468                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 469                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 470                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 471                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 472                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 473                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 474                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 475                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 476                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 477                          <&topckgen CLK_TOP_ASM_M_SEL>,
 478                          <&topckgen CLK_TOP_ASM_H_SEL>,
 479                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 480                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 481                          <&topckgen CLK_TOP_SYSPLL_D5>;
 482
 483                 clock-names = "infra_sys_audio_clk",
 484                          "top_audio_mux1_sel",
 485                          "top_audio_mux2_sel",
 486                          "top_audio_mux1_div",
 487                          "top_audio_mux2_div",
 488                          "top_audio_48k_timing",
 489                          "top_audio_44k_timing",
 490                          "top_audpll_mux_sel",
 491                          "top_apll_sel",
 492                          "top_aud1_pll_98M",
 493                          "top_aud2_pll_90M",
 494                          "top_hadds2_pll_98M",
 495                          "top_hadds2_pll_294M",
 496                          "top_audpll",
 497                          "top_audpll_d4",
 498                          "top_audpll_d8",
 499                          "top_audpll_d16",
 500                          "top_audpll_d24",
 501                          "top_audintbus_sel",
 502                          "clk_26m",
 503                          "top_syspll1_d4",
 504                          "top_aud_k1_src_sel",
 505                          "top_aud_k2_src_sel",
 506                          "top_aud_k3_src_sel",
 507                          "top_aud_k4_src_sel",
 508                          "top_aud_k5_src_sel",
 509                          "top_aud_k6_src_sel",
 510                          "top_aud_k1_src_div",
 511                          "top_aud_k2_src_div",
 512                          "top_aud_k3_src_div",
 513                          "top_aud_k4_src_div",
 514                          "top_aud_k5_src_div",
 515                          "top_aud_k6_src_div",
 516                          "top_aud_i2s1_mclk",
 517                          "top_aud_i2s2_mclk",
 518                          "top_aud_i2s3_mclk",
 519                          "top_aud_i2s4_mclk",
 520                          "top_aud_i2s5_mclk",
 521                          "top_aud_i2s6_mclk",
 522                          "top_asm_m_sel",
 523                          "top_asm_h_sel",
 524                          "top_univpll2_d4",
 525                          "top_univpll2_d2",
 526                          "top_syspll_d5";
 527         };
 528
 529         mmsys: syscon@14000000 {
 530                 compatible = "mediatek,mt2701-mmsys", "syscon";
 531                 reg = <0 0x14000000 0 0x1000>;
 532                 #clock-cells = <1>;
 533         };
 534
 535         bls: pwm@1400a000 {
 536                 compatible = "mediatek,mt2701-disp-pwm";
 537                 reg = <0 0x1400a000 0 0x1000>;
 538                 #pwm-cells = <2>;
 539                 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
 540                 clock-names = "main", "mm";
 541                 status = "disabled";
 542         };
 543
 544         larb0: larb@14010000 {
 545                 compatible = "mediatek,mt2701-smi-larb";
 546                 reg = <0 0x14010000 0 0x1000>;
 547                 mediatek,smi = <&smi_common>;
 548                 mediatek,larb-id = <0>;
 549                 clocks = <&mmsys CLK_MM_SMI_LARB0>,
 550                          <&mmsys CLK_MM_SMI_LARB0>;
 551                 clock-names = "apb", "smi";
 552                 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 553         };
 554
 555         imgsys: syscon@15000000 {
 556                 compatible = "mediatek,mt2701-imgsys", "syscon";
 557                 reg = <0 0x15000000 0 0x1000>;
 558                 #clock-cells = <1>;
 559         };
 560
 561         larb2: larb@15001000 {
 562                 compatible = "mediatek,mt2701-smi-larb";
 563                 reg = <0 0x15001000 0 0x1000>;
 564                 mediatek,smi = <&smi_common>;
 565                 mediatek,larb-id = <2>;
 566                 clocks = <&imgsys CLK_IMG_SMI_COMM>,
 567                          <&imgsys CLK_IMG_SMI_COMM>;
 568                 clock-names = "apb", "smi";
 569                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 570         };
 571
 572         jpegdec: jpegdec@15004000 {
 573                 compatible = "mediatek,mt2701-jpgdec";
 574                 reg = <0 0x15004000 0 0x1000>;
 575                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
 576                 clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
 577                           <&imgsys CLK_IMG_JPGDEC>;
 578                 clock-names = "jpgdec-smi",
 579                               "jpgdec";
 580                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 581                 mediatek,larb = <&larb2>;
 582                 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
 583                          <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
 584         };
 585
 586         vdecsys: syscon@16000000 {
 587                 compatible = "mediatek,mt2701-vdecsys", "syscon";
 588                 reg = <0 0x16000000 0 0x1000>;
 589                 #clock-cells = <1>;
 590         };
 591
 592         larb1: larb@16010000 {
 593                 compatible = "mediatek,mt2701-smi-larb";
 594                 reg = <0 0x16010000 0 0x1000>;
 595                 mediatek,smi = <&smi_common>;
 596                 mediatek,larb-id = <1>;
 597                 clocks = <&vdecsys CLK_VDEC_CKGEN>,
 598                          <&vdecsys CLK_VDEC_LARB>;
 599                 clock-names = "apb", "smi";
 600                 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
 601         };
 602
 603         hifsys: syscon@1a000000 {
 604                 compatible = "mediatek,mt2701-hifsys", "syscon";
 605                 reg = <0 0x1a000000 0 0x1000>;
 606                 #clock-cells = <1>;
 607         };
 608
 609         usb0: usb@1a1c0000 {
 610                 compatible = "mediatek,mt8173-xhci";
 611                 reg = <0 0x1a1c0000 0 0x1000>,
 612                       <0 0x1a1c4700 0 0x0100>;
 613                 reg-names = "mac", "ippc";
 614                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 615                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 616                          <&topckgen CLK_TOP_ETHIF_SEL>;
 617                 clock-names = "sys_ck", "ref_ck";
 618                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 619                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 620                 status = "disabled";
 621         };
 622
 623         u3phy0: usb-phy@1a1c4000 {
 624                 compatible = "mediatek,mt2701-u3phy";
 625                 reg = <0 0x1a1c4000 0 0x0700>;
 626                 #address-cells = <2>;
 627                 #size-cells = <2>;
 628                 ranges;
 629                 status = "disabled";
 630
 631                 u2port0: usb-phy@1a1c4800 {
 632                         reg = <0 0x1a1c4800 0 0x0100>;
 633                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 634                         clock-names = "ref";
 635                         #phy-cells = <1>;
 636                         status = "okay";
 637                 };
 638
 639                 u3port0: usb-phy@1a1c4900 {
 640                         reg = <0 0x1a1c4900 0 0x0700>;
 641                         clocks = <&clk26m>;
 642                         clock-names = "ref";
 643                         #phy-cells = <1>;
 644                         status = "okay";
 645                 };
 646         };
 647
 648         usb1: usb@1a240000 {
 649                 compatible = "mediatek,mt8173-xhci";
 650                 reg = <0 0x1a240000 0 0x1000>,
 651                       <0 0x1a244700 0 0x0100>;
 652                 reg-names = "mac", "ippc";
 653                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 654                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 655                          <&topckgen CLK_TOP_ETHIF_SEL>;
 656                 clock-names = "sys_ck", "ref_ck";
 657                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 658                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 659                 status = "disabled";
 660         };
 661
 662         u3phy1: usb-phy@1a244000 {
 663                 compatible = "mediatek,mt2701-u3phy";
 664                 reg = <0 0x1a244000 0 0x0700>;
 665                 #address-cells = <2>;
 666                 #size-cells = <2>;
 667                 ranges;
 668                 status = "disabled";
 669
 670                 u2port1: usb-phy@1a244800 {
 671                         reg = <0 0x1a244800 0 0x0100>;
 672                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 673                         clock-names = "ref";
 674                         #phy-cells = <1>;
 675                         status = "okay";
 676                 };
 677
 678                 u3port1: usb-phy@1a244900 {
 679                         reg = <0 0x1a244900 0 0x0700>;
 680                         clocks = <&clk26m>;
 681                         clock-names = "ref";
 682                         #phy-cells = <1>;
 683                         status = "okay";
 684                 };
 685         };
 686
 687         ethsys: syscon@1b000000 {
 688                 compatible = "mediatek,mt2701-ethsys", "syscon";
 689                 reg = <0 0x1b000000 0 0x1000>;
 690                 #clock-cells = <1>;
 691         };
 692
 693         eth: ethernet@1b100000 {
 694                 compatible = "mediatek,mt2701-eth", "syscon";
 695                 reg = <0 0x1b100000 0 0x20000>;
 696                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 697                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 698                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 699                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 700                          <&ethsys CLK_ETHSYS_ESW>,
 701                          <&ethsys CLK_ETHSYS_GP1>,
 702                          <&ethsys CLK_ETHSYS_GP2>,
 703                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 704                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 705                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 706                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 707                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 708                 reset-names = "fe", "gmac", "ppe";
 709                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 710                 mediatek,ethsys = <&ethsys>;
 711                 mediatek,pctl = <&syscfg_pctl_a>;
 712                 #address-cells = <1>;
 713                 #size-cells = <0>;
 714                 status = "disabled";
 715         };
 716
 717         bdpsys: syscon@1c000000 {
 718                 compatible = "mediatek,mt2701-bdpsys", "syscon";
 719                 reg = <0 0x1c000000 0 0x1000>;
 720                 #clock-cells = <1>;
 721         };
 722 };