Merge branch 'master' into fixes
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / mt2701-evb.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: Erin Lo <erin.lo@mediatek.com>
5  *
6  */
7
8 /dts-v1/;
9 #include "mt2701.dtsi"
10
11 / {
12         model = "MediaTek MT2701 evaluation board";
13         compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
14
15         memory {
16                 reg = <0 0x80000000 0 0x40000000>;
17         };
18
19         sound:sound {
20                 compatible = "mediatek,mt2701-cs42448-machine";
21                 mediatek,platform = <&afe>;
22                 /* CS42448 Machine name */
23                 audio-routing =
24                 "Line Out Jack", "AOUT1L",
25                 "Line Out Jack", "AOUT1R",
26                 "Line Out Jack", "AOUT2L",
27                 "Line Out Jack", "AOUT2R",
28                 "Line Out Jack", "AOUT3L",
29                 "Line Out Jack", "AOUT3R",
30                 "Line Out Jack", "AOUT4L",
31                 "Line Out Jack", "AOUT4R",
32                 "AIN1L", "AMIC",
33                 "AIN1R", "AMIC",
34                 "AIN2L", "Tuner In",
35                 "AIN2R", "Tuner In",
36                 "AIN3L", "Satellite Tuner In",
37                 "AIN3R", "Satellite Tuner In",
38                 "AIN3L", "AUX In",
39                 "AIN3R", "AUX In";
40                 mediatek,audio-codec = <&cs42448>;
41                 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
42                 pinctrl-names = "default";
43                 pinctrl-0 = <&aud_pins_default>;
44                 i2s1-in-sel-gpio1 = <&pio 53 0>;
45                 i2s1-in-sel-gpio2 = <&pio 54 0>;
46                 status = "okay";
47         };
48
49         bt_sco_codec:bt_sco_codec {
50                 compatible = "linux,bt-sco";
51         };
52
53         backlight_lcd: backlight_lcd {
54                 compatible = "pwm-backlight";
55                 pwms = <&bls 0 100000>;
56                 brightness-levels = <
57                           0  16  32  48  64  80  96 112
58                         128 144 160 176 192 208 224 240
59                         255
60                 >;
61                 default-brightness-level = <9>;
62         };
63 };
64
65 &auxadc {
66         status = "okay";
67 };
68
69 &bls {
70         status = "okay";
71         pinctrl-names = "default";
72         pinctrl-0 = <&pwm_bls_gpio>;
73 };
74
75 &i2c0 {
76         pinctrl-names = "default";
77         pinctrl-0 = <&i2c0_pins_a>;
78         status = "okay";
79 };
80
81 &i2c1 {
82         pinctrl-names = "default";
83         pinctrl-0 = <&i2c1_pins_a>;
84         status = "okay";
85 };
86
87 &i2c2 {
88         pinctrl-names = "default";
89         pinctrl-0 = <&i2c2_pins_a>;
90         status = "okay";
91         cs42448: cs42448@48 {
92                 compatible = "cirrus,cs42448";
93                 reg = <0x48>;
94                 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
95                 clock-names = "mclk";
96         };
97 };
98
99 &pio {
100         i2c0_pins_a: i2c0@0 {
101                 pins1 {
102                         pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>,
103                                  <MT2701_PIN_76_SCL0__FUNC_SCL0>;
104                         bias-disable;
105                 };
106         };
107
108         i2c1_pins_a: i2c1@0 {
109                 pins1 {
110                         pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>,
111                                  <MT2701_PIN_58_SCL1__FUNC_SCL1>;
112                         bias-disable;
113                 };
114         };
115
116         i2c2_pins_a: i2c2@0 {
117                 pins1 {
118                         pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>,
119                                  <MT2701_PIN_78_SCL2__FUNC_SCL2>;
120                         bias-disable;
121                 };
122         };
123
124         pwm_bls_gpio: pwm_bls_gpio {
125                 pins_cmd_dat {
126                         pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
127                 };
128         };
129
130         spi_pins_a: spi0@0 {
131                 pins_spi {
132                         pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
133                                  <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
134                                  <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
135                                  <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
136                         bias-disable;
137                 };
138         };
139
140         aud_pins_default: audiodefault {
141                 pins_cmd_dat {
142                         pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>,
143                                  <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>,
144                                  <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>,
145                                  <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>,
146                                  <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>,
147                                  <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>,
148                                  <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>,
149                                  <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>,
150                                  <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>,
151                                  <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>,
152                                  <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>,
153                                  <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>,
154                                  <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>,
155                                  <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>,
156                                  <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>,
157                                  <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>,
158                                  <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>,
159                                  <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>;
160                         drive-strength = <MTK_DRIVE_12mA>;
161                         bias-pull-down;
162                 };
163         };
164
165         spi_pins_b: spi1@0 {
166                 pins_spi {
167                         pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
168                                  <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
169                                  <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
170                                  <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
171                         bias-disable;
172                 };
173         };
174
175         spi_pins_c: spi2@0 {
176                 pins_spi {
177                         pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
178                                  <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
179                                  <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
180                                  <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
181                         bias-disable;
182                 };
183         };
184 };
185
186 &spi0 {
187         pinctrl-names = "default";
188         pinctrl-0 = <&spi_pins_a>;
189         status = "disabled";
190 };
191
192 &spi1 {
193         pinctrl-names = "default";
194         pinctrl-0 = <&spi_pins_b>;
195         status = "disabled";
196 };
197
198 &spi2 {
199         pinctrl-names = "default";
200         pinctrl-0 = <&spi_pins_c>;
201         status = "disabled";
202 };
203
204 &nor_flash {
205         pinctrl-names = "default";
206         pinctrl-0 = <&nor_pins_default>;
207         status = "okay";
208         flash@0 {
209                 compatible = "jedec,spi-nor";
210                 reg = <0>;
211         };
212 };
213
214 &pio {
215         nor_pins_default: nor {
216                 pins1 {
217                         pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>,
218                                  <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>,
219                                  <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>,
220                                  <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
221                                  <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
222                                  <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
223                         drive-strength = <MTK_DRIVE_4mA>;
224                         bias-pull-up;
225                 };
226         };
227 };
228
229 &uart0 {
230         status = "okay";
231 };