Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / mmp2.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (C) 2012 Marvell Technology Group Ltd.
4  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
5  */
6
7 #include <dt-bindings/clock/marvell,mmp2.h>
8
9 / {
10         #address-cells = <1>;
11         #size-cells = <1>;
12
13         aliases {
14                 serial0 = &uart1;
15                 serial1 = &uart2;
16                 serial2 = &uart3;
17                 serial3 = &uart4;
18                 i2c0 = &twsi1;
19                 i2c1 = &twsi2;
20         };
21
22         soc {
23                 #address-cells = <1>;
24                 #size-cells = <1>;
25                 compatible = "simple-bus";
26                 interrupt-parent = <&intc>;
27                 ranges;
28
29                 L2: l2-cache {
30                         compatible = "marvell,tauros2-cache";
31                         marvell,tauros2-cache-features = <0x3>;
32                 };
33
34                 axi@d4200000 {  /* AXI */
35                         compatible = "mrvl,axi-bus", "simple-bus";
36                         #address-cells = <1>;
37                         #size-cells = <1>;
38                         reg = <0xd4200000 0x00200000>;
39                         ranges;
40
41                         intc: interrupt-controller@d4282000 {
42                                 compatible = "mrvl,mmp2-intc";
43                                 interrupt-controller;
44                                 #interrupt-cells = <1>;
45                                 reg = <0xd4282000 0x1000>;
46                                 mrvl,intc-nr-irqs = <64>;
47                         };
48
49                         intcmux4: interrupt-controller@d4282150 {
50                                 compatible = "mrvl,mmp2-mux-intc";
51                                 interrupts = <4>;
52                                 interrupt-controller;
53                                 #interrupt-cells = <1>;
54                                 reg = <0x150 0x4>, <0x168 0x4>;
55                                 reg-names = "mux status", "mux mask";
56                                 mrvl,intc-nr-irqs = <2>;
57                         };
58
59                         intcmux5: interrupt-controller@d4282154 {
60                                 compatible = "mrvl,mmp2-mux-intc";
61                                 interrupts = <5>;
62                                 interrupt-controller;
63                                 #interrupt-cells = <1>;
64                                 reg = <0x154 0x4>, <0x16c 0x4>;
65                                 reg-names = "mux status", "mux mask";
66                                 mrvl,intc-nr-irqs = <2>;
67                                 mrvl,clr-mfp-irq = <1>;
68                         };
69
70                         intcmux9: interrupt-controller@d4282180 {
71                                 compatible = "mrvl,mmp2-mux-intc";
72                                 interrupts = <9>;
73                                 interrupt-controller;
74                                 #interrupt-cells = <1>;
75                                 reg = <0x180 0x4>, <0x17c 0x4>;
76                                 reg-names = "mux status", "mux mask";
77                                 mrvl,intc-nr-irqs = <3>;
78                         };
79
80                         intcmux17: interrupt-controller@d4282158 {
81                                 compatible = "mrvl,mmp2-mux-intc";
82                                 interrupts = <17>;
83                                 interrupt-controller;
84                                 #interrupt-cells = <1>;
85                                 reg = <0x158 0x4>, <0x170 0x4>;
86                                 reg-names = "mux status", "mux mask";
87                                 mrvl,intc-nr-irqs = <5>;
88                         };
89
90                         intcmux35: interrupt-controller@d428215c {
91                                 compatible = "mrvl,mmp2-mux-intc";
92                                 interrupts = <35>;
93                                 interrupt-controller;
94                                 #interrupt-cells = <1>;
95                                 reg = <0x15c 0x4>, <0x174 0x4>;
96                                 reg-names = "mux status", "mux mask";
97                                 mrvl,intc-nr-irqs = <15>;
98                         };
99
100                         intcmux51: interrupt-controller@d4282160 {
101                                 compatible = "mrvl,mmp2-mux-intc";
102                                 interrupts = <51>;
103                                 interrupt-controller;
104                                 #interrupt-cells = <1>;
105                                 reg = <0x160 0x4>, <0x178 0x4>;
106                                 reg-names = "mux status", "mux mask";
107                                 mrvl,intc-nr-irqs = <2>;
108                         };
109
110                         intcmux55: interrupt-controller@d4282188 {
111                                 compatible = "mrvl,mmp2-mux-intc";
112                                 interrupts = <55>;
113                                 interrupt-controller;
114                                 #interrupt-cells = <1>;
115                                 reg = <0x188 0x4>, <0x184 0x4>;
116                                 reg-names = "mux status", "mux mask";
117                                 mrvl,intc-nr-irqs = <2>;
118                         };
119
120                         usb_otg_phy0: usb-otg-phy@d4207000 {
121                                 compatible = "marvell,mmp2-usb-phy";
122                                 reg = <0xd4207000 0x40>;
123                                 #phy-cells = <0>;
124                                 status = "disabled";
125                         };
126
127                         usb_otg0: usb-otg@d4208000 {
128                                 compatible = "marvell,pxau2o-ehci";
129                                 reg = <0xd4208000 0x200>;
130                                 interrupts = <44>;
131                                 clocks = <&soc_clocks MMP2_CLK_USB>;
132                                 clock-names = "USBCLK";
133                                 phys = <&usb_otg_phy0>;
134                                 phy-names = "usb";
135                                 status = "disabled";
136                         };
137
138                         mmc1: mmc@d4280000 {
139                                 compatible = "mrvl,pxav3-mmc";
140                                 reg = <0xd4280000 0x120>;
141                                 clocks = <&soc_clocks MMP2_CLK_SDH0>;
142                                 clock-names = "io";
143                                 interrupts = <39>;
144                                 status = "disabled";
145                         };
146
147                         mmc2: mmc@d4280800 {
148                                 compatible = "mrvl,pxav3-mmc";
149                                 reg = <0xd4280800 0x120>;
150                                 clocks = <&soc_clocks MMP2_CLK_SDH1>;
151                                 clock-names = "io";
152                                 interrupts = <52>;
153                                 status = "disabled";
154                         };
155
156                         mmc3: mmc@d4281000 {
157                                 compatible = "mrvl,pxav3-mmc";
158                                 reg = <0xd4281000 0x120>;
159                                 clocks = <&soc_clocks MMP2_CLK_SDH2>;
160                                 clock-names = "io";
161                                 interrupts = <53>;
162                                 status = "disabled";
163                         };
164
165                         mmc4: mmc@d4281800 {
166                                 compatible = "mrvl,pxav3-mmc";
167                                 reg = <0xd4281800 0x120>;
168                                 clocks = <&soc_clocks MMP2_CLK_SDH3>;
169                                 clock-names = "io";
170                                 interrupts = <54>;
171                                 status = "disabled";
172                         };
173                 };
174
175                 apb@d4000000 {  /* APB */
176                         compatible = "mrvl,apb-bus", "simple-bus";
177                         #address-cells = <1>;
178                         #size-cells = <1>;
179                         reg = <0xd4000000 0x00200000>;
180                         ranges;
181
182                         timer0: timer@d4014000 {
183                                 compatible = "mrvl,mmp-timer";
184                                 reg = <0xd4014000 0x100>;
185                                 interrupts = <13>;
186                                 clocks = <&soc_clocks MMP2_CLK_TIMER>;
187                         };
188
189                         uart1: uart@d4030000 {
190                                 compatible = "mrvl,mmp-uart";
191                                 reg = <0xd4030000 0x1000>;
192                                 interrupts = <27>;
193                                 clocks = <&soc_clocks MMP2_CLK_UART0>;
194                                 resets = <&soc_clocks MMP2_CLK_UART0>;
195                                 status = "disabled";
196                         };
197
198                         uart2: uart@d4017000 {
199                                 compatible = "mrvl,mmp-uart";
200                                 reg = <0xd4017000 0x1000>;
201                                 interrupts = <28>;
202                                 clocks = <&soc_clocks MMP2_CLK_UART1>;
203                                 resets = <&soc_clocks MMP2_CLK_UART1>;
204                                 status = "disabled";
205                         };
206
207                         uart3: uart@d4018000 {
208                                 compatible = "mrvl,mmp-uart";
209                                 reg = <0xd4018000 0x1000>;
210                                 interrupts = <24>;
211                                 clocks = <&soc_clocks MMP2_CLK_UART2>;
212                                 resets = <&soc_clocks MMP2_CLK_UART2>;
213                                 status = "disabled";
214                         };
215
216                         uart4: uart@d4016000 {
217                                 compatible = "mrvl,mmp-uart";
218                                 reg = <0xd4016000 0x1000>;
219                                 interrupts = <46>;
220                                 clocks = <&soc_clocks MMP2_CLK_UART3>;
221                                 resets = <&soc_clocks MMP2_CLK_UART3>;
222                                 status = "disabled";
223                         };
224
225                         gpio: gpio@d4019000 {
226                                 compatible = "marvell,mmp2-gpio";
227                                 #address-cells = <1>;
228                                 #size-cells = <1>;
229                                 reg = <0xd4019000 0x1000>;
230                                 gpio-controller;
231                                 #gpio-cells = <2>;
232                                 interrupts = <49>;
233                                 interrupt-names = "gpio_mux";
234                                 clocks = <&soc_clocks MMP2_CLK_GPIO>;
235                                 resets = <&soc_clocks MMP2_CLK_GPIO>;
236                                 interrupt-controller;
237                                 #interrupt-cells = <2>;
238                                 ranges;
239
240                                 gcb0: gpio@d4019000 {
241                                         reg = <0xd4019000 0x4>;
242                                 };
243
244                                 gcb1: gpio@d4019004 {
245                                         reg = <0xd4019004 0x4>;
246                                 };
247
248                                 gcb2: gpio@d4019008 {
249                                         reg = <0xd4019008 0x4>;
250                                 };
251
252                                 gcb3: gpio@d4019100 {
253                                         reg = <0xd4019100 0x4>;
254                                 };
255
256                                 gcb4: gpio@d4019104 {
257                                         reg = <0xd4019104 0x4>;
258                                 };
259
260                                 gcb5: gpio@d4019108 {
261                                         reg = <0xd4019108 0x4>;
262                                 };
263                         };
264
265                         twsi1: i2c@d4011000 {
266                                 compatible = "mrvl,mmp-twsi";
267                                 reg = <0xd4011000 0x1000>;
268                                 interrupts = <7>;
269                                 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
270                                 resets = <&soc_clocks MMP2_CLK_TWSI0>;
271                                 #address-cells = <1>;
272                                 #size-cells = <0>;
273                                 mrvl,i2c-fast-mode;
274                                 status = "disabled";
275                         };
276
277                         twsi2: i2c@d4031000 {
278                                 compatible = "mrvl,mmp-twsi";
279                                 reg = <0xd4031000 0x1000>;
280                                 interrupt-parent = <&intcmux17>;
281                                 interrupts = <0>;
282                                 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
283                                 resets = <&soc_clocks MMP2_CLK_TWSI1>;
284                                 #address-cells = <1>;
285                                 #size-cells = <0>;
286                                 status = "disabled";
287                         };
288
289                         twsi3: i2c@d4032000 {
290                                 compatible = "mrvl,mmp-twsi";
291                                 reg = <0xd4032000 0x1000>;
292                                 interrupt-parent = <&intcmux17>;
293                                 interrupts = <1>;
294                                 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
295                                 resets = <&soc_clocks MMP2_CLK_TWSI2>;
296                                 #address-cells = <1>;
297                                 #size-cells = <0>;
298                                 status = "disabled";
299                         };
300
301                         twsi4: i2c@d4033000 {
302                                 compatible = "mrvl,mmp-twsi";
303                                 reg = <0xd4033000 0x1000>;
304                                 interrupt-parent = <&intcmux17>;
305                                 interrupts = <2>;
306                                 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
307                                 resets = <&soc_clocks MMP2_CLK_TWSI3>;
308                                 #address-cells = <1>;
309                                 #size-cells = <0>;
310                                 status = "disabled";
311                         };
312
313
314                         twsi5: i2c@d4033800 {
315                                 compatible = "mrvl,mmp-twsi";
316                                 reg = <0xd4033800 0x1000>;
317                                 interrupt-parent = <&intcmux17>;
318                                 interrupts = <3>;
319                                 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
320                                 resets = <&soc_clocks MMP2_CLK_TWSI4>;
321                                 #address-cells = <1>;
322                                 #size-cells = <0>;
323                                 status = "disabled";
324                         };
325
326                         twsi6: i2c@d4034000 {
327                                 compatible = "mrvl,mmp-twsi";
328                                 reg = <0xd4034000 0x1000>;
329                                 interrupt-parent = <&intcmux17>;
330                                 interrupts = <4>;
331                                 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
332                                 resets = <&soc_clocks MMP2_CLK_TWSI5>;
333                                 #address-cells = <1>;
334                                 #size-cells = <0>;
335                                 status = "disabled";
336                         };
337
338                         rtc: rtc@d4010000 {
339                                 compatible = "mrvl,mmp-rtc";
340                                 reg = <0xd4010000 0x1000>;
341                                 interrupts = <1 0>;
342                                 interrupt-names = "rtc 1Hz", "rtc alarm";
343                                 interrupt-parent = <&intcmux5>;
344                                 clocks = <&soc_clocks MMP2_CLK_RTC>;
345                                 resets = <&soc_clocks MMP2_CLK_RTC>;
346                                 status = "disabled";
347                         };
348
349                         ssp1: ssp@d4035000 {
350                                 compatible = "marvell,mmp2-ssp";
351                                 reg = <0xd4035000 0x1000>;
352                                 clocks = <&soc_clocks MMP2_CLK_SSP0>;
353                                 interrupts = <0>;
354                                 status = "disabled";
355                         };
356
357                         ssp2: ssp@d4036000 {
358                                 compatible = "marvell,mmp2-ssp";
359                                 reg = <0xd4036000 0x1000>;
360                                 clocks = <&soc_clocks MMP2_CLK_SSP1>;
361                                 interrupts = <1>;
362                                 status = "disabled";
363                         };
364
365                         ssp3: ssp@d4037000 {
366                                 compatible = "marvell,mmp2-ssp";
367                                 reg = <0xd4037000 0x1000>;
368                                 clocks = <&soc_clocks MMP2_CLK_SSP2>;
369                                 interrupts = <20>;
370                                 status = "disabled";
371                         };
372
373                         ssp4: ssp@d4039000 {
374                                 compatible = "marvell,mmp2-ssp";
375                                 reg = <0xd4039000 0x1000>;
376                                 clocks = <&soc_clocks MMP2_CLK_SSP3>;
377                                 interrupts = <21>;
378                                 status = "disabled";
379                         };
380                 };
381
382                 soc_clocks: clocks{
383                         compatible = "marvell,mmp2-clock";
384                         reg = <0xd4050000 0x1000>,
385                               <0xd4282800 0x400>,
386                               <0xd4015000 0x1000>;
387                         reg-names = "mpmu", "apmu", "apbc";
388                         #clock-cells = <1>;
389                         #reset-cells = <1>;
390                 };
391         };
392 };